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| to our customers, old company name in catalogs and other documents on april 1 st , 2010, nec electronics corporation merged with renesas technology corporation, and renesas electronics corporation took over all the business of both companies. therefore, although the old company name remains in this document, it is a valid renesas electronics document. we appreciate your understanding. renesas electronics website: http://www.renesas.com april 1 st , 2010 renesas electronics corporation issued by: renesas electronics corporation ( http://www.renesas.com ) send any inquiries to http://www.renesas.com/inquiry .
notice 1. all information included in this document is current as of the date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas electronics products listed herein, please confirm the latest product information with a renesas electronics sales office. also, please pay regular and careful attention to additional and different information to be disclosed by renesas electronics such as that disclosed through our website. 2. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electronics products or technical information described in this document . no license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property right s of renesas electronics or others. 3. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part . 4. descriptions of circuits, software and other related information in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. when exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. you should not use renesas electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. renesas electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 6. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. 7. renesas electronics products are classified according to the following three quality grades: ?standard?, ?high quality?, an d ?specific?. the recommended applications for each renesas electronics product depends on the product?s quality grade, as indicated below. you must check the quality grade of each renesas electronics product before using it in a particular application. you may not use any renesas electronics product for any application categorized as ?specific? without the prior written consent of renesas electronics. further, you may not use any renesas electronics product for any application for which it is not intended without the prior written consent of renesas electronics. renesas electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any renesas electronics product for a n application categorized as ?specific? or for which the product is not intended where you have failed to obtain the prior writte n consent of renesas electronics. the quality grade of each renesas electronics product is ?standard? unless otherwise expressly specified in a renesas electronics data sheets or data books, etc. ?standard?: computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. ?high quality?: transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; an ti- crime systems; safety equipment; and medical equipment not specifically designed for life support. ?specific?: aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life. 8. you should use the renesas electronics products described in this document within the range specified by renesas electronics , especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas electronics shall have no liability for malfunctions o r damages arising out of the use of renesas electronics products beyond such specified ranges. 9. although renesas electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. fur ther, renesas electronics products are not subject to radiation resistance design. please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 10. please contact a renesas electronics sales office for details as to environmental matters such as the environmental compatibility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the eu rohs directive. renesas electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of renes as electronics. 12. please contact a renesas electronics sales office if you have any questions regarding the information contained in this document or renesas electronics products, or if you have any other inquiries. (note 1) ?renesas electronics? as used in this document means renesas electronics corporation and also includes its majority- owned subsidiaries. (note 2) ?renesas electronics product(s)? means any product developed or manufactured by or for renesas electronics. h8s/2612 group, h8s/2612 f-ztat hardware manual 16 users manual rev.7.00 2009.09 renesas 16-bit single-chip microcomputer h8s family/h8s/2600 series rev. 7.00 sep. 11, 2009 page ii of xxxiv rej09b0211-0700 1. this document is provided for reference purposes only so that renesas customers may select the appropriate renesas products for their use. renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor g rants any license to any intellectual property ri g hts or any other ri g hts of renesas or any third party with respect to the information in this document. 2. renesas shall have no liability for dama g es or infrin g ement of any intellectual property or other ri g hts arisin g out of the use of any information in this document, includin g , but not limited to, product data, dia g rams, charts, pro g rams, al g orithms, and application circuit examples. 3. you should not use the products or the technolo g y described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. when exportin g the products or technolo g y described herein, you should follow the applicable export control laws and re g ulations, and procedures required by such laws and re g ulations. 4. all information included in this document such as product data, dia g rams, charts, pro g rams, al g orithms, and application circuit examples, is current as of the date this document is issued. such information, however, is subject to chan g e without any prior notice. before purchasin g or usin g any renesas products listed in this document, please confirm the latest product information with a renesas sales office. also, please pay re g ular and careful attention to additional and different information to be disclosed by renesas such as that disclosed throu g h our website. (http://www.renesas.com ) 5. renesas has used reasonable care in compilin g the information included in this document, but renesas assumes no liability whatsoever for any dama g es incurred as a result of errors or omissions in the information included in this document. 6. when usin g or otherwise relyin g on the information in this document, you should evaluate the information in li g ht of the total system before decidin g about the applicability of such information to the intended application. renesas makes no representations, warranties or g uaranties re g ardin g the suitability of its products for any particular application and specifically disclaims any liability arisin g out of the application and use of the information in this document or renesas products. 7. with the exception of products specified by renesas as suitable for automobile applications, renesas products are not desi g ned, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially hi g h quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. if you are considerin g the use of our products for such purposes, please contact a renesas sales office beforehand. renesas shall have no liability for dama g es arisin g out of the uses set forth above. 8. notwithstandin g the precedin g para g raph, you should not use renesas products for the purposes listed below: (1) artificial life support devices or systems (2) sur g ical implantations (3) healthcare intervention (e. g ., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life renesas shall have no liability for dama g es arisin g out of the uses set forth in the above and purchasers who elect to use renesas products in any of the fore g oin g applications shall indemnify and hold harmless renesas technolo g y corp., its affiliated companies and their officers, directors, and employees a g ainst any and all dama g es arisin g out of such applications. 9. you should use the products described herein within the ran g e specified by renesas, especially with respect to the maximum ratin g , operatin g supply volta g e ran g e, movement power volta g e ran g e, heat radiation characteristics, installation and other product characteristics. renesas shall have no liability for malfunctions or dama g es arisin g out of the use of renesas products beyond such specified ran g es. 10. althou g h renesas endeavors to improve the quality and reliability of its products, ic products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. please be sure to implement safety measures to g uard a g ainst the possibility of physical injury, and injury or dama g e caused by fire in the event of the failure of a renesas product, such as safety desi g n for hardware and software includin g but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for a g in g de g radation or any other applicable measures. amon g others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. in case renesas products listed in this document are detached from the products to which the renesas products are attached or affixed, the risk of accident such as swallowin g by infants and small children is very hi g h. you should implement safety measures so that renesas products may not be easily detached from your products. renesas shall have no liability for dama g es arisin g out of such detachment. 12. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from renesas. 13. please contact a renesas sales office if you have any questions re g ardin g the information contained in this document, renesas semiconductor products, or if you have any other inquiries. notes re g ardin g these materials rev. 7.00 sep. 11, 2009 page iii of xxxiv rej09b0211-0700 general precautions in the handling of mpu/mcu products the following usage notes are applicable to all mpu/mcu products from renesas. for detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. if the descriptions under general precautions in the handling of mpu/mcu products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. handling of unused pins handle unused pins in accord with the directions given under handling of unused pins in the manual. ? the input pins of cmos products are generally in the high-impedance state. in operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of lsi, an associated shoot-through current flows internally, and malfunctions may occur due to the false recognition of the pin state as an input signal. unused pins should be handled as described under handling of unused pins in the manual. 2. processing at power-on the state of the product is undefined at the moment when power is supplied. ? the states of internal circuits in the lsi are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. in a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. in a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. prohibition of access to reserved addresses access to reserved addresses is prohibited. ? the reserved addresses are provided for the possible future expansion of functions. do not access these addresses; the correct operation of lsi is not guaranteed if they are accessed. 4. clock signals after applying a reset, only release the reset line after the operating clock signal has become stable. when switching the clock signal during program execution, wait until the target clock signal has stabilized. ? when the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. differences between products before changing from one product to another, i.e. to one with a different type number, confirm that the change will not lead to problems. ? the characteristics of mpu/mcu in the same group but having different type numbers may differ because of the differences in internal memory capacity and layout pattern. when changing to products of different type numbers, implement a system-evaluation test for each of the products. rev. 7.00 sep. 11, 2009 page iv of xxxiv rej09b0211-0700 configuration of this manual this manual comprises the following items: 1. general precautions in the handling of mpu/mcu products 2. configuration of this manual 3. preface 4. main revisions for this edition 5. contents 6. overview 7. description of functional modules ? cpu and system-control modules ? on-chip peripheral modules the configuration of the functional descrip tion of each module differs according to the module. however, the generic style includes the following items: i) feature ii) input/output pin iii) register description iv) operation v) usage note when designing an application system that includes this lsi, take notes into account. each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 8. electrical characteristics 9. appendix 10. index rev. 7.00 sep. 11, 2009 page v of xxxiv rej09b0211-0700 preface the h8s/2612 group are single-chip microcomputers made up of the high-speed h8s/2600 cpu as its core, and the peripheral functions required to configure a system. the h8s/2600 cpu has an instruction set that is compatible with the h8/300 and h8/300h cpus. this lsi is equipped with a data transfer controller (dtc), rom and ram, a pc break controller (pbc), a 16-bit timer pulse unit (tpu), a motor management timer (mmt), a programmable pulse generator (ppg), a watchdog timer (wdt), a se rial communication interf ace (sci), a controller area network (hcan), an a/d converter, and i/o ports as on-chip peripheral modules required for system configuration. this lsi is suitable for use as an embedded microcomputer for high-level control systems. a single-power flash memory (f-ztat tm ) version is available for this lsi?s rom. this provides flexibility as it can be reprogrammed in no time to cope with all situations from the early stages of mass production to full-scale mass production. this is particularly applicable to application devices with specifications that will most probably change. notes: f-ztat is a trademark of renesas technology, corp. mmt, ppg, pc break controller, and dtc are not implemented in the h8s/2614 and h8s/2616. target users: this manual was written for user s who will be using the h8s/2612 group in the design of application systems. target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. objective: this manual was written to explain the hardware functions and electrical characteristics of the h8s/2612 group to the target users. refer to the h8s/2600 series, h8s/2000 series software manual for a detailed description of the instruction set. notes on reading this manual: ? in order to understand the overall functions of the chip read the manual according to the contents. this manual can be roughly categorized into parts on the cpu, system control functions, peripher al functions and elect rical characteristics. ? in order to understand the details of the cpu?s functions read the h8s/2600 series, h8s/2000 series software manual. rev. 7.00 sep. 11, 2009 page vi of xxxiv rej09b0211-0700 ? in order to understand the details of a register when its name is known read the index that is the final part of the manual to find the page number of the entry on the register. the addresses, bits, and initial values of the registers are summarized in appendix a, on-chip i/o register. examples: register name: the following notatio n is used for cases when the same or a similar function, e.g. 16-bit timer pulse unit or serial communication, is implemente d on more than one channel: xxx_n (xxx is the register name and n is the channel number) bit order: the msb is on the left and the lsb is on the right. number notation: binary is b'xxxx, hexadecimal is h'xxxx, decimal is xxxx. signal notation: an overbar is added to a low-active signal: xxxx related manuals: the latest versions of all related manuals are available from our web site. please ensure you have the latest versions of all documents you require. http://www.renesas.com/eng/ h8s/2612 group manuals: document title document no. h8s/2612 group, h8s/2612 f-ztat hardware manual this manual h8s/2600 series, h8s/2000 series software manual rej09b0139 user?s manuals for development tools: document title document no. h8s, h8/300 series c/c++ compiler, assembler, optimizing linkage editor user?s manual rej10b0161 h8s, h8/300 series simulator/debugger user?s manual rej10b0211 high-performance embedded workshop user?s manual rej10j2000 rev. 7.00 sep. 11, 2009 page vii of xxxiv rej09b0211-0700 main revisions for this edition item page revision (see manual for details) 8.5.7 number of dtc execution states 122 equation amended number of execution states = i s i + (j s j + k s k + l s l ) + m s m 14.7.6 data transmission (except for block transfer mode) figure 14.26 retransfer operation in sci transmit mode 370 figure amended tend [1] fer/ers [2] [3] [3] 14.7.7 serial data reception (except for block transfer mode) figure 14.29 retransfer operation in sci receive mode 371 figure amended rdrf [1] per [2] [3] [3] 14.7.8 clock output control figure 14.32 clock halt and restart procedure 374 figure amended [1] [2] [3] [4] [5] [2] [1] 15.4.2 initialization after hardware reset figure 15.8 detailed description of one bit 415 figure amended sync_seg prseg phseg1 phseg2 time segment 2 (tseg2) time segment 1 (tseg1) 1-bit time (8 to 25 time quanta) 4 to 16 time quanta 2 to 8 time quanta 1 time quantum 15.8.11 hcan transmit procedure 433 newly added 15.8.12 note on releasing the hcan reset or hcan sleep newly added 15.8.13 note on accessing mailbox during the hcan sleep newly added rev. 7.00 sep. 11, 2009 page viii of xxxiv rej09b0211-0700 item page revision (see manual for details) 18.8.3 interrupt handling when programming/erasing flash memory figure 18.10 erase/erase-verify flowchart 473 figure amended erase start set ebr1 and ebr2 enable wdt disable wdt read verify data set block start address as verify address h'ff dummy write to verify address swe bit 1 n 1 esu bit 1 e bit 1 wait 1 s wait 100 s e bit 0 ev bit 1 wait 10 ms esu bit 0 wait 10 s wait 10 s wait 20 s n n + 1 wait 2 s all trademarks and registered trademarks are the property of their respective owners. rev. 7.00 sep. 11, 2009 page ix of xxxiv rej09b0211-0700 contents section 1 overview................................................................................................1 1.1 overview....................................................................................................................... ......... 1 1.2 internal block diagram..................................................................................................... ..... 3 1.3 pin arrangement ............................................................................................................ ........ 5 1.4 pin functions .................................................................................................................. ....... 7 1.5 differences between h8s/2612, h8 s/2611, h8s/2614, and h8s/2616............................... 12 section 2 cpu......................................................................................................13 2.1 features ....................................................................................................................... ......... 13 2.1.1 differences between h8s/2600 cpu and h8s/2000 cpu ..................................... 14 2.1.2 differences from h8/300 cpu ............................................................................... 15 2.1.3 differences from h8/300h cpu............................................................................. 15 2.2 cpu operating modes ........................................................................................................ . 16 2.2.1 normal mode .......................................................................................................... 16 2.2.2 advan ced m ode...................................................................................................... 17 2.3 address space.............................................................................................................. ........ 20 2.4 register configuration..................................................................................................... .... 21 2.4.1 general registers .................................................................................................... 22 2.4.2 program counter (pc) ............................................................................................ 23 2.4.3 extended control register (exr) .......................................................................... 23 2.4.4 condition-code register (ccr) ............................................................................. 24 2.4.5 multiply-accumulate register (mac) ................................................................... 26 2.4.6 initial values of cpu registers .............................................................................. 26 2.5 data formats............................................................................................................... ......... 27 2.5.1 general register data formats ............................................................................... 27 2.5.2 memory data formats ............................................................................................ 29 2.6 instruction set ............................................................................................................ .......... 30 2.6.1 table of instructions classified by function .......................................................... 31 2.6.2 basic instruction formats ....................................................................................... 40 2.7 addressing modes and effect ive address calculation ........................................................ 42 2.7.1 register direct?rn................................................................................................ 42 2.7.2 register indirect?@ern ....................................................................................... 42 2.7.3 register indirect with displacem ent?@(d:16, ern) or @(d:32, ern)................. 43 2.7.4 register indirect with post-increme nt or pre-decrement?@ern+ or @-ern ..... 43 2.7.5 absolute address?@aa:8, @aa:16, @aa:24, or @aa:32....................................... 43 2.7.6 immediate?#xx:8, #xx:16, or #xx:32 .................................................................... 44 2.7.7 program-counter relative?@(d:8, pc) or @(d:16, pc)....................................... 44 2.7.8 memory indirect?@@aa:8 ................................................................................... 44 2.7.9 effective address calculation ................................................................................ 45 rev. 7.00 sep. 11, 2009 page x of xxxiv rej09b0211-0700 2.8 processing states.............................................................................................................. .... 48 2.9 usage notes .................................................................................................................... ..... 49 2.9.1 usage notes on bit manipulation instructions ....................................................... 49 section 3 mcu operating modes .......................................................................51 3.1 operating mode selection ................................................................................................... 51 3.2 register descriptions .......................................................................................................... .51 3.2.1 mode control register (mdcr) ............................................................................ 52 3.2.2 system control register (syscr) ......................................................................... 53 3.3 pin functions in each operating mode ............................................................................... 54 3.3.1 pin functions .......................................................................................................... 54 3.4 address map .................................................................................................................... .... 55 section 4 exception handling .............................................................................57 4.1 exception handling types and priority ............................................................................... 57 4.2 exception sources and exception vector table .................................................................. 57 4.3 reset.......................................................................................................................... ........... 59 4.3.1 reset exception handling....................................................................................... 59 4.3.2 interrupts after reset............................................................................................... 61 4.3.3 state of on-chip supporting m odules after reset release .................................... 61 4.4 traces......................................................................................................................... .......... 62 4.5 interrupts ..................................................................................................................... ......... 62 4.6 trap instruction............................................................................................................... ..... 63 4.7 stack status after exception handling................................................................................. 64 4.8 usage note..................................................................................................................... ...... 65 section 5 interrupt controller..............................................................................67 5.1 features ....................................................................................................................... ......... 67 5.2 input/output pins .............................................................................................................. ... 69 5.3 register descriptions .......................................................................................................... .69 5.3.1 interrupt priority registers a to h, j, k, m (ipra to iprh,iprj, iprk, iprm) ....................................................................... 70 5.3.2 irq enable register (ier) ..................................................................................... 71 5.3.3 irq sense control registers h and l (iscrh, iscrl)........................................ 71 5.3.4 irq status register (isr)....................................................................................... 74 5.4 interrupt ...................................................................................................................... ......... 75 5.4.1 external interrupts .................................................................................................. 75 5.4.2 internal interrupts.................................................................................................... 76 5.5 interrupt exception handling vector table......................................................................... 76 5.6 interrupt control modes and interrupt operation ................................................................ 79 5.6.1 interrupt control mode 0 ........................................................................................ 79 rev. 7.00 sep. 11, 2009 page xi of xxxiv rej09b0211-0700 5.6.2 interrupt control mode 2 ........................................................................................ 81 5.6.3 interrupt exception handling sequence ................................................................. 83 5.6.4 interrupt res ponse times ....................................................................................... 85 5.6.5 dtc activation by interrupt................................................................................... 86 5.7 usage notes .................................................................................................................... ..... 86 5.7.1 contention between interrupt generation and disabling........................................ 86 5.7.2 instructions that di sable interrupts ......................................................................... 87 5.7.3 when interrupts are disabled ................................................................................. 87 5.7.4 interrupts during execution of eepmov instruction............................................. 88 section 6 pc break controller (pbc) .................................................................89 6.1 features ....................................................................................................................... ......... 89 6.2 register descriptions .......................................................................................................... .90 6.2.1 break address register a (bara) ........................................................................ 90 6.2.2 break address register b (barb)......................................................................... 91 6.2.3 break control register a (bcra) ......................................................................... 91 6.2.4 break control register b (bcrb).......................................................................... 92 6.3 operation...................................................................................................................... ........ 92 6.3.1 pc break interrupt due to instruction fetch .......................................................... 92 6.3.2 pc break interrupt due to data access.................................................................. 92 6.3.3 notes on pc break interrupt handling ................................................................... 93 6.3.4 operation in transitions to power-down modes ................................................... 93 6.3.5 when instruction execution is delayed by one state ............................................ 94 6.4 usage notes .................................................................................................................... ..... 95 6.4.1 module stop mode setting ..................................................................................... 95 6.4.2 pc break interrupts................................................................................................. 95 6.4.3 cmfa and cmfb .................................................................................................. 95 6.4.4 pc break interrupt when dtc is bus master......................................................... 95 6.4.5 pc break set for instruction fetch at address following bsr, jsr, jmp, trapa, rte, or rts instruction .......................................................................... 95 6.4.6 i bit set by ldc, andc, orc, or xorc instruction .......................................... 95 6.4.7 pc break set for instruction fetch at address following bcc instruction............. 96 6.4.8 pc break set for instruction fetch at branch destination address of bcc instruction ............................................................................................................... 96 section 7 bus controller......................................................................................97 7.1 basic timing................................................................................................................... ..... 97 7.1.1 on-chip memory access timing (rom, ram) ................................................... 97 7.1.2 on-chip support modu le access timing............................................................... 98 7.1.3 on-chip hcan module access timing................................................................ 99 7.1.4 on-chip mmt module access timing................................................................ 100 rev. 7.00 sep. 11, 2009 page xii of xxxiv rej09b0211-0700 7.2 bus arbitration................................................................................................................ ... 101 7.2.1 order of priority of the bus masters..................................................................... 101 7.2.2 bus transfer timing ............................................................................................. 101 section 8 data transfer controller (dtc) ........................................................103 8.1 features ....................................................................................................................... ....... 103 8.2 register configuration....................................................................................................... 10 5 8.2.1 dtc mode register a (mra) ............................................................................. 106 8.2.2 dtc mode register b (mrb).............................................................................. 107 8.2.3 dtc source address register (sar)................................................................... 107 8.2.4 dtc destination address register (dar)........................................................... 107 8.2.5 dtc transfer count register a (cra) ............................................................... 107 8.2.6 dtc transfer count re gister b (crb)................................................................ 108 8.2.7 dtc enable registers (dtcer) .......................................................................... 108 8.2.8 dtc vector register (dtvecr)......................................................................... 109 8.3 activation sources ............................................................................................................. 109 8.4 location of register informa tion and dtc vector table ................................................. 110 8.5 operation...................................................................................................................... ...... 114 8.5.1 normal mode........................................................................................................ 115 8.5.2 repeat mode ......................................................................................................... 116 8.5.3 block transfer mode ............................................................................................ 117 8.5.4 chain transfer ...................................................................................................... 119 8.5.5 interrupts............................................................................................................... 120 8.5.6 operation timing.................................................................................................. 120 8.5.7 number of dtc execution states ........................................................................ 121 8.6 procedures for using dtc................................................................................................. 123 8.6.1 activation by interrupt.......................................................................................... 123 8.6.2 activation by software ......................................................................................... 123 8.7 examples of use of the dtc ............................................................................................. 123 8.7.1 normal mode........................................................................................................ 123 8.7.2 chain transfer ...................................................................................................... 124 8.7.3 software activation .............................................................................................. 125 8.8 usage notes .................................................................................................................... ... 126 8.8.1 module stop mode setting ................................................................................... 126 8.8.2 on-chip ram ...................................................................................................... 126 8.8.3 dtce bit setting.................................................................................................. 126 section 9 i/o ports.............................................................................................127 9.1 port 1......................................................................................................................... ......... 130 9.1.1 port 1 data direction register (p1ddr).............................................................. 130 9.1.2 port 1 data register (p1dr)................................................................................. 131 rev. 7.00 sep. 11, 2009 page xiii of xxxiv rej09b0211-0700 9.1.3 port 1 register (port1)....................................................................................... 131 9.1.4 pin functions ........................................................................................................ 132 9.2 port 4......................................................................................................................... ......... 135 9.2.1 port 4 register (port4)....................................................................................... 135 9.3 port 9......................................................................................................................... ......... 136 9.3.1 port 9 register (port9)....................................................................................... 136 9.4 port a......................................................................................................................... ........ 137 9.4.1 port a data directi on register (paddr) ............................................................ 137 9.4.2 port a data register (padr)............................................................................... 138 9.4.3 port a register (porta) ..................................................................................... 138 9.4.4 port a pull-up mos control register (papcr) ................................................. 139 9.4.5 port a open-drain control register (paodr) ................................................... 139 9.4.6 pin functions ........................................................................................................ 140 9.5 port b ......................................................................................................................... ........ 141 9.5.1 port b data direction register (pbddr) ............................................................ 141 9.5.2 port b data register (pbdr) ............................................................................... 142 9.5.3 port b register (portb) ..................................................................................... 142 9.5.4 port b pull-up mos contro l register (pbpcr).................................................. 143 9.5.5 port b open-drain control register (pbodr).................................................... 143 9.5.6 pin functions ........................................................................................................ 144 9.6 port c ......................................................................................................................... ........ 147 9.6.1 port c data direction register (pcddr) ............................................................ 147 9.6.2 port c data register (pcdr) ............................................................................... 148 9.6.3 port c register (portc) ..................................................................................... 148 9.6.4 port c pull-up mos contro l register (pcpcr).................................................. 149 9.6.5 port c open-drain control register (pcodr).................................................... 149 9.6.6 pin functions ........................................................................................................ 150 9.7 port d......................................................................................................................... ........ 152 9.7.1 port d data directi on register (pdddr) ............................................................ 152 9.7.2 port d data register (pddr)............................................................................... 153 9.7.3 port d register (portd) ..................................................................................... 153 9.7.4 port d pull-up mos control register (pdpcr) ................................................. 154 9.8 port f......................................................................................................................... ......... 155 9.8.1 port f data direction register (pfddr) ............................................................. 155 9.8.2 port f data regi ster (pfdr) ................................................................................ 156 9.8.3 port f register (portf) ...................................................................................... 156 9.8.4 pin functions ........................................................................................................ 157 section 10 16-bit timer pulse unit (tpu)........................................................159 10.1 features ....................................................................................................................... ....... 159 10.2 input/output pins .............................................................................................................. . 163 rev. 7.00 sep. 11, 2009 page xiv of xxxiv rej09b0211-0700 10.3 register descriptions ......................................................................................................... 1 64 10.3.1 timer control register (tcr).............................................................................. 166 10.3.2 timer mode register (tmdr) ............................................................................. 171 10.3.3 timer i/o control register (tior) ...................................................................... 173 10.3.4 timer interrupt enable register (tier) ............................................................... 190 10.3.5 timer status register (tsr)................................................................................. 192 10.3.6 timer counter (tcnt)......................................................................................... 195 10.3.7 timer general register (tgr) ............................................................................. 195 10.3.8 timer start register (tstr)................................................................................. 195 10.3.9 timer synchro register (tsyr) .......................................................................... 196 10.4 operation...................................................................................................................... ...... 197 10.4.1 basic functions..................................................................................................... 197 10.4.2 synchronous op eration......................................................................................... 203 10.4.3 buffer operation ................................................................................................... 205 10.4.4 cascaded operation .............................................................................................. 209 10.4.5 pwm modes ......................................................................................................... 211 10.4.6 phase counting mode ........................................................................................... 216 10.5 interrupts ..................................................................................................................... ....... 223 10.6 dtc activation................................................................................................................. . 225 10.7 a/d converter activation.................................................................................................. 225 10.8 operation timing............................................................................................................... 226 10.8.1 input/output timing ............................................................................................. 226 10.8.2 interrupt signal timing......................................................................................... 230 10.9 usage notes .................................................................................................................... ... 234 10.9.1 module stop mode setting ................................................................................... 234 10.9.2 input clock re strictions ....................................................................................... 234 10.9.3 caution on period setting ..................................................................................... 234 10.9.4 contention between tcnt write and clear operations...................................... 235 10.9.5 contention between tcnt write and increment operations............................... 236 10.9.6 contention between tgr write and compare match .......................................... 237 10.9.7 contention between buffer register write and compare match ......................... 238 10.9.8 contention between tgr read and input capture............................................... 239 10.9.9 contention between tgr write and input capture.............................................. 240 10.9.10 contention between buffer register write and input capture ............................. 241 10.9.11 contention between overflow/underflow and counter clearing......................... 242 10.9.12 contention between tcnt write and overflow/underflow................................ 243 10.9.13 multiplexing of i/o pins ....................................................................................... 243 10.9.14 interrupts in modul e stop mode........................................................................... 243 section 11 motor mana gement timer (mmt) .................................................245 11.1 features ....................................................................................................................... ....... 245 rev. 7.00 sep. 11, 2009 page xv of xxxiv rej09b0211-0700 11.2 input/output pins .............................................................................................................. . 247 11.3 register descriptions ......................................................................................................... 2 47 11.3.1 timer mode register (tmdr) ............................................................................. 248 11.3.2 timer control register (tcnr) ........................................................................... 249 11.3.3 timer status register (tsr)................................................................................. 250 11.3.4 timer counter (tcnt)......................................................................................... 250 11.3.5 timer buffer registers (tbr) .............................................................................. 251 11.3.6 timer general registers (tgr)............................................................................ 251 11.3.7 timer dead time counters (tdcnt).................................................................. 251 11.3.8 timer dead time data register (tddr)............................................................. 251 11.3.9 timer period buffer register (tpbr) .................................................................. 251 11.3.10 timer period data register (tpdr)..................................................................... 251 11.3.11 mmt pin control register (mmtpc) ................................................................. 252 11.4 operation...................................................................................................................... ...... 253 11.4.1 sample setting procedure ..................................................................................... 254 11.4.2 output protecti on functions ................................................................................. 262 11.5 interrupts ..................................................................................................................... ....... 263 11.6 operation timing............................................................................................................... 264 11.6.1 input/output timing ............................................................................................. 264 11.6.2 interrupt signal timing......................................................................................... 268 11.7 usage notes .................................................................................................................... ... 270 11.7.1 module stop mode setting ................................................................................... 270 11.7.2 notes for mmt operation .................................................................................... 270 11.8 port output enable (poe).................................................................................................. 274 11.8.1 features................................................................................................................. 274 11.8.2 input/output pins .................................................................................................. 275 11.8.3 register descriptions ............................................................................................ 275 11.8.4 operation .............................................................................................................. 279 section 12 programmable pulse generator (ppg) ............................................281 12.1 features ....................................................................................................................... ....... 281 12.2 input/output pins .............................................................................................................. . 283 12.3 register descriptions ......................................................................................................... 2 83 12.3.1 next data enable registers h, l (nderh, nderl).......................................... 284 12.3.2 output data registers h, l (podrh, podrl)................................................... 285 12.3.3 next data registers h, l (ndrh, ndrl) .......................................................... 286 12.3.4 ppg output control register (pcr)..................................................................... 289 12.3.5 ppg output mode re gister (pmr)....................................................................... 290 12.4 operation...................................................................................................................... ...... 291 12.4.1 overview............................................................................................................... 291 12.4.2 output timing....................................................................................................... 292 rev. 7.00 sep. 11, 2009 page xvi of xxxiv rej09b0211-0700 12.4.3 sample setup procedure for normal pulse output............................................... 293 12.4.4 example of normal pulse output (examp le of five-phase pulse output)........... 294 12.4.5 non-overlapping pulse output............................................................................. 295 12.4.6 sample setup procedure for n on-overlapping pulse output ............................... 297 12.4.7 example of non-overlapping pulse output (example of four-phase compleme ntary non-overlapping output)................... 298 12.4.8 inverted pulse output ........................................................................................... 300 12.4.9 pulse output triggered by input capture ............................................................. 301 12.5 usage notes .................................................................................................................... ... 301 12.5.1 module stop mode setting ................................................................................... 301 12.5.2 operation of pulse output pins............................................................................. 301 section 13 watchdog timer ..............................................................................303 13.1 features ....................................................................................................................... ....... 303 13.2 register descriptions ......................................................................................................... 3 04 13.2.1 timer counter (tcnt)......................................................................................... 304 13.2.2 timer control/status register (tcsr)................................................................. 305 13.2.3 reset control/status register (rstcsr) ............................................................. 307 13.3 operation...................................................................................................................... ...... 308 13.3.1 watchdog time r mode ......................................................................................... 308 13.3.2 interval timer mode ............................................................................................. 308 13.4 interrupts ..................................................................................................................... ....... 309 13.5 usage notes .................................................................................................................... ... 309 13.5.1 notes on register access...................................................................................... 309 13.5.2 contention between timer counter (tcnt) write and increment ...................... 310 13.5.3 changing value of cks2 to cks0....................................................................... 311 13.5.4 switching between watchdog timer mode and interval timer mode................. 311 13.5.5 internal reset in watchdog time r mode.............................................................. 311 13.5.6 ovf flag clearing in intervel timer mode ......................................................... 311 section 14 serial communication interface (sci) ............................................313 14.1 features ....................................................................................................................... ....... 313 14.2 input/output pins .............................................................................................................. . 315 14.3 register descriptions ......................................................................................................... 3 15 14.3.1 receive shift register (rsr) ............................................................................... 316 14.3.2 receive data register (rdr) ............................................................................... 316 14.3.3 transmit data register (tdr).............................................................................. 316 14.3.4 transmit shift register (tsr) .............................................................................. 316 14.3.5 serial mode register (smr)................................................................................. 317 14.3.6 serial control re gister (scr)............................................................................... 321 14.3.7 serial status register (ssr) ................................................................................. 324 rev. 7.00 sep. 11, 2009 page xvii of xxxiv rej09b0211-0700 14.3.8 smart card mode register (scmr) ..................................................................... 330 14.3.9 bit rate register (brr) ....................................................................................... 331 14.4 operation in async hronous mode ..................................................................................... 338 14.4.1 data transfer format............................................................................................ 338 14.4.2 receive data sampling timing and reception margin in asynchronous mode ..................................................................................................................... 340 14.4.3 clock..................................................................................................................... 341 14.4.4 sci initialization (as ynchronous mode) .............................................................. 342 14.4.5 data transmission (as ynchronous mode)............................................................ 343 14.4.6 serial data reception (a synchronous mode)....................................................... 345 14.5 multiprocessor communication function.......................................................................... 349 14.5.1 multiprocessor serial da ta transmission ............................................................. 350 14.5.2 multiprocessor serial data reception .................................................................. 352 14.6 operation in clocked synchronous mode ......................................................................... 355 14.6.1 clock..................................................................................................................... 355 14.6.2 sci initialization (clocked synchronous mode) .................................................. 356 14.6.3 serial data transmission (clo cked synchron ous mode ) ..................................... 357 14.6.4 serial data reception (clock ed synchronous mode)........................................... 360 14.6.5 simultaneous serial data transmission and reception (clocked synchr onous m ode) .............................................................................. 362 14.7 operation in smart card interface ..................................................................................... 364 14.7.1 pin connection example....................................................................................... 364 14.7.2 data format (except for block transfer mode)................................................... 365 14.7.3 block transfer mode ............................................................................................ 366 14.7.4 receive data sampling timing and receptio n margin in smart card interface mode ..................................................................................................................... 367 14.7.5 initialization .......................................................................................................... 368 14.7.6 data transmission (except for block transfer mode)......................................... 369 14.7.7 serial data reception (except for block transfer mode) .................................... 371 14.7.8 clock output control............................................................................................ 373 14.8 interrupts ..................................................................................................................... ....... 375 14.8.1 interrupts in normal serial communication interface mode................................ 375 14.8.2 interrupts in smart card interface mode .............................................................. 376 14.9 usage notes .................................................................................................................... ... 377 14.9.1 module stop mode setting ................................................................................... 377 14.9.2 break detection and processing ........................................................................... 377 14.9.3 mark state and break detection ........................................................................... 377 14.9.4 receive error flags and transmit operations (clocked synchron ous mode only)...................................................................... 377 14.9.5 restrictions on using dtc ................................................................................... 378 14.9.6 sci operations during mode transitions ............................................................. 378 rev. 7.00 sep. 11, 2009 page xviii of xxxiv rej09b0211-0700 14.9.7 notes when switching from sck pin to port pin................................................. 381 section 15 controller area network (hcan) ..................................................383 15.1 features ....................................................................................................................... ....... 383 15.2 input/output pins .............................................................................................................. . 385 15.3 register descriptions ......................................................................................................... 3 85 15.3.1 master control register (mcr) ........................................................................... 386 15.3.2 general status register (gsr) ............................................................................. 387 15.3.3 bit configuration register (bcr) ........................................................................ 389 15.3.4 mailbox configuration register (mbcr) ............................................................ 391 15.3.5 transmit wait register (txpr) ........................................................................... 392 15.3.6 transmit wait cancel register (txcr)............................................................... 393 15.3.7 transmit acknowledge register (txack) ......................................................... 394 15.3.8 abort acknowledge register (aback) .............................................................. 395 15.3.9 receive complete register (rxpr)..................................................................... 396 15.3.10 remote request register (rfpr)......................................................................... 397 15.3.11 interrupt register (irr) ........................................................................................ 398 15.3.12 mailbox interrupt mask register (mbimr)......................................................... 402 15.3.13 interrupt mask register (imr) ............................................................................. 403 15.3.14 receive error counter (rec) ............................................................................... 404 15.3.15 transmit error c ounter (tec).............................................................................. 404 15.3.16 unread message status register (umsr) ............................................................ 405 15.3.17 local acceptance filter ma sks (lafml, lafmh)............................................ 406 15.3.18 message control (mc0 to mc15) ........................................................................ 409 15.3.19 message data (md0 to md15) ............................................................................ 411 15.3.20 hcan monitor register (hcanmon)............................................................... 411 15.4 operation...................................................................................................................... ...... 412 15.4.1 hardware and software resets ............................................................................. 412 15.4.2 initialization after hardware reset ....................................................................... 412 15.4.3 message transmission .......................................................................................... 418 15.4.4 message reception ............................................................................................... 421 15.4.5 hcan sleep mode ............................................................................................... 424 15.4.6 hcan halt mode ................................................................................................. 427 15.5 interrupts ..................................................................................................................... ....... 428 15.6 dtc interface .................................................................................................................. .. 429 15.7 can bus interface............................................................................................................. 4 30 15.8 usage notes .................................................................................................................... ... 430 15.8.1 module stop mode setting ................................................................................... 430 15.8.2 reset ..................................................................................................................... 430 15.8.3 hcan sleep mode ............................................................................................... 431 15.8.4 interrupts............................................................................................................... 431 rev. 7.00 sep. 11, 2009 page xix of xxxiv rej09b0211-0700 15.8.5 error counters....................................................................................................... 431 15.8.6 register access..................................................................................................... 431 15.8.7 hcan medium-speed mode ............................................................................... 431 15.8.8 register hold in standby m odes .......................................................................... 431 15.8.9 usage of bit manipulation instructions ................................................................ 431 15.8.10 hcan txcr operation....................................................................................... 432 15.8.11 hcan transmit procedure................................................................................... 433 15.8.12 note on releasing the hcan reset or hcan sleep........................................... 433 15.8.13 note on accessing mailbox during the hcan sleep........................................... 433 section 16 a/d converter..................................................................................435 16.1 features ....................................................................................................................... ....... 435 16.2 input/output pins .............................................................................................................. . 437 16.3 register description........................................................................................................... 438 16.3.1 a/d data registers a to d (addra to addrd) .............................................. 438 16.3.2 a/d control/status register (adcsr) ................................................................ 439 16.3.3 a/d control register (adcr) ............................................................................. 441 16.4 operation...................................................................................................................... ...... 442 16.4.1 single mode.......................................................................................................... 442 16.4.2 scan mode ............................................................................................................ 442 16.4.3 input sampling and a/ d conversi on time........................................................... 443 16.4.4 external trigger input ti ming.............................................................................. 445 16.5 interrupts ..................................................................................................................... ....... 445 16.6 a/d conversion preci sion definitions............................................................................... 446 16.7 usage notes .................................................................................................................... ... 448 16.7.1 module stop mode setting ................................................................................... 448 16.7.2 permissible signal s ource impedance .................................................................. 448 16.7.3 influences on absolute precision.......................................................................... 448 16.7.4 range of analog power supp ly and other pin settings ....................................... 449 16.7.5 notes on board design ......................................................................................... 449 16.7.6 notes on noise c ountermeasures ......................................................................... 449 section 17 ram ................................................................................................451 section 18 rom ................................................................................................453 18.1 features ....................................................................................................................... ....... 453 18.2 mode transitions ............................................................................................................... 454 18.3 block configuration........................................................................................................... 4 58 18.4 input/output pins .............................................................................................................. . 459 18.5 register descriptions ......................................................................................................... 4 59 18.5.1 flash memory control register 1 (flmcr1)...................................................... 459 rev. 7.00 sep. 11, 2009 page xx of xxxiv rej09b0211-0700 18.5.2 flash memory control register 2 (flmcr2)...................................................... 461 18.5.3 erase block register 1 (ebr1) ............................................................................ 461 18.5.4 erase block register 2 (ebr2) ............................................................................ 462 18.5.5 ram emulation register (ramer).................................................................... 462 18.6 on-board programming modes......................................................................................... 463 18.6.1 boot m ode ............................................................................................................ 464 18.6.2 programming/erasing in user program mode...................................................... 466 18.7 flash memory emulation in ram .................................................................................... 468 18.8 flash memory programming/erasing ................................................................................ 470 18.8.1 program/program-verify ...................................................................................... 470 18.8.2 erase/erase-verify................................................................................................ 472 18.8.3 interrupt handling when progra mming/erasing flash memory........................... 472 18.9 program/erase protection .................................................................................................. 474 18.9.1 hardware protection ............................................................................................. 474 18.9.2 software protection............................................................................................... 474 18.9.3 error protection..................................................................................................... 474 18.10 programmer mode ............................................................................................................. 475 18.11 power-down states for flash memory.............................................................................. 475 18.12 note on switching from f-ztat version to mask rom version ................................... 476 section 19 clock pulse generator .....................................................................477 19.1 register descriptions ......................................................................................................... 4 78 19.1.1 system clock control register (sckcr) ............................................................ 478 19.1.2 low-power control register (lpwrcr) ............................................................ 479 19.2 oscilla tor..................................................................................................................... ....... 480 19.2.1 connecting a crystal resonator............................................................................ 480 19.2.2 external clock input ............................................................................................. 481 19.3 pll circuit .................................................................................................................... .... 483 19.4 medium-speed clock divider ........................................................................................... 483 19.5 bus master clock se lection circuit ................................................................................... 483 19.6 usage notes .................................................................................................................... ... 484 19.6.1 note on crystal resonator .................................................................................... 484 19.6.2 note on board design........................................................................................... 484 section 20 power-down modes ........................................................................487 20.1 register descriptions ......................................................................................................... 4 90 20.1.1 standby control regi ster (sbycr) ..................................................................... 490 20.1.2 module stop control registers a to c (mstpcra to mstpcrc).................... 492 20.2 medium-speed mode ......................................................................................................... 493 20.3 sleep mode ..................................................................................................................... ... 495 20.3.1 transition to sleep mode...................................................................................... 495 rev. 7.00 sep. 11, 2009 page xxi of xxxiv rej09b0211-0700 20.3.2 clearing sleep mode............................................................................................. 495 20.4 software st andby m ode..................................................................................................... 496 20.4.1 transition to software standby mode .................................................................. 496 20.4.2 clearing software standby mode ......................................................................... 496 20.4.3 setting oscillation stabilization time af ter clearing software standby mode.... 497 20.4.4 software standby mode ap plication ex ample..................................................... 498 20.5 hardware standby mode ................................................................................................... 499 20.5.1 transition to hardware standby mode ................................................................. 499 20.5.2 clearing hardware standby mode........................................................................ 499 20.5.3 hardware standby mode ti mings ........................................................................ 499 20.6 module stop mode............................................................................................................. 50 0 20.7 clock output disabling function ................................................................................... 501 20.8 usage notes .................................................................................................................... ... 502 20.8.1 i/o port status....................................................................................................... 502 20.8.2 current dissipation during oscilla tion stabilization wait period ........................ 502 20.8.3 dtc module stop................................................................................................. 502 20.8.4 on-chip supporting module interrupt.................................................................. 502 20.8.5 writing to mstpcr ............................................................................................. 502 section 21 electrical characteristics .................................................................503 21.1 absolute maximum ratings .............................................................................................. 503 21.2 dc charact eristic s ............................................................................................................. 504 21.3 ac charact eristic s ............................................................................................................. 507 21.3.1 clock ti ming ........................................................................................................ 508 21.3.2 control signal timing .......................................................................................... 509 21.3.3 timing of on-chip su pporting m odules.............................................................. 511 21.4 a/d conversion characteristics......................................................................................... 516 21.5 flash memory characteristics............................................................................................ 517 appendix ..........................................................................................................519 a. on-chip i/o register ......................................................................................................... 51 9 a.1 register addresses................................................................................................ 519 a.2 register bits.......................................................................................................... 534 a.3 register states in each operating mode .............................................................. 548 b. i/o port states in each pin state........................................................................................ 559 c. product code lineup ......................................................................................................... 560 d. package dimensions .......................................................................................................... 561 index ..........................................................................................................563 rev. 7.00 sep. 11, 2009 page xxii of xxxiv rej09b0211-0700 figures section 1 overview figure 1.1 internal block diagram (hd64f2612, hd6432612, and hd6432611)...................... 3 figure 1.2 internal block diag ram (hd6432616 an d hd6432614) ............................................ 4 figure 1.3 pin arrangement (hd64f 2612, hd6432612, and hd6432611) ................................ 5 figure 1.4 pin arrangement (hd6432616 and hd6432614)....................................................... 6 section 2 cpu figure 2.1 exception vector table (normal mode)................................................................... 17 figure 2.2 stack structure in normal mode............................................................................... 17 figure 2.3 exception vector table (advanced mode)............................................................... 18 figure 2.4 stack structure in advanced mode........................................................................... 19 figure 2.5 memory map.......................................................................................................... ... 20 figure 2.6 cpu registers ....................................................................................................... .... 21 figure 2.7 usage of general registers ....................................................................................... 22 figure 2.8 stack............................................................................................................... ........... 23 figure 2.9 general register data formats (1)............................................................................ 27 figure 2.9 general register data formats (2)............................................................................ 28 figure 2.10 memory data formats............................................................................................... 2 9 figure 2.11 instruction formats (examples) ................................................................................ 41 figure 2.12 branch address specifica tion in memory indirect mode......................................... 45 figure 2.13 state transitions.................................................................................................. ...... 49 section 3 mcu operating modes figure 3.1 address map (h8s/2612, h8s/2611, h8s/2616 , h8s/2614) ................................... 55 section 4 ex ception handling figure 4.1 reset sequence (advanced mode with on-chip rom enabled)............................. 60 figure 4.2 reset sequence (advanced mode with on-chip rom disabled: cannot be used in this lsi) ........ 61 figure 4.3 stack status af ter exception handling ...................................................................... 64 figure 4.4 operation when sp value is odd.............................................................................. 65 section 5 int errupt controller figure 5.1 block diagram of interrupt controller...................................................................... 68 figure 5.2 block diagram of interrupts irq0 to irq5.............................................................. 75 figure 5.3 flowchart of procedure up to interrupt acceptance in interrupt control mode 0... 80 figure 5.4 flowchart of procedure up to in terrupt acceptance in control mode 2 .................. 82 figure 5.5 interrupt exception handling.................................................................................... 84 figure 5.6 contention between interr upt generation and disabling .......................................... 87 rev. 7.00 sep. 11, 2009 page xxiii of xxxiv rej09b0211-0700 section 6 pc break controller (pbc) figure 6.1 block diagram of pc break controller ................................................................... 90 figure 6.2 operation in powe r-down mode transitions .......................................................... 93 section 7 bus controller figure 7.1 on-chip memory access cycle............................................................................... 97 figure 7.2 on-chip support module access cycle .................................................................. 98 figure 7.3 on-chip hcan module access cycle (wait states inserted) ................................ 99 figure 7.4 on-chip mmt module access cycle ................................................................... 100 section 8 data transfer controller (dtc) figure 8.1 block diagram of dtc .......................................................................................... 104 figure 8.2 block diagram of dt c activation source control ............................................... 110 figure 8.3 correspondence between dtc vector address and register information ............ 111 figure 8.4 flowchart of dtc operation ................................................................................. 114 figure 8.5 memory mappi ng in normal mode ....................................................................... 115 figure 8.6 memory mapping in repeat mode ........................................................................ 116 figure 8.7 memory mapping in block transf er mode ........................................................... 118 figure 8.8 chain transfer operation....................................................................................... 119 figure 8.9 dtc operation timi ng (example in normal mode or repeat mode) .................. 120 figure 8.10 dtc operation timing (example of block transfer mode, with block size of 2).................................... 121 figure 8.11 dtc operation timing (e xample of chain transfer) ........................................... 121 section 10 16-bit timer pulse unit (tpu) figure 10.1 block diagram of tpu .......................................................................................... 162 figure 10.2 example of counter operation setting procedure ................................................. 197 figure 10.3 free-running co unter operation........................................................................... 198 figure 10.4 periodic c ounter operation.................................................................................... 199 figure 10.5 example of setting procedure fo r waveform output by compare match............. 199 figure 10.6 example of 0 outp ut/1 output operation .............................................................. 200 figure 10.7 example of toggle output operation .................................................................... 200 figure 10.8 example of input captur e operation setting procedure ........................................ 201 figure 10.9 example of input capture operation ..................................................................... 202 figure 10.10 example of synchronous operation setting procedure ......................................... 203 figure 10.11 example of s ynchronous op eration....................................................................... 204 figure 10.12 compare match buffer operation.......................................................................... 205 figure 10.13 input captur e buffer operation ............................................................................. 206 figure 10.14 example of buffer operation setting procedure.................................................... 206 figure 10.15 example of bu ffer operation (1) ........................................................................... 207 figure 10.16 example of bu ffer operation (2) ........................................................................... 208 rev. 7.00 sep. 11, 2009 page xxiv of xxxiv rej09b0211-0700 figure 10.17 cascaded operation setting procedure .................................................................. 209 figure 10.18 example of ca scaded operation (1)....................................................................... 210 figure 10.19 example of ca scaded operation (2)....................................................................... 210 figure 10.20 example of pwm mode setting procedure ........................................................... 213 figure 10.21 example of pwm mode operation (1) .................................................................. 214 figure 10.22 example of pwm mode operation (2) .................................................................. 214 figure 10.23 example of pwm mode operation (3) .................................................................. 215 figure 10.24 example of phase c ounting mode setting procedure............................................ 217 figure 10.25 example of phase counting mode 1 operation ..................................................... 217 figure 10.26 example of phase counting mode 2 operation ..................................................... 218 figure 10.27 example of phase counting mode 3 operation ..................................................... 219 figure 10.28 example of phase counting mode 4 operation ..................................................... 220 figure 10.29 phase counting mode application example.......................................................... 222 figure 10.30 count timing in in ternal clock operation ............................................................ 226 figure 10.31 count timing in ex ternal clock operation ........................................................... 226 figure 10.32 output comp are output timing ............................................................................ 227 figure 10.33 input captur e input signa l timing......................................................................... 227 figure 10.34 counter clear timing (compare match) ............................................................... 228 figure 10.35 counter clear timing (input capture) ................................................................... 228 figure 10.36 buffer operation timing (compare match) .......................................................... 229 figure 10.37 buffer operation timing (input capture) .............................................................. 229 figure 10.38 tgi interrupt ti ming (compare match) ................................................................ 230 figure 10.39 tgi interrupt ti ming (input capture).................................................................... 230 figure 10.40 tciv inte rrupt setting timing............................................................................... 231 figure 10.41 tciu inte rrupt setting timing............................................................................... 232 figure 10.42 timing for status flag clearing by cpu ............................................................... 232 figure 10.43 timing for status fl ag clearing by dtc activation ............................................. 233 figure 10.44 phase difference, overlap, an d pulse width in phase counting mode ................. 234 figure 10.45 contention between tcnt write and clear operations........................................ 235 figure 10.46 contention between tcnt write and increment operations ................................ 236 figure 10.47 contention between tg r write and compare match ........................................... 237 figure 10.48 contention between buffer register write and compare match........................... 238 figure 10.49 contention between tg r read and input capture ................................................ 239 figure 10.50 contention between tg r write and input capture ............................................... 240 figure 10.51 contention between buffer register write and input capt ure............................... 241 figure 10.52 contention between ov erflow and count er clearing ............................................ 242 figure 10.53 contention between tcnt write and overflow ................................................... 243 section 11 motor management timer (mmt) figure 11.1 block diagram of mmt ........................................................................................ 246 figure 11.2 sample operating mode setting procedure ........................................................... 254 rev. 7.00 sep. 11, 2009 page xxv of xxxiv rej09b0211-0700 figure 11.3 mmt canceling procedure.................................................................................... 255 figure 11.4 example of tc nt count operation ...................................................................... 256 figure 11.5 examples of counter and register operations....................................................... 257 figure 11.6 example of pwm waveform generation .............................................................. 260 figure 11.7 example of tc nt counter clearing ..................................................................... 261 figure 11.8 example of toggle output wa veform synchronized with pwm period .............. 262 figure 11.9 c ount ti ming ....................................................................................................... .. 264 figure 11.10 tcnt count er clearing timing ............................................................................ 264 figure 11.11 tdcnt op eration timing..................................................................................... 265 figure 11.12 dead time generation timing............................................................................... 266 figure 11.13 buffer operation timing........................................................................................ 267 figure 11.14 tgi interrupt timing ............................................................................................. 2 68 figure 11.15 timing of status flag clearing by cpu................................................................. 269 figure 11.16 timing of status fl ag clearing by dtc controller ............................................... 269 figure 11.17 contention between buffer register write and compare match........................... 270 figure 11.18 contention between compare register write and compare match....................... 271 figure 11.19 error case in writing operation ............................................................................ 272 figure 11.20 output waveform caus ed by dead time limitation............................................. 273 figure 11.21 block diagram of poe .......................................................................................... 274 figure 11.22 low level detection operation ............................................................................. 279 section 12 programmabl e pulse generator (ppg) figure 12.1 block diagram of ppg........................................................................................... 282 figure 12.2 ppg output operation ........................................................................................... 291 figure 12.3 timing of transfer and outp ut of ndr contents (example)................................ 292 figure 12.4 setup procedure for norm al pulse output (example) ........................................... 293 figure 12.5 normal pulse output exam ple (five-phase pulse output).................................... 294 figure 12.6 non-overlapping pulse output .............................................................................. 295 figure 12.7 non-overlapping oper ation and ndr write timing ............................................ 296 figure 12.8 setup procedure for non-ov erlapping pulse output (example)............................ 297 figure 12.9 non-overlapping pulse output example (four-phase complementary)............... 298 figure 12.10 inverted pulse output (example) ........................................................................... 300 figure 12.11 pulse output triggere d by input capture (example)............................................. 301 section 13 watchdog timer figure 13.1 block diagram of wdt......................................................................................... 304 figure 13.2 writing to tcnt, tcsr, and rstcsr (example for wdt0) ............................. 310 figure 13.3 contention between tc nt write and increment................................................... 310 section 14 serial comm unication interface (sci) figure 14.1 block diagram of sci............................................................................................ 314 rev. 7.00 sep. 11, 2009 page xxvi of xxxiv rej09b0211-0700 figure 14.2 data format in asynchronous communication (example with 8-bit data, parity, two stop bits)................................................. 338 figure 14.3 receive data sampling timing in asynchr onous m ode ....................................... 340 figure 14.4 relationship between output clock and transfer data phase (asynchronous mode)............................................................................................ 341 figure 14.5 sample sci in itialization flowchart ...................................................................... 342 figure 14.6 example of operation in transmission in asynchronous mode (example with 8-bit data , parity, one stop bit) ................................................... 343 figure 14.7 sample serial transmission flowchart .................................................................. 344 figure 14.8 example of sci operation in reception (example with 8-bit data , parity, one stop bit) ................................................... 345 figure 14.9 sample serial recep tion data flowchart (1) ......................................................... 347 figure 14.9 sample serial recep tion data flowchart (2) ......................................................... 348 figure 14.10 example of communication using multiprocessor format (transmission of data h'aa to receiving station a) ........................................... 350 figure 14.11 sample multiprocessor se rial transmissi on flowchart ......................................... 351 figure 14.12 example of sci operation in reception (example with 8-bit data, mu ltiprocessor bit, one stop bit)............................... 352 figure 14.13 sample multiprocessor se rial reception flowchart (1)......................................... 353 figure 14.13 sample multiprocessor se rial reception flowchart (2)......................................... 354 figure 14.14 data format in synchrono us communication (f or lsb-first) ............................. 355 figure 14.15 sample sci in itialization flowchart ...................................................................... 356 figure 14.16 sample sci transmission oper ation in clocked synchronous mode ................... 358 figure 14.17 sample serial transmission flowchart .................................................................. 359 figure 14.18 example of sci operation in reception ................................................................ 360 figure 14.19 sample serial reception flowchart ....................................................................... 361 figure 14.20 sample flowchart of simultaneous serial transmit and receive operations ....... 363 figure 14.21 schematic diagram of sm art card interface pin connections............................... 364 figure 14.22 normal smart ca rd interface data format ............................................................ 365 figure 14.23 direct convention (sdir = sinv = o/ e = 0) ....................................................... 365 figure 14.24 inverse convention (sdir = sinv = o/ e = 1) ..................................................... 366 figure 14.25 receive data sampli ng timing in smart card mode (using clock of 372 times the transfer rate) ...................................................... 368 figure 14.26 retransfer operation in sci transmit mode ......................................................... 370 figure 14.27 tend flag generation timi ng in transmission operation .................................. 370 figure 14.28 example of tran smission processing flow ........................................................... 371 figure 14.29 retransfer operation in sci receive mode........................................................... 372 figure 14.30 example of reception processing flow................................................................. 373 figure 14.31 timing for fixi ng clock output level .................................................................. 373 figure 14.32 clock halt and restart procedure .......................................................................... 374 figure 14.33 sample transmission using dtc in clocked synchronous mode......................... 378 rev. 7.00 sep. 11, 2009 page xxvii of xxxiv rej09b0211-0700 figure 14.34 sample flowchart for m ode transition during transmission................................ 379 figure 14.35 pin states duri ng transmission in asynchronous mode (internal clock) ............. 379 figure 14.36 pin states during transmission in clocked synchronous mode (internal clock) ...................................................................................................... 380 figure 14.37 sample flowchart for mode transition during reception ..................................... 381 figure 14.38 operation when switchi ng from sck pin to port pin ........................................... 382 section 15 controller area network (hcan) figure 15.1 hcan block diagram ........................................................................................... 384 figure 15.2 message control register configuration ............................................................... 409 figure 15.3 standard format .................................................................................................... . 409 figure 15.4 extended format .................................................................................................... 409 figure 15.5 message data configuration .................................................................................. 411 figure 15.6 hardware reset flowchart ..................................................................................... 413 figure 15.7 software reset flowchart ...................................................................................... 414 figure 15.8 detailed description of one bit ............................................................................. 415 figure 15.9 transmission flowchart ......................................................................................... 418 figure 15.10 transmit message cancellation flowchart ............................................................ 420 figure 15.11 reception flowchart .............................................................................................. 4 21 figure 15.12 unread message overwrite flowchart................................................................... 424 figure 15.13 hcan sleep mode flowchart ............................................................................... 425 figure 15.14 hcan halt mode flowchart ................................................................................. 427 figure 15.15 dtc transfer flowchart ........................................................................................ 429 figure 15.16 high-speed interface using pca82c250.............................................................. 430 section 16 a/d converter figure 16.1 block diagra m of a/d converter .......................................................................... 436 figure 16.2 a/d conve rsion ti ming......................................................................................... 443 figure 16.3 external tr igger input timing ............................................................................... 445 figure 16.4 a/d conversion precision definitions................................................................... 447 figure 16.5 a/d conversion precision definitions................................................................... 447 figure 16.6 example of analog input circuit ........................................................................... 448 figure 16.7 example of analog input protection circuit.......................................................... 450 figure 16.8 analog input pin equivalent circuit ...................................................................... 450 section 18 rom figure 18.1 block diagram of flash memory........................................................................... 454 figure 18.2 flash memory state transitions............................................................................. 455 figure 18.3 boot mode.......................................................................................................... .... 456 figure 18.4 user program mode ............................................................................................... 457 figure 18.5 flash memory block configuration....................................................................... 458 rev. 7.00 sep. 11, 2009 page xxviii of xxxiv rej09b0211-0700 figure 18.6 programming/erasing flowchar t example in user program mode....................... 467 figure 18.7 flowchart for flash memory emulation in ram .................................................. 468 figure 18.8 example of ram overlap operation..................................................................... 469 figure 18.9 program/program-verify flowchart ...................................................................... 471 figure 18.10 erase/erase-verify flowchart ................................................................................ 473 section 19 clock pulse generator figure 19.1 block diagram of clock pulse generator .............................................................. 477 figure 19.2 connection of crystal resonator (example).......................................................... 480 figure 19.3 crystal resonator equivalent circuit..................................................................... 480 figure 19.4 external cloc k input (exa mples) ........................................................................... 481 figure 19.5 external cl ock input timing.................................................................................. 482 figure 19.6 note on board design of oscillator circuit ........................................................... 484 figure 19.7 external circuitry r ecommended for pll circuit ................................................ 485 section 20 power-down modes figure 20.1 mode transition diagram ...................................................................................... 488 figure 20.2 medium-speed mode tr ansition and clearance timing ....................................... 494 figure 20.3 software standby m ode applicati on exampl e ...................................................... 498 figure 20.4 timing of transition to hardware standby mode ................................................. 499 figure 20.5 timing of recovery from hardware standby mode.............................................. 500 section 21 electrical characteristics figure 21.1 output load circuit ............................................................................................... 5 07 figure 21.2 system clock timing............................................................................................. 508 figure 21.3 oscillation st abilization timing ............................................................................ 509 figure 21.4 reset input timing................................................................................................. 510 figure 21.5 interrupt input timing............................................................................................ 5 10 figure 21.6 i/o port in put/output timing................................................................................. 512 figure 21.7 tpu inpu t/output timing...................................................................................... 513 figure 21.8 tpu cloc k input ti ming........................................................................................ 513 figure 21.9 sck cloc k input ti ming ....................................................................................... 513 figure 21.10 sci input/o utput timing (clock synchronous mode) .......................................... 514 figure 21.11 a/d converter exte rnal trigger in put timing....................................................... 514 figure 21.12 hcan inpu t/output timing .................................................................................. 514 figure 21.13 ppg ou tput timing................................................................................................ 5 14 figure 21.14 mmt input/output timing.................................................................................... 515 figure 21.15 poe inpu t/output timing...................................................................................... 515 appendix figure d.1 fp-80q, fp-80qv package dimensions ............................................................... 561 rev. 7.00 sep. 11, 2009 page xxix of xxxiv rej09b0211-0700 tables section 1 overview table 1.1 comparison of produc t specifications ...................................................................... 12 section 2 cpu table 2.1 instruction classification........................................................................................... 30 table 2.2 operation notation.................................................................................................... 31 table 2.3 data transfer instructions ......................................................................................... 32 table 2.4 arithmetic operations instructions ........................................................................... 33 table 2.5 logic operations instructions ................................................................................... 35 table 2.6 shift instructions ....................................................................................................... 35 table 2.7 bit manipulation instructions.................................................................................... 36 table 2.8 branch instructions ................................................................................................... 38 table 2.9 system control instructions ...................................................................................... 39 table 2.10 block data transfer instructions............................................................................... 40 table 2.11 addressing modes..................................................................................................... 42 table 2.12 absolute address access ranges ............................................................................. 44 table 2.13 effective address calculation................................................................................... 46 section 3 mcu operating modes table 3.1 mcu operating mode selection............................................................................... 51 table 3.2 pin functions in each mode ..................................................................................... 54 section 4 ex ception handling table 4.1 exception types and priority .................................................................................... 57 table 4.2 exception handling vector table ............................................................................. 58 table 4.3 status of ccr and exr after trace exception handling......................................... 62 table 4.4 status of ccr and exr after trap instruction exception handling ........................ 63 section 5 int errupt controller table 5.1 pin configuration ...................................................................................................... 69 table 5.2 interrupt sources, vector addresse s, and interrupt priorities ................................... 77 table 5.3 interrupt control modes............................................................................................ 79 table 5.4 interrupt res ponse times.......................................................................................... 85 table 5.5 number of states in interrupt handling routine execution status........................... 86 section 8 data transfer controller (dtc) table 8.1 interrupt sources, dtc vector addresses, and corresponding dtces ................. 112 table 8.2 register information in normal mode .................................................................... 115 table 8.3 register information in repeat mode ..................................................................... 116 rev. 7.00 sep. 11, 2009 page xxx of xxxiv rej09b0211-0700 table 8.4 register information in block transf er mode ........................................................ 117 table 8.5 dtc execution status ............................................................................................. 122 table 8.6 number of states required fo r each execution status ........................................... 122 section 9 i/o ports table 9.1 port functions ......................................................................................................... 128 table 9.2 p17 pin function ..................................................................................................... 132 table 9.3 p16 pin function ..................................................................................................... 132 table 9.4 p15 pin function ..................................................................................................... 133 table 9.5 p14 pin function ..................................................................................................... 133 table 9.6 p13 pin function ..................................................................................................... 133 table 9.7 p12 pin function ..................................................................................................... 134 table 9.8 p11 pin function ..................................................................................................... 134 table 9.9 p10 pin function ..................................................................................................... 134 table 9.10 pa3 pin function .................................................................................................... 140 table 9.11 pa2 pin function .................................................................................................... 140 table 9.12 pa1 pin function .................................................................................................... 140 table 9.13 pa0 pin function .................................................................................................... 140 table 9.14 pb7 pin function .................................................................................................... 144 table 9.15 pb6 pin function .................................................................................................... 144 table 9.16 pb5 pin function .................................................................................................... 145 table 9.17 pb4 pin function .................................................................................................... 145 table 9.18 pb3 pin function .................................................................................................... 145 table 9.19 pb2 pin function .................................................................................................... 146 table 9.20 pb1 pin function .................................................................................................... 146 table 9.21 pb0 pin function .................................................................................................... 146 section 10 16-bit timer pulse unit (tpu) table 10.1 tpu functions......................................................................................................... 160 table 10.2 tpu pins ................................................................................................................. 163 table 10.3 cclr0 to cclr2 (cha nnels 0 a nd 3) ..................................................................... 167 table 10.4 cclr0 to cclr2 (channels 1, 2, 4, and 5)............................................................ 167 table 10.5 tpsc0 to tpsc2 (channel 0).................................................................................. 168 table 10.6 tpsc0 to tpsc2 (channel 1).................................................................................. 168 table 10.7 tpsc0 to tpsc2 (channel 2).................................................................................. 169 table 10.8 tpsc0 to tpsc2 (channel 3).................................................................................. 169 table 10.9 tpsc0 to tpsc2 (channel 4).................................................................................. 170 table 10.10 tpsc0 to tpsc2 (channel 5).................................................................................. 170 table 10.11 md0 to md3........................................................................................................... 172 table 10.12 tiorh_0 (channel 0).............................................................................................. 174 table 10.13 tiorl_0 (channel 0) .............................................................................................. 175 rev. 7.00 sep. 11, 2009 page xxxi of xxxiv rej09b0211-0700 table 10.14 tior_1 (channel 1) ................................................................................................ 176 table 10.15 tior_2 (channel 2) ................................................................................................ 177 table 10.16 tiorh_3 (channel 3).............................................................................................. 178 table 10.17 tiorl_3 (channel 3) .............................................................................................. 179 table 10.18 tior_4 (channel 4) ................................................................................................ 180 table 10.19 tior_5 (channel 5) ................................................................................................ 181 table 10.20 tiorh_0 (channel 0).............................................................................................. 182 table 10.21 tiorl_0 (channel 0) .............................................................................................. 183 table 10.22 tior_1 (channel 1) ................................................................................................ 184 table 10.23 tior_2 (channel 2) ................................................................................................ 185 table 10.24 tiorh_3 (channel 3).............................................................................................. 186 table 10.25 tiorl_3 (channel 3) .............................................................................................. 187 table 10.26 tior_4 (channel 4) ................................................................................................ 188 table 10.27 tior_5 (channel 5) ................................................................................................ 189 table 10.28 register combinations in buffer operation............................................................ 205 table 10.29 cascaded combinations .......................................................................................... 209 table 10.30 pwm output registers and output pins................................................................. 212 table 10.31 phase counting mode clock input pins.................................................................. 216 table 10.32 up/down-count conditions in phase counting mode 1 ........................................ 218 table 10.33 up/down-count conditions in phase counting mode 2 ........................................ 219 table 10.34 up/down-count conditions in phase counting mode 3 ........................................ 220 table 10.35 up/down-count conditions in phase counting mode 4 ........................................ 221 table 10.36 tpu interrupts......................................................................................................... 224 section 11 motor management timer (mmt) table 11.1 pin configuration .................................................................................................... 247 table 11.2 initial values of tbru to tbrw and initial output.............................................. 259 table 11.3 mmt interrupt sources........................................................................................... 263 table 11.4 pin configuration .................................................................................................... 275 section 12 programmabl e pulse generator (ppg) table 12.1 ppg i/o pins ........................................................................................................... 283 section 13 watchdog timer table 13.1 wdt interrupt source............................................................................................. 309 section 14 serial comm unication interface (sci) table 14.1 pin configuration .................................................................................................... 315 table 14.2 relationships between the n setting in brr and bit rate b ................................. 331 table 14.3 brr settings for various bit rates (asynchr onous mode) ................................... 332 table 14.4 maximum bit rate for each frequency (asynchronous mode)............................. 334 rev. 7.00 sep. 11, 2009 page xxxii of xxxiv rej09b0211-0700 table 14.5 maximum bit rate with external cl ock input (asynchronous mode)................... 335 table 14.6 brr settings for various bit rates (clocked synchronous mode) ....................... 336 table 14.7 maximum bit rate with external clock input (clocked synchronous mode)....... 336 table 14.8 examples of bit rate for various brr settings (smart card interface mode) (when n = 0 a nd s = 372) ....................................................................................... 337 table 14.9 maximum bit rate at various frequenc ies (smart card interface mode) (when s = 372) ....................................................................................................... 337 table 14.10 serial transfer formats (asynchronous mode) ...................................................... 339 table 14.11 ssr status flags and receive data handling......................................................... 346 table 14.12 sci interrupt sources .............................................................................................. 375 table 14.13 sci interrupt sources .............................................................................................. 376 section 15 controller area network (hcan) table 15.1 hcan pins.............................................................................................................. 385 table 15.2 limits for settable value ........................................................................................ 415 table 15.3 setting range for tseg1 and tseg2 in bcr ....................................................... 416 table 15.4 hcan interrupt sources ......................................................................................... 428 table 15.5 interval limitation between txpr and txpr or between txpr and txcr ....... 433 section 16 a/d converter table 16.1 pin configuration .................................................................................................... 437 table 16.2 analog input channels and corresponding addr registers................................. 439 table 16.3 a/d conversion time (single m ode) ..................................................................... 444 table 16.4 a/d conversion time (scan mode)........................................................................ 444 table 16.5 a/d converter interrupt source .............................................................................. 445 table 16.6 analog pin speci fications ....................................................................................... 450 section 18 rom table 18.1 differences between boot mode and user program mode..................................... 455 table 18.2 pin configuration .................................................................................................... 459 table 18.3 setting on-board programming modes.................................................................. 463 table 18.4 boot mode operation.............................................................................................. 465 table 18.5 system clock frequencies for which automatic adjustment of lsi bit rate is possible ................................................................................................................... 465 table 18.6 flash memory operating states .............................................................................. 475 table 18.7 registers present in f-ztat version but absent in mask rom version ............. 476 section 19 clock pulse generator table 19.1 damping resistance value ..................................................................................... 480 table 19.2 crystal resonator characteristics............................................................................ 481 table 19.3 external clock input conditions ............................................................................. 482 rev. 7.00 sep. 11, 2009 page xxxiii of xxxiv rej09b0211-0700 section 20 power-down modes table 20.1 low power dissipation mode transition conditions ............................................. 487 table 20.2 lsi internal states in each mode............................................................................ 489 table 20.3 oscillation stabilizati on time settings ................................................................... 497 table 20.4 pin state in each processing state ....................................................................... 501 section 21 electrical characteristics table 21.1 absolute maximum ratings.................................................................................... 503 table 21.2 dc characteristics................................................................................................... 504 table 21.3 permissible output currents ................................................................................... 507 table 21.4 clock timing........................................................................................................... 508 table 21.5 control signal timing............................................................................................. 509 table 21.6 timing of on-chip su pporting m odules ................................................................ 511 table 21.7 a/d conversion characteristics .............................................................................. 516 table 21.8 flash memory characteristics................................................................................. 517 rev. 7.00 sep. 11, 2009 page xxxiv of xxxiv rej09b0211-0700 section 1 overview rev. 7.00 sep. 11, 2009 page 1 of 566 rej09b0211-0700 section 1 overview 1.1 overview ? high-speed h8s/2600 central processing unit with an internal 16-bit architecture ? upward-compatible with h8/300 and h8/300h cpus on an object level ? sixteen 16-bit general registers ? 69 basic instructions ? various peripheral functions ? pc break controller ? data transfer controller (dtc) ? 16-bit timer-pulse unit (tpu) ? motor management timer (mmt) ? programmable pulse generator (ppg) ? watchdog timer ? asynchronous or clocked synchronous serial communicati on interface (sci) ? controller area network (hcan) ? 10-bit a/d converter ? clock pulse generator ? on-chip memory rom model rom ram remarks f-ztat version hd64f2612 128 kbytes 4 kbytes hd6432612 128 kbytes 4 kbytes mask rom version hd6432611 64 kbytes 4 kbytes hd6432616 128 kbytes 4 kbytes hd6432614 64 kbytes 4 kbytes ? general i/o ports ? i/o pins: 43 ? input-only pins: 13 ? supports various power-down states section 1 overview rev. 7.00 sep. 11, 2009 page 2 of 566 rej09b0211-0700 ? compact package package package code body size pin pitch qfp-80 fp-80q/fp-80qv 14.0 14.0 mm 0.65 mm note: mmt, ppg, pc break controller, and dtc are not implemented in the h8s/2614 and h8s/2616. section 1 overview rev. 7.00 sep. 11, 2009 page 3 of 566 rej09b0211-0700 1.2 internal block diagram pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 vcl vcl vcc v cc v cc v ss v ss v ss pa3/sck2/ poe3 pa2/rxd2/ poe2 pa1/txd2/ poe1 pa0/ poe0 pb7/tiocb5/pwob pb6/tioca5/pwoa pb5/tiocb4/pvob pb4/tioca4/pvoa pb3/tiocd3/puob pb2/tiocc3/puoa pb1/tiocb3/pco pb0/tioca3/ pci pc7 pc6 pc5/sck1/ irq5 pc4/rxd1 pc3/txd1 pc2/sck0/ irq4 pc1/rxd0 pc0/txd0 p93 /an11 p92 /an10 p91 /an9 p90 /an8 p47 /an7 p46 /an6 p45 /an5 p44 /an4 p43 /an3 p42 /an2 p41 /an1 p40 /an0 hrxd htxd avcc avss p17/po15/tiocb2/tclkd p16/po14/tioca2/ irq1 p15/po13/tiocb1/tclkc p14/po12/tioca1/ irq0 p13/po11/tiocd0/tclkb p12/po10/tiocc0/tclka p11/po9/tiocb0 p10/po8/tioca0 pf7/ pf6 pf5 pf4 pf3/ adtrg / irq3 pf2 pf1 pf0/ irq2 ram tpu mmt ppg md2 md1 md0 extal xtal pllvcl pllcap pllvss stby res fwe/nc * nmi h8s/2600 cpu dtc port d port a port b port c port 9 port 4 port 1 port f pll clock pulse g enerator interrupt controller pc break controller (2 channels) rom (mask rom, flash memory * ) wdt 1 channel sci 3 channels hcan 1 channel a/d converter peripheral address bus peripheral data bus bus controller internal address bus internal data bus note: * the fwe pin is provided only in the flash memory version. the nc pin is provided only in the mask rom versions. figure 1.1 internal block diagram (hd64f2612, hd6432612, and hd6432611) section 1 overview rev. 7.00 sep. 11, 2009 page 4 of 566 rej09b0211-0700 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 vcl vcl vcc vcc vcc vss vss vss pa3/sck2 pa2/rxd2 pa1/txd2 pa0 pb7/tiocb5 pb6/tioca5 pb5/tiocb4 pb4/tioca4 pb3/tiocd3 pb2/tiocc3 pb1/tiocb3 pb0/tioca3 pc7 pc6 pc5/sck1/ irq 5 pc4/rxd1 pc3/txd1 pc2/sck0/ irq 4 pc1/rxd0 pc0/txd0 p93/an11 p92/an10 p91/an9 p90/an8 p47 /an7 p46 /an6 p45 /an5 p44 /an4 p43 /an3 p42 /an2 p41 /an1 p40 /an0 hrxd htxd avcc avss p17/tiocb2/tclkd p16/tioca2/ irq1 p15/tiocb1/tclkc p14/tioca1/ irq0 p13/tiocd0/tclkb p12/tiocc0/tclka p11/tiocb0 p10/tioca0 pf7/ pf6 pf5 pf4 pf3/ adtrg / irq3 pf2 pf1 pf0/ irq2 md2 md1 md0 extal xtal pllvcl pllcap pllvss stby res nc nmi h8s/2600 cpu port a port b pll clock pulse g enerator interrupt controller peripheral address bus peripheral data bus bus controller internal address bus internal data bus port d port c port 9 port 4 port 1 port f ram tpu 6 channels rom (mask rom) wdt 1 channel hcan 1 channel sci 3 channels a/d converter figure 1.2 internal block diagram (hd6432616 and hd6432614) section 1 overview rev. 7.00 sep. 11, 2009 page 5 of 566 rej09b0211-0700 1.3 pin arrangement md2 md1 md0 pa3/sck2/ poe3 pa2/rxd2/ poe2 pa1/txd2/ poe1 pa 0 / poe0 pb7/tiocb5/pwob pb6/tioca5/pwoa pb5/tiocb4/pvob pb4/tioca4/pvoa pb3/tiocd3/puob pb2/tiocc3/puoa vcc pb1/tiocb3/pco vss pb0/tioca3/ pci pc7 pc6 pc5/sck1/ irq5 avcc p93/an11 p92/an10 p91/an9 p90/an8 p47/an7 p46/an6 p45/an5 p44/an4 p43/an3 p42/an2 p41/an1 p40/an0 avss p10/po8/tioca0 vcc p11/po9/tiocb0 vss p12/po10/tiocc0/tclka vcl p13/po11/tiocd0/tclkb p14/po12/tioca1/ irq0 p15/po13/tiocb1/tclkc p16/po14/tioca2/ irq1 p17/po15/tiocb2/tclkd htxd hrxd pf0/ irq2 pf1 pf2 pf3/ adtrg / irq3 pf4 pf5 pf6 pf7/ pc0/txd0 pc1/rxd0 pc2/sck0/ irq4 pc3/txd1 pc4/rxd1 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 vcl fwe/nc * vss extal vcc xtal pllvss stby pllvcl nmi pllcap res top view (fp-80q) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 note : * the fwe pin is used only in the flash memory version. the nc pin is used only in the mask rom versions. figure 1.3 pin arrangement (hd64f2612, hd6432612, and hd6432611) section 1 overview rev. 7.00 sep. 11, 2009 page 6 of 566 rej09b0211-0700 md2 md1 md0 pa3/sck2 pa2/rxd2 pa1/txd2 pa 0 pb7/tiocb5 pb6/tioca5 pb5/tiocb4 pb4/tioca4 pb3/tiocd3 pb2/tiocc3 vcc pb1/tiocb3 vss pb0/tioca3 pc7 pc6 pc5/sck1/ irq 5 avcc p93/an11 p92/an10 p91/an9 p90/an8 p47/an7 p46/an6 p45/an5 p44/an4 p43/an3 p42/an2 p41/an1 p40/an0 avss p10/tioca0 vcc p11/tiocb0 vss p12/tiocc0/tclka vcl p13/tiocd0/tclkb p14/tioca1/ irq0 p15/tiocb1/tclkc p16/tioca2/ irq1 p17/tiocb2/tclkd htxd hrxd pf0/ irq2 pf1 pf2 pf3/ adtrg / irq3 pf4 pf5 pf6 pf7/ pc0/txd0 pc1/rxd0 pc2/sck0/ irq4 pc3/txd1 pc4/rxd1 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 vcl nc vss extal vcc xtal pllvss stby pllvcl nmi pllcap res top view (fp-80q) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 note: ppg and mmt pin functions are not implemented. figure 1.4 pin arrangement (hd6432616 and hd6432614) section 1 overview rev. 7.00 sep. 11, 2009 page 7 of 566 rej09b0211-0700 1.4 pin functions type symbol pin no. i/o function power supply vcc 27 48 76 input power supply pins. connect all these pins to the system power supply. vss 25 50 78 input ground pins. connect all these pins to the system power supply (0v). vcl 52 80 output external capacitance pin for internal power-down power supply. connect this pin to vss via a 0.1-f capacitor (placed close to the pins). clock pllvcl 44 output external capacitance pin for internal power-down power supply for an on-chip pll oscillator. connect this pin to pllvss via a 0.1-f capacitor (placed close to the pins). pllvss 46 input on-chip pll oscillator ground pin. pllcap 42 output external capacitance pin for an on-chip pll oscillator. xtal 47 input for connection to a crystal resonator. for examples of crystal resonator connection and external clock input, see section 19, clock pulse generator. extal 49 input for connection to a crystal resonator. (an external clock can be supplied from the extal pin.) for examples of crystal resonator connection and external clock input, see section 19, clock pulse generator. 15 output supplies the system clock to external devices. operating mode control md2 md1 md0 40 39 38 input set the operating mode. inputs at these pins should not be changed during operation. system control res 41 input reset input pin. when this pin is low, the chip is reset. stby 45 input when this pin is low, a transition is made to hardware standby mode. fwe 51 input pin for use by flash memory. this pin is only used in the flash memory version. section 1 overview rev. 7.00 sep. 11, 2009 page 8 of 566 rej09b0211-0700 type symbol pin no. i/o function interrupts nmi 43 input nonmaskable interrupt pin. if this pin is not used, it should be fixed-high. irq5 irq4 irq3 irq2 irq1 irq0 21 18 11 8 4 2 input these pins request a maskable interrupt. 16-bit timer-pulse unit tclka tclkb tclkc tclkd 79 1 3 5 input these pins input an external clock. tioca0 tiocb0 tiocc0 tiocd0 75 77 79 1 input/ output tgra_0 to tgrd_0 input capture input/output compare output/pwm output pins. tioca1 tiocb1 2 3 input/ output tgra_1 to tgrb_1 input capture input/output compare output/pwm output pins. tioca2 tiocb2 4 5 input/ output tgra_2 to tgrb_2 input capture input/output compare output/pwm output pins. tioca3 tiocb3 tiocc3 tiocd3 24 26 28 29 input/ output tgra_3 to tgrd_3 input capture input/output compare output/pwm output pins. tioca4 tiocb4 30 31 input/ output tgra_4 to tgrb_4 input capture input/output compare output/pwm output pins. tioca5 tiocb5 32 33 input/ output tgra_5 to tgrb_5 input capture input/output compare output/pwm output pins. program- mable pulse generator (ppg) po15 po14 po13 po12 po11 po10 po9 po8 5 4 3 2 1 79 77 75 output pulse output pins. section 1 overview rev. 7.00 sep. 11, 2009 page 9 of 566 rej09b0211-0700 type symbol pin no. i/o function puoa 28 output u-phase output pin for 6-phase non-overlap pwm waveforms. puob 29 output u -phase output pin for 6-phase non-overlap pwm waveforms motor manage- ment timer (mmt) pvoa 30 output v-phase output pin for 6-phase non-overlap pwm waveforms. pvob 31 output v -phase output pin for 6-phase non-overlap pwm waveforms. pwoa 32 output w-phase output pin for 6-phase non-overlap pwm waveforms. pwob 33 output w -phase output pin for 6-phase non-overlap pwm waveforms. pci 24 input counter clear input pin by external input. pco 26 output output pin for toggle synchronized with 6-phase non-overlap pwm waveforms. poe3 poe2 poe1 poe0 37 36 35 34 input input pin for signal requesting to set the mmt waveform output pin to the high-impedance state. txd2 txd1 txd0 35 19 16 output data output pins. rxd2 rxd1 rxd0 36 20 17 input data input pins. serial communi- cation interface (sci)/ smart card interface sck2 sck1 sck0 37 21 18 input/ output clock input/output pins. hcan htxd 6 output can bus transmission pin. hrxd 7 input can bus reception pin. section 1 overview rev. 7.00 sep. 11, 2009 page 10 of 566 rej09b0211-0700 type symbol pin no. i/o function a/d converter an11 an10 an9 an8 an7 an6 an5 an4 an3 an2 an1 an0 62 63 64 65 66 67 68 69 70 71 72 73 input analog input pins. adtrg 11 input pin for input of an external trigger to start a/d conversion. avcc 61 input power supply pin for the a/d converter. when the a/d converter is not used, connect this pin to the system power supply (+5v). avss 74 input the ground pin for the a/d converter. connect this pin to the system power supply (0v). i/o ports p17 p16 p15 p14 p13 p12 p11 p10 5 4 3 2 1 79 77 75 input/ output eight input/output pins. p47 p46 p45 p44 p43 p42 p41 p40 66 67 68 69 70 71 72 73 input eight input pins. p93 p92 p91 p90 62 63 64 65 input four input pins. section 1 overview rev. 7.00 sep. 11, 2009 page 11 of 566 rej09b0211-0700 type symbol pin no. i/o function i/o ports pa3 pa2 pa1 pa0 37 36 35 34 input/ output four input/output pins. pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 33 32 31 30 29 28 26 24 input/ output eight input/output pins. pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 23 22 21 20 19 18 17 16 input/ output eight input/output pins. pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 53 54 55 56 57 58 59 60 input/ output eight input/output pins. pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 15 14 13 12 11 10 9 8 input/ output eight input/output pins. section 1 overview rev. 7.00 sep. 11, 2009 page 12 of 566 rej09b0211-0700 1.5 differences between h8s/2612, h8s/2611, h8s/2614, and h8s/2616 the amount of on-chip rom and the specific on-chip modules implemented differ among the h8s/2612, h8s/2611, h8s/2614, and h8s/2616. table 1.1 lists the specifications for these products. note: the dtc, pbc, ppg, and mmt are not implemented in the h8s/2616 and h8s/2614, so these modules cannot be used on these products. table 1.1 comparison of product specifications product specifications product type model rom ram dtc, pbc, ppg, mmt h8s/2612 hd64f2612 128-kbyte on-chip flash memory 4-kbyte sram yes hd6432612 128-kbyte mask rom h8s/2611 hd6432611 64-kbyte mask rom h8s/2616 hd6432616 128-kbyte mask rom no h8s/2614 hd6432614 64-kbyte mask rom section 2 cpu rev. 7.00 sep. 11, 2009 page 13 of 566 rej09b0211-0700 section 2 cpu the h8s/2600 cpu is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the h8/300 and h8/300h cpus. the h8s/2600 cpu has sixteen 16-bit general registers, can address a 16-mbyte linear ad dress space, and is ideal for realtime control. this section describes the h8s/2600 cpu. the us able modes and address spaces differ depending on the product. for details on each product, refer to section 3, mcu operating modes. 2.1 features ? upward-compatible with h8/300 and h8/300h cpus ? can execute h8/300 and h8/300h cpus object programs ? general-register architecture ? sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers ? sixty-nine basic instructions ? 8/16/32-bit arithmetic and logic instructions ? multiply and divide instructions ? powerful bit-manipulation instructions ? multiply-and-accumulate instruction ? eight addressing modes ? register direct [rn] ? register indirect [@ern] ? register indirect with displacemen t [@(d:16,ern) or @(d:32,ern)] ? register indirect with post-increment or pre-decrement [@ern+ or @?ern] ? absolute address [@aa:8, @aa:16, @aa:24, or @aa:32] ? immediate [#xx:8, #xx:16, or #xx:32] ? program-counter relative [@(d:8,pc) or @(d:16,pc)] ? memory indirect [@@aa:8] ? 16-mbyte address space ? program: 16 mbytes ? data: 16 mbytes ? high-speed operation ? all frequently-used instructions execute in one or two states ? 8/16/32-bit register-register add/subtract: 1 state ? 8 8-bit register-register multiply: 3 states ? 16 8-bit register-register divide: 12 states section 2 cpu rev. 7.00 sep. 11, 2009 page 14 of 566 rej09b0211-0700 ? 16 16-bit register-register multiply: 4 states ? 32 16-bit register-register divide: 20 states ? two cpu operating modes ? normal mode * ? advanced mode ? power-down state ? transition to power-down state by sleep instruction ? cpu clock speed selection note: * normal mode is not available in this lsi. 2.1.1 differences between h8s/2600 cpu and h8s/2000 cpu the differences between the h8s/2600 cpu and the h8s/2000 cpu are shown below. ? register configuration the mac register is supported by the h8s/2600 cpu only. ? basic instructions the four instructions mac, clrmac, ldmac, and stmac are supported by the h8s/2600 cpu only. ? the number of execution states of the mulxu and mulxs instructions; execution states instruction mnemonic h8s/2600 h8s/2000 mulxu mulxu.b rs, rd 3 12 mulxu.w rs, erd 4 20 mulxs mulxs.b rs, rd 4 13 mulxs.w rs, erd 5 21 in addition, there are differences in address space, ccr and exr register functions, and power- down modes, etc., depending on the model. section 2 cpu rev. 7.00 sep. 11, 2009 page 15 of 566 rej09b0211-0700 2.1.2 differences from h8/300 cpu in comparison to the h8/300 cpu, the h8s/2600 cpu has the following enhancements: ? more general registers and control registers ? eight 16-bit expanded registers, and one 8-bit and two 32-bit control registers, have been added. ? expanded address space ? normal mode supports the same 64-kbyt e address space as the h8/300 cpu. ? advanced mode supports a maximum 16-mbyte address space. ? enhanced addressing ? the addressing modes have been enhanced to make effective use of the 16-mbyte address space. ? enhanced instructions ? addressing modes of bit-manipulation instructions have been enhanced. ? signed multiply and divide instructions have been added. ? a multiply-and-accumulate instruction has been added. ? two-bit shift instructions have been added. ? instructions for saving and restoring multiple registers have been added. ? a test and set instruction has been added. ? higher speed ? basic instructions execute twice as fast. 2.1.3 differences from h8/300h cpu in comparison to the h8/300h cpu, the h8s/2600 cpu has the following enhancements: ? additional control register ? one 8-bit and two 32-bit control registers have been added. ? enhanced instructions ? addressing modes of bit-manipulation instructions have been enhanced. ? a multiply-and-accumulate instruction has been added. ? two-bit shift instructions have been added. ? instructions for saving and restoring multiple registers have been added. ? a test and set instruction has been added. ? higher speed ? basic instructions execute twice as fast. section 2 cpu rev. 7.00 sep. 11, 2009 page 16 of 566 rej09b0211-0700 2.2 cpu operating modes the h8s/2600 cpu has two operating modes: norma l and advanced. normal mode supports a maximum 64-kbyte address space. advanced mode supports a maximum 16-mbyte total address space. the mode is selected by the mode pins. 2.2.1 normal mode the exception vector table and stack have th e same structure as in the h8/300 cpu. ? address space a maximum address space of 64 kbytes can be accessed. ? extended registers (en) the extended registers (e0 to e7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. when en is used as a 16-bit register it can contain any value, even when the corresponding general register (rn) is used as an address register. if the general register is referenced in the register indirect addressing mode with pre-decrement (@?rn) or post-increment (@rn+) and a carry or borrow o ccurs, however, the value in the corresponding extended register (en) will be affected. ? instruction set all instructions and addressing modes can be used. only the lower 16 bits of effective addresses (ea) are valid. ? exception vector table and memory indirect branch addresses in normal mode the top area starting at h'0000 is allocated to the excep tion vector table. one branch address is stored per 16 bits. the exception vector table differs depending on the microcontroller. for details of the exception vector table, see section 4, exception handling. the memory indirect addressing mode (@@aa:8) employed in the jmp and jsr instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. in normal mode the operand is a 16-bit word operand, providing a 16-bit branch address. branch addresses can be stored in the top area from h'0000 to h'00ff. note that this area is also used for the exception vector table. ? stack structure when the program counter (pc) is pushed onto the stack in a subroutine call, and the pc, condition-code register (ccr), and extended control register (exr) are pushed onto the stack in exception handling, they are stored as shown in figure 2.2. exr is not pushed onto the stack in interrupt control mode 0. for details, see section 4, exception handling. note: normal mode is not available in this lsi. section 2 cpu rev. 7.00 sep. 11, 2009 page 17 of 566 rej09b0211-0700 h'0000 h'0001 h'0002 h'0003 h'0004 h'0005 h'0006 h'0007 h'0008 h'0009 h'000a h'000b reset exception vector (reserved for system use) (reserved for system use) exception vector 1 exception vector 2 exception vector table figure 2.1 exception v ector table (normal mode) pc (16 bits) exr * 1 reserved * 1 * 3 ccr ccr * 3 pc (16 bits) sp sp (sp * 2 1. when exr is not used it is not stored on the stack. 2. sp when exr is not used. 3. l g nored when returnin g . notes: (b) exception handlin g (a) subroutine branch ) figure 2.2 stack stru cture in normal mode 2.2.2 advanced mode ? address space linear access is provided to a 16-mbyt e maximum address space is provided. ? extended registers (en) the extended registers (e0 to e7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers. section 2 cpu rev. 7.00 sep. 11, 2009 page 18 of 566 rej09b0211-0700 ? instruction set all instructions and addressing modes can be used. ? exception vector table and memory indirect branch addresses in advanced mode, the top area starting at h'00000000 is allocated to the exception vector table in units of 32 bits. in each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2.3). for details of the exception vector table, see section 4, exception handling. h'00000000 h'00000003 h'00000004 h'0000000b h'0000000c h'00000010 h'00000008 h'00000007 reserved reserved reserved reserved reserved exception vector 1 exception vector 2 exception vector 3 exception vector 4 exception vector table exception vector 5 figure 2.3 excep tion vector tabl e (advanced mode) the memory indirect addressing mode (@@aa:8) employed in the jmp and jsr instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. in advanced mode the operand is a 32-bit longword operand, providing a 32-bit branch address. the upper 8 bits of these 32 bits is a reserved area that is regarded as h'00. branch addresses can be stored in the area from h'00000000 to h'000000ff. note that the first part of this range is also the exception vector table. section 2 cpu rev. 7.00 sep. 11, 2009 page 19 of 566 rej09b0211-0700 ? stack structure in advanced mode, when the program counter (pc) is pushed onto the stack in a subroutine call, and the pc, condition-code register (ccr ), and extended control register (exr) are pushed onto the stack in exception handling, they are stored as shown in figure 2.4. when exr is invalid, it is not pushed onto the stack. for details, see section 4, exception handling. pc (24 bits) exr * 1 reserved * 1 * 3 ccr pc (24 bits) sp sp (sp * 2 reserved (a) subroutine branch (b) exception handlin g notes: 1. when exr is not used it is not stored on the stack. 2. sp when exr is not used. 3. i g nored when returnin g . ) figure 2.4 stack stru cture in advanced mode section 2 cpu rev. 7.00 sep. 11, 2009 page 20 of 566 rej09b0211-0700 2.3 address space figure 2.5 shows a memory map for the h8s/2600 cpu. the h8s/2600 cpu provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-mbyte (architecturally 4-gbyte) address space in adva nced mode. the usable modes and address spaces differ depending on the product. for details on each product, refer to section 3, mcu operating modes. h'0000 h'ffff h'00000000 h'ffffffff h'00ffffff 64 kbytes 16 mbytes cannot be used in this lsi pro g ram area data area (b) advanced mode (a) normal mode figure 2.5 memory map section 2 cpu rev. 7.00 sep. 11, 2009 page 21 of 566 rej09b0211-0700 2.4 register configuration the h8s/2600 cpu has the internal registers shown in figure 2.6. there are two types of registers; general registers and control registers. the control registers are a 24-bit program counter (pc), an 8-bit extended control register (exr), an 8-bit condition code register (ccr), and a 64-bit multiply-accumulate register (mac). ti2i1i0 exr 76543210 pc mach macl mac 23 63 32 41 31 0 0 15 0 7 0 7 0 e0 e1 e2 e3 e4 e5 e6 e7 r0h r1h r2h r3h r4h r5h r6h r7h r0l r1l r2l r3l r4l r5l r6l r7l sp: pc: exr: t: i2 to i0: ccr: i: ui: stack pointer pro g ram counter extended control re g ister trace bit interrupt mask bits condition-code re g ister interrupt mask bit user bit or interrupt mask bit half-carry fla g user bit ne g ative fla g zero fla g overflow fla g carry fla g multiply-accumulate re g ister er0 er1 er2 er3 er4 er5 er6 er7 (sp) iuihunzvc ccr 76543210 h: u: n: z: v: c: mac: general re g isters (rn) and extended re g isters (en) control re g isters (cr) le g end: si g n extension ---- figure 2.6 cpu registers section 2 cpu rev. 7.00 sep. 11, 2009 page 22 of 566 rej09b0211-0700 2.4.1 general registers the h8s/2600 cpu has eight 32-bit general register s. these general registers are all functionally identical and can be used as both address register s and data registers. when a general register is used as a data register, it can be accessed as a 32-b it, 16-bit, or 8-bit register. figure 2.7 illustrates the usage of the general registers. when the genera l registers are used as 32-bit registers or address registers, they are designated by the letters er (er0 to er7). the er registers divide into 16-bit general registers designated by the letters e (e0 to e7) and r (r0 to r7). these registers are functionally equivalent, providing a maximum of sixteen 16-bit registers. the e registers (e0 to e7) are also referred to as extended registers. the r registers divide into 8-bit general register s designated by the letters rh (r0h to r7h) and rl (r0l to r7l). these registers are functionally equivalent, providing a maximum of sixteen 8- bit registers. the usage of each register can be selected independently. general register er7 has the function of stack poi nter (sp) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. figure 2.8 shows the stack. ? address re g isters ? 32-bit re g isters ? 16-bit re g isters ? 8-bit re g isters er re g isters (er0 to er7) e re g isters (extended re g isters) (e0 to e7) r re g isters (r0 to r7) rh re g isters (r0h to r7h) rl re g isters (r0l to r7l) figure 2.7 usage of general registers section 2 cpu rev. 7.00 sep. 11, 2009 page 23 of 566 rej09b0211-0700 sp (er7) free area stack area figure 2.8 stack 2.4.2 program counter (pc) this 24-bit counter indicates the address of the next instruction the cpu will execute. the length of all cpu instructions is 2 bytes (one word), so the least significant pc bit is ignored. (when an instruction is fetched, the least significant pc bit is regarded as 0.) 2.4.3 extended control register (exr) exr is an 8-bit register that manipulates the ldc, stc, andc, orc, and xorc instructions. when these instructions, except for the stc instruction, are executed, all interrupts including nmi will be masked for three states after execution is completed. bit bit name initial value r/w description 7 t 0 r/w trace bit when this bit is set to 1, a trace exception is generated each time an instruction is executed. when this bit is cleared to 0, instructions are executed in sequence. 6 to 3 ? all 1 ? reserved they are always read as 1. 2 1 0 i2 i1 i0 1 1 1 r/w r/w r/w these bits designate the interrupt mask level (0 to 7). for details, refer to section 5, interrupt controller. section 2 cpu rev. 7.00 sep. 11, 2009 page 24 of 566 rej09b0211-0700 2.4.4 condition-code register (ccr) this 8-bit register contains internal cpu status information, including an interrupt mask bit (i) and half-carry (h), negative (n), zero (z), overflow (v), and carry (c) flags. operations can be performed on the ccr bits by the ldc, stc, andc, orc, and xorc instructions. the n, z, v, and c flags are used as branching conditions for conditional branch (bcc) instructions. section 2 cpu rev. 7.00 sep. 11, 2009 page 25 of 566 rej09b0211-0700 bit bit name initial value r/w description 7 i 1 r/w interrupt mask bit masks interrupts other than nmi when set to 1. nmi is accepted regardless of the i bit setting. the i bit is set to 1 by hardware at the start of an exception- handling sequence. for details, refer to section 5, interrupt controller. 6 ui undefined r/w user bit or interrupt mask bit can be written and read by software using the ldc, stc, andc, orc, and xorc instructions. this bit cannot be used as an interrupt mask bit in this lsi. 5 h undefined r/w half-carry flag when the add.b, addx.b, sub.b, subx.b, cmp.b, or neg.b instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. when the add.w, sub.w, cmp.w, or neg.w instruction is executed, the h flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. when the add.l, sub.l, cmp.l, or neg.l instruction is executed, the h flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. 4 u undefined r/w user bit can be written and read by software using the ldc, stc, andc, orc, and xorc instructions. 3 n undefined r/w negative flag stores the value of the most significant bit of data as a sign bit. 2 z undefined r/w zero flag set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. 1 v undefined r/w overflow flag set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. section 2 cpu rev. 7.00 sep. 11, 2009 page 26 of 566 rej09b0211-0700 bit bit name initial value r/w description 0 c undefined r/w carry flag set to 1 when a carry occurs, and cleared to 0 otherwise. used by: ? add instructions, to indicate a carry ? subtract instructions, to indicate a borrow ? shift and rotate instructions, to indicate a carry the carry flag is also used as a bit accumulator by bit manipulation instructions. 2.4.5 multiply-accumulate register (mac) this 64-bit register stores the results of multiply -and-accumulate operations. it consists of two 32- bit registers denoted mach and macl. the lower 10 bits of mach are valid; the upper bits are a sign extension. 2.4.6 initial values of cpu registers reset exception handling loads the cp u's program counter (pc) from the vector table, clears the trace bit in exr to 0, and sets th e interrupt mask bits in ccr and exr to 1. the other ccr bits and the general registers are not initialized. in particular, the stack pointer (er7) is not initialized. the stack pointer should therefore be initialized by an mov.l instruction executed immediately after a reset. section 2 cpu rev. 7.00 sep. 11, 2009 page 27 of 566 rej09b0211-0700 2.5 data formats the h8s/2600 cpu can process 1-bit, 4-bit (bcd), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. bit-manipul ation instructions operate on 1-bit da ta by accessing bit n (n = 0, 1, 2, ?, 7) of byte operand data. the daa and das decimal-adjust instructions treat byte data as two digits of 4-bit bcd data. 2.5.1 general register data formats figure 2.9 shows the data formats in general registers. 70 70 msb lsb msb lsb 70 43 don?t care don?t care don?t care 70 43 70 don?t care 65432 710 70 don?t care 65432 710 don?t care rnh rnl rnh rnl rnh rnl data type re g ister number data format byte data byte data 4-bit bcd data 4-bit bcd data 1-bit data 1-bit data upper lower upper lower figure 2.9 general re gister data formats (1) section 2 cpu rev. 7.00 sep. 11, 2009 page 28 of 566 rej09b0211-0700 15 0 msb lsb 15 0 msb lsb 31 16 msb 15 0 lsb en rn ern: en: rn: rnh: rnl: msb: lsb: general re g ister er general re g ister e general re g ister r general re g ister rh general re g ister rl most si g nificant bit least si g nificant bit data type data format re g ister number word data word data rn en lon g word data le g end: ern figure 2.9 general re gister data formats (2) section 2 cpu rev. 7.00 sep. 11, 2009 page 29 of 566 rej09b0211-0700 2.5.2 memory data formats figure 2.10 shows the data formats in memo ry. the h8s/2600 cpu can access word data and longword data in memory, however word or longword data must begin at an even address. if an attempt is made to access word or longword data at an odd address, an address error does not occur, however the least significan t bit of the address is regarded as 0, so access begins the preceding address. this also a pplies to instruction fetches. when er7 is used as an address register to access the stack, the operand size should be word or longword. 70 76 543210 msb lsb msb msb lsb lsb data type address 1-bit data byte data word data address l address l address 2m address 2m+1 lon g word data address 2n address 2n+1 address 2n+2 address 2n+3 data format figure 2.10 memory data formats section 2 cpu rev. 7.00 sep. 11, 2009 page 30 of 566 rej09b0211-0700 2.6 instruction set the h8s/2600 cpu has 69 instructions. the instructions are classified by function in table 2.1. table 2.1 instructio n classification function instructions size types data transfer mov b/w/l 5 pop * 1 , push * 1 w/l ldm, stm l movfpe * 3 , movtpe * 3 b add, sub, cmp, neg b/w/l 23 arithmetic operations addx, subx, daa, das b inc, dec b/w/l adds, subs l mulxu, divxu, mulxs, divxs b/w extu, exts w/l tas * 4 b mac, ldmac, stmac, clrmac ? logic operations and, or, xor, not b/w/l 4 shift shal, shar, shll, shlr, ro tl, rotr, rotxl, rotxr b/w/l 8 bit manipulation bset, bclr, bnot, btst, bld, bild, bst, bist, band, biand, bor, bior, bxor, bixor b 14 branch bcc * 2 , jmp, bsr, jsr, rts ? 5 system control trapa, rte, sleep, ldc, stc, andc, orc, xorc, nop ? 9 block data transfer eepmov ? 1 total: 69 legend: b: byte w: word l: longword notes: 1. pop.w rn and push.w rn are identical to mov.w @sp+, rn and mov.w rn, @-sp. pop.l ern and push.l ern are identical to mov.l @sp+, ern and mov.l ern, @-sp. 2. bcc is the general name for conditional branch instructions. 3. cannot be used in this lsi. 4. only register er0, er1, er4, or er5 should be used when using the tas instruction. section 2 cpu rev. 7.00 sep. 11, 2009 page 31 of 566 rej09b0211-0700 2.6.1 table of instructions classified by function tables 2.3 to 2.10 summarize the instructions in each functional category. the notation used in tables 2.3 to 2.10 is defined below. table 2.2 operation notation symbol description rd general register (destination) * rs general register (source) * rn general register * ern general register (32-bit register) mac multiply-accumulate register (32-bit register) (ead) destination operand (eas) source operand exr extended control register ccr condition-code register n n (negative) flag in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr pc program counter sp stack pointer #imm immediate data disp displacement + addition ? subtraction multiplication division logical and logical or logical xor move ? not (logical complement) :8/:16/:24/:32 8-, 16-, 24-, or 32-bit length note: * general registers include 8-bit registers (r0h to r7h, r0l to r7l), 16-bit registers (r0 to r7, e0 to e7), and 32-bit registers (er0 to er7). section 2 cpu rev. 7.00 sep. 11, 2009 page 32 of 566 rej09b0211-0700 table 2.3 data transfer instructions instruction size * function mov b/w/l (eas) rd, rs (ead) moves data between two general registers or between a general register and memory, or moves immediate data to a general register. movfpe b cannot be used in this lsi. movtpe b cannot be used in this lsi. pop w/l @sp+ rn pops a general register from the stack. pop.w rn is identical to mov.w @sp+, rn. pop.l ern is iden tical to mov.l @sp+, ern. push w/l rn @?sp pushes a general register onto the stack. push.w rn is identical to mov.w rn, @?sp. push.l ern is identical to mov.l ern, @?sp. ldm l @sp+ rn (register list) pops two or more general registers from the stack. stm l rn (register list) @?sp pushes two or more general registers onto the stack. note: * refers to the operand size. b: byte w: word l: longword section 2 cpu rev. 7.00 sep. 11, 2009 page 33 of 566 rej09b0211-0700 table 2.4 arithmetic operations instructions instruction size * function add sub b/w/l rd rs rd, rd #imm rd performs addition or subtraction on data in two general registers, or on immediate data and data in a general register (immediate byte data cannot be subtracted from byte data in a general register. use the subx or add instruction). addx subx b rd rs c rd, rd #imm c rd performs addition or subtraction with carry on byte data in two general registers, or on immediate data and data in a general register. inc dec b/w/l rd 1 rd, rd 2 rd increments or decrements a general register by 1 or 2. (byte operands can be incremented or decremented by 1 only.) adds subs l rd 1 rd, rd 2 rd, rd 4 rd adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. daa das b rd decimal adjust rd decimal-adjusts an addition or subtracti on result in a general register by referring to the ccr to produce 4-bit bcd data. mulxu b/w rd rs rd performs unsigned multiplication on data in two general registers: either 8 bits 8 bits 16 bits or 16 bits 16 bits 32 bits. mulxs b/w rd rs rd performs signed multiplication on data in two general registers: either 8 bits 8 bits 16 bits or 16 bits 16 bits 32 bits. divxu b/w rd rs rd performs unsigned division on data in two general registers: either 16 bits 8 bits 8-bit quotient and 8-bit remainder or 32 bits 16 bits 16-bit quotient and 16-bit remainder. section 2 cpu rev. 7.00 sep. 11, 2009 page 34 of 566 rej09b0211-0700 instruction size * 1 function divxs b/w rd rs rd performs signed division on data in two general registers: either 16 bits 8 bits 8-bit quotient and 8-bit remainder or 32 bits 16 bits 16-bit quotient and 16-bit remainder. cmp b/w/l rd ? rs, rd ? #imm compares data in a general register wi th data in another general register or with immediate data, and sets ccr bits according to the result. neg b/w/l 0 ? rd rd takes the two's complement (arithmetic complement) of data in a general register. extu w/l rd (zero extension) rd extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. exts w/l rd (sign extension) rd extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit. tas * 2 b @erd ? 0, 1 ( section 2 cpu rev. 7.00 sep. 11, 2009 page 35 of 566 rej09b0211-0700 table 2.5 logic operations instructions instruction size * function and b/w/l rd rs rd, rd #imm rd performs a logical and operation on a general register and another general register or immediate data. or b/w/l rd rs rd, rd #imm rd performs a logical or operation on a general register and another general register or immediate data. xor b/w/l rd rs rd, rd #imm rd performs a logical exclusive or operation on a general register and another general register or immediate data. not b/w/l ? rd rd takes the one's complement of general register contents. note: * refers to the operand size. b: byte w: word l: longword table 2.6 shift instructions instruction size * function shal shar b/w/l rd (shift) rd performs an arithmetic shift on general register contents. 1-bit or 2-bit shifts are possible. shll shlr b/w/l rd (shift) rd performs a logical shift on general register contents. 1-bit or 2-bit shifts are possible. rotl rotr b/w/l rd (rotate) rd rotates general register contents. 1-bit or 2-bit rotations are possible. rotxl rotxr b/w/l rd (rotate) rd rotates general register contents through the carry flag. 1-bit or 2-bit rotations are possible. note: * refers to the operand size. b: byte w: word l: longword section 2 cpu rev. 7.00 sep. 11, 2009 page 36 of 566 rej09b0211-0700 table 2.7 bit manipulation instructions instruction size * function bset b 1 ( section 2 cpu rev. 7.00 sep. 11, 2009 page 37 of 566 rej09b0211-0700 instruction size * function bxor bixor b b c ( section 2 cpu rev. 7.00 sep. 11, 2009 page 38 of 566 rej09b0211-0700 table 2.8 branch instructions instruction size function bcc ? branches to a specified address if a specified condition is true. the branching conditions are listed below. mnemonic description condition bra (bt) always (true) always brn (bf) never (false) never bhi high c z = 0 bls low or same c z = 1 bcc (bhs) carry clear (high or same) c = 0 bcs (blo) carry set (low) c = 1 bne not equal z = 0 beq equal z = 1 bvc overflow clear v = 0 bvs overflow set v = 1 bpl plus n = 0 bmi minus n = 1 bge greater or equal n v = 0 blt less than n v = 1 bgt greater than z (n v) = 0 ble less or equal z (n v) = 1 jmp ? branches unconditionally to a specified address. bsr ? branches to a subroutine at a specified address. jsr ? branches to a subroutine at a specified address. rts ? returns from a subroutine. section 2 cpu rev. 7.00 sep. 11, 2009 page 39 of 566 rej09b0211-0700 table 2.9 system co ntrol instructions instruction size * function trapa ? starts trap-instruction exception handling. rte ? returns from an exception-handling routine. sleep ? causes a transition to a power-down state. ldc b/w (eas) ccr, (eas) exr moves the source operand contents or immediate data to ccr or exr. although ccr and exr are 8-bit registers, word-size transfers are performed between them and memory. the upper 8 bits are valid. stc b/w ccr (ead), exr (ead) transfers ccr or exr contents to a general register or memory. although ccr and exr are 8-bit registers, word-size transfers are performed between them and memory. the upper 8 bits are valid. andc b ccr #imm ccr, exr #imm exr logically ands the ccr or exr contents with immediate data. orc b ccr #imm ccr, exr #imm exr logically ors the ccr or exr contents with immediate data. xorc b ccr #imm ccr, exr #imm exr logically xors the ccr or exr contents with immediate data. nop ? pc + 2 pc only increments the program counter. note: * refers to the operand size. b: byte w: word l: longword section 2 cpu rev. 7.00 sep. 11, 2009 page 40 of 566 rej09b0211-0700 table 2.10 block data transfer instructions instruction size function eepmov.b eepmov.w ? ? if r4l 0 then repeat @er5+ @er6+ r4l?1 r4l until r4l = 0 else next; if r4 0 then repeat @er5+ @er6+ r4?1 r4 until r4 = 0 else next; transfers a data block. starting from the address set in er5, transfers data for the number of bytes set in r4l or r4 to the address location set in er6. execution of the next instruction begins as soon as the transfer is completed. 2.6.2 basic instruction formats this lsi instructions consist of 2-byte (1-word) units. an instruction consists of an operation field (op field), a register field (r field), an effective address extension (ea field), and a condition field (cc). figure 2.11 shows examples of instruction formats. section 2 cpu rev. 7.00 sep. 11, 2009 page 41 of 566 rej09b0211-0700 ? operation field indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. the operation field always includes the first four bits of the instruction. some instructions have two operation fields. ? register field specifies a general register. address registers ar e specified by 3 bits, and data registers by 3 bits or 4 bits. some instructions have two register fields. some have no register field. ? effective address extension 8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. ? condition field specifies the branching condition of bcc instructions. op op rn rm nop, rts, etc. add.b rn, rm, etc. mov.b @(d:16, rn), rm, etc. rn rm op ea (disp) op cc ea (disp) bra d:16, etc. (1) operation field only (2) operation field and re g ister fields (3) operation field, re g ister fields, and effective address extension (4) operation field, effective address extension, and condition field figure 2.11 instruction formats (examples) section 2 cpu rev. 7.00 sep. 11, 2009 page 42 of 566 rej09b0211-0700 2.7 addressing modes and eff ective address calculation the h8s/2600 cpu supports the eight addressing modes listed in table 2.11. each instruction uses a subset of these addressing modes. arithmetic and logic instructions can use the register direct and immediate modes. data transfer instructi ons can use all addressing modes except program- counter relative and memory indirect. bit manipulation instructions use register direct, register indirect, or the absolute addressing mode to specify an operand, and register direct (bset, bclr, bnot, and btst instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. table 2.11 addressing modes no. addressing mode symbol 1 register direct rn 2 register indirect @ern 3 register indirect with displacement @(d:16,ern)/@(d:32,ern) 4 register indirect with post-increment register indirect with pre-decrement @ern+ @ ? ern 5 absolute address @aa:8/@aa:16/@aa:24/@aa:32 6 immediate #xx:8/#xx:16/#xx:32 7 program-counter relative @(d:8,pc)/@(d:16,pc) 8 memory indirect @@aa:8 2.7.1 register direct?rn the register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. r0h to r7h and r0l to r7l can be specified as 8-bit registers. r0 to r7 and e0 to e7 can be specified as 16-bit registers. er0 to er7 can be specified as 32-bit registers. 2.7.2 register indirect?@ern the register field of the instruc tion code specifies an address re gister (ern) which contains the address of the operand on memory. if the address is a program instruction address, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (h'00). section 2 cpu rev. 7.00 sep. 11, 2009 page 43 of 566 rej09b0211-0700 2.7.3 register indirect with displacem ent?@(d:16, ern) or @(d:32, ern) a 16-bit or 32-bit displacement contained in the inst ruction is added to an address register (ern) specified by the register field of the instructio n, and the sum gives the address of a memory operand. a 16-bit displacement is sign-extended when added. 2.7.4 register indirect with post-increm ent or pre-decrement?@ern+ or @-ern register indirect with post-increment?@ern+: the register field of the instruction code specifies an address register (ern) which contains the address of a memory operand. after the operand is accessed, 1, 2, or 4 is added to the addr ess register contents and the sum is stored in the address register. the value added is 1 for byte acce ss, 2 for word transfer instruction, or 4 for longword transfer instruction. for the word or longword transfer instructions, the register value should be even. register indirect with pre-decrement?@-ern: the value 1, 2, or 4 is subtracted from an address register (ern) specified by the register fi eld in the instruction code, and the result is the address of a memory operand. the result is also stored in the address register. the value subtracted is 1 for byte access, 2 for word transf er instruction, or 4 for longword transfer instruction. for the word or longword transfer instructions, the register value should be even. 2.7.5 absolute address?@aa:8, @aa:16, @aa:24, or @aa:32 the instruction code contains th e absolute address of a memory operand. the absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32). table 2.12 indicates the acce ssible absolute address ranges. to access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) long. for an 8-bit absolute address, th e upper 24 bits are all a ssumed to be 1 (h'ffff). for a 16-bit absolute address the upper 16 bits are a sign extension. a 32-bit absolute address can access the entire address space. a 24-bit absolute address (@aa:24) indicates the address of a program instruction. the upper 8 bits are all assumed to be 0 (h'00). section 2 cpu rev. 7.00 sep. 11, 2009 page 44 of 566 rej09b0211-0700 table 2.12 absolute address access ranges absolute address normal mode * advanced mode data address 8 bits (@aa:8) h'ff00 to h'ffff h'ffff00 to h'ffffff 16 bits (@aa:16) h'0000 to h'ffff h'000000 to h'007fff, h'ff8000 to h'ffffff 32 bits (@aa:32) h'000000 to h'ffffff program instruction address 24 bits (@aa:24) note: * normal mode is not available in this lsi. 2.7.6 immediate?#xx:8, #xx:16, or #xx:32 the instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. the adds, subs, inc, and dec instructions contain immediate data implicitly. some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. the trapa instruction contains 2-bit immediate data in its instruction code, specifying a vector address. 2.7.7 program-counter relative?@(d:8, pc) or @(d:16, pc) this mode is used in the bcc and bsr instruc tions. an 8-bit or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit pc contents to generate a branch address. only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (h'00). the pc value to which the displacement is added is the addre ss of the first byte of the next instruction, so the possible branching range is ? 126 to +128 bytes ( ? 63 to +64 words) or ? 32766 to +32768 bytes ( ? 16383 to +16384 words) from the branch instruction. the resulting value should be an even number. 2.7.8 memory indirect?@@aa:8 this mode can be used by the jmp and jsr instructions. the instruction code contains an 8-bit absolute address specifying a memory operand. this memory operand contains a branch address. the upper bits of the absolute address are all a ssumed to be 0, so the address range is 0 to 255 (h'0000 to h'00ff in normal mode, h'000000 to h' 0000ff in advanced mode). in normal mode, the memory operand is a word operand and the branch address is 16 bits long. in advanced mode, the memory operand is a longword operand, the first byte of which is assumed to be 0 (h'00). section 2 cpu rev. 7.00 sep. 11, 2009 page 45 of 566 rej09b0211-0700 note that the first part of the address range is also the exception vector area. for further details, refer to section 4, exception handling. if an odd address is specified in word or longwor d memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched at the address preceding the specified address. (for further informa tion, see section 2.5.2, memory data formats.) note: normal mode is not available in this lsi. specified by @aa:8 specified by @aa:8 branch address branch address reserved (a) normal mode * (b) advanced mode note: * normal mode is not available in this lsi. figure 2.12 branch a ddress specification in memory indirect mode 2.7.9 effective address calculation table 2.13 indicates how effective addresses ar e calculated in each addressing mode. in normal mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. note: normal mode is not available in this lsi. section 2 cpu rev. 7.00 sep. 11, 2009 page 46 of 566 rej09b0211-0700 table 2.13 effective address calculation no 1 offset 1 2 4 r op 31 0 31 23 2 3 re g ister indirect with d isplacement @(d:16,ern)/@(d :32,ern) 4 r op disp r op rm op rn 31 0 31 0 r op don ?t care 31 23 31 0 don ?t care 31 0 disp 31 0 31 0 31 23 31 0 don ?t care 31 23 31 0 don ?t care 24 24 24 24 addressin g mode and instruction format effective address calculation effective address (ea) re g ister direct (rn) general re g ister contents general re g ister contents general re g ister contents general re g ister contents si g n extension re g ister indirect (@ern) re g ister indirect with post-increment or pre-decrement ? re g ister indirect with post-increment @ern + ? re g ister indirect with pre-decrement @ ? ern 1, 2, or 4 1, 2, or 4 operand size byte word lon g word operand is g eneral re g ister contents. section 2 cpu rev. 7.00 sep. 11, 2009 page 47 of 566 rej09b0211-0700 no 5 op 31 23 31 0 don ?t care abs @aa:8 7 h'ffff op 31 23 31 0 don ?t care @aa:16 op @aa:24 @aa:32 abs 15 16 31 23 31 0 don ?t care 31 23 31 0 don ?t care abs op abs 6 op imm #xx:8/#xx:16/#xx:32 8 24 24 24 24 addressin g mode and instruction format absolute address immediate effective address calculation effective address (ea) si g n extension operand is immediate data. 31 23 7 pro g ram-counter relative @(d:8,pc)/@(d:16,pc) memory indirect @@aa:8 ? normal mode * ? advanced mode 31 0 don ? t care 23 0 disp 0 31 23 31 0 don ? t care disp op 23 op 8 abs 31 0 abs h'000000 7 8 0 15 31 23 31 0 don ? t care 15 h'00 16 op abs 31 0 abs h'000000 7 8 0 31 24 24 24 note: * normal mode is not available in this lsi. pc contents si g n extension memory contents memory contents section 2 cpu rev. 7.00 sep. 11, 2009 page 48 of 566 rej09b0211-0700 2.8 processing states the h8s/2600 cpu has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. figure 2.14 shows a diagram of the processing states. figure 2. 13 indicates the state transitions. ? reset state in this state, the cpu and all on-chip peripheral modules are initialized and not operating. when the res input goes low, all current processing stops and the cpu enters the reset state. all interrupts are masked in the reset stat e. reset exception hand ling starts when the res signal changes from low to high. for details , refer to section 4, exception handling. the reset state can also be entered by a watchdog timer overflow. ? exception-handling state the exception-handling state is a transient state that occurs when the cp u alters the normal processing flow due to an exception source, such as a reset, trace, interrupt, or trap instruction. the cpu fetches a start address (vector) from th e exception vector table and branches to that address. for further details, refer to section 4, exception handling. ? program execution state in this state, the cpu executes pr ogram instructions in sequence. ? bus-released state in a product which has a bus master other than the cpu, such as a data transfer controller (dtc), the bus-released state occurs when the bus has been released in response to a bus request from a bus master other than the cpu. while the bus is released, the cpu halts operations. ? program stop state this is a power-down state in which the cpu stops operating. the program stop state occurs when a sleep instruction is executed or the cpu enters hardware standby mode. for further details, refer to section 20, power-down modes. section 2 cpu rev. 7.00 sep. 11, 2009 page 49 of 566 rej09b0211-0700 pro g ram execution state exception handlin g state pro g ram halt state bus-released state reset state * end of bus request bus request interrupt request sleep instruction r es = h i g h stby = hi g h, res = low notes: from any state, a transition to hardware standby mode occurs when stby g oes low. * from any state except hardware standby mode, a transition to the reset state occurs whenever res g oes low. a transition can also be made to the reset state when the watchdo g timer overflows. bus request end of bus request request for exception handlin g end of exception handlin g figure 2.13 state transitions 2.9 usage notes 2.9.1 usage notes on bit manipulation instructions the bset, bclr, bnot, bst, and bist instructions are used to read data in bytes, then, after bit manipulation, they write data in bytes again. therefore, special care is necessary to use these instructions for the registers and the ports that include write-only bit. the bclr instruction can be used to clear the flags in the internal i/o registers to 0. in this time, if it is obvious that the flag has been set to 1 in the interrupt processing routine or other processing, there is no need to read the flag beforehand. section 2 cpu rev. 7.00 sep. 11, 2009 page 50 of 566 rej09b0211-0700 section 3 mcu operating modes rev. 7.00 sep. 11, 2009 page 51 of 566 rej09b0211-0700 section 3 mcu operating modes 3.1 operating mode selection this lsi supports only operating mode 7, that is, the advanced single-chip mode. the operating mode is determined by the setting of the mode pins (md2 to md0). only mode 7 can be used in this lsi. therefore, all mode pins must be fixed high, as shown in table 3.1. do not change the mode pin settings during operation. table 3.1 mcu operating mode selection external data bus mcu operating mode md2 md1 md0 cpu operating mode description on-chip rom initial width max width 7 1 1 1 advanced mode single-chip mode enabled ? ? 3.2 register descriptions the following registers are related to the operating mode. for details on register addresses and register states during each processing, refe r to appendix a, on-chip i/o register. ? mode control register (mdcr) ? system control register (syscr) section 3 mcu operating modes rev. 7.00 sep. 11, 2009 page 52 of 566 rej09b0211-0700 3.2.1 mode control register (mdcr) bit bit name intial value r/w descriptions 7 ? 1 r/w reserved only 1 should be written to this bit. 6 to 3 ? all 0 ? reserved these bits are always read as 0 and cannot be modified. 2 1 0 mds2 mds1 mds0 ? ? ? r r r these bits indicate the input levels at pins md2 to md0 (the current operating mode). bits mds2 to mds0 correspond to md2 to md0. mds2 to mds0 are read-only bits and they cannot be written to. the mode pin (md2 to md0) input levels are latched into these bits when mdcr is read. these latches are canceled by a reset. these latches are canceled by a reset. section 3 mcu operating modes rev. 7.00 sep. 11, 2009 page 53 of 566 rej09b0211-0700 3.2.2 system control register (syscr) syscr is an 8-bit readable/writable register that selects saturating or non-saturating calculation for the mac instruction, selects the interrupt control mode and the detected edge for nmi, and enables or disables on-chip ram. bit bit name intial value r/w descriptions 7 macs 0 ? mac saturation selects either saturating or non-saturating calculation for the mac instruction. 0: non-saturating calculation for the mac instruction 1: saturating calculation for the mac instruction 6 ? 0 ? reserved this bit is always read as 0 and cannot be modified. 5 4 intm1 intm0 0 0 r/w r/w these bits select the control mode of the interrupt controller. for details of the interrupt control modes, see section 5.6, interrupt control modes and interrupt operation. 00: interrupt control mode 0 01: setting prohibited 10: interrupt control mode 2 11: setting prohibited 3 nmieg 0 r/w nmi edge select selects the valid edge of the nmi interrupt input. 0: an interrupt is requested at the falling edge of nmi input 1: an interrupt is requested at the rising edge of nmi input 2, 1 ? all 0 ? reserved these bits are always read as 0 and cannot be modified. 0 rame 1 r/w ram enable enables or disables on-chip ram. the rame bit is initialized when the reset status is released. 0: on-chip ram is disabled 1: on-chip ram is enabled section 3 mcu operating modes rev. 7.00 sep. 11, 2009 page 54 of 566 rej09b0211-0700 3.3 pin functions in each operating mode the cpu can access a 16-mbyte address space in ad vanced mode. the on-chip rom is enabled, however external addresses cannot be accessed. all i/o ports are available for use as input-output ports. 3.3.1 pin functions table 3.2 shows their functions in mode 7. table 3.2 pin functions in each mode port mode 7 port 1 p10 p p11 to p13 port a pa3 to pa0 p port b p port c p port d p port f pf7 p * /c pf6 to pf4 p pf3 pf2 to pf0 legend: p: i/o port a: address bus output d: data bus i/o c: control signals, clock i/o * : after reset section 3 mcu operating modes rev. 7.00 sep. 11, 2009 page 55 of 566 rej09b0211-0700 3.4 address map figure 3.1 shows the address map in each operating mode. h'000000 h'01ffff h'ffe000 h'ffefbf h'fff800 h'ffffc0 h'ffffff h'ffff3f h'ffff60 h'ffffbf h'000000 h'01ffff h'00ffff h'ffe000 h'ffefbf h'fff800 h'ffffc0 h'ffffff h'ffff3f h'ffff60 h'ffffbf h8s/2612, h8s/2616 h8s/2611, h8s/2614 on-chip rom (f-ztat/mask rom * ) on-chip rom (mask rom) on-chip ram on-chip ram on-chip i/o re g isters on-chip ram on-chip ram on-chip i/o re g isters on-chip i/o re g isters on-chip i/o re g isters rom: 128 kbytes, ram: 4 kbytes mode 7 advanced sin g le-chip mode rom: 64 kbytes, ram: 4 kbytes mode 7 advanced sin g le-chip mode note: * mask rom version is available only in h8s/2616. figure 3.1 address map (h8s/2612, h8s/2611, h8s/2616, h8s/2614) section 3 mcu operating modes rev. 7.00 sep. 11, 2009 page 56 of 566 rej09b0211-0700 section 4 exception handling rev. 7.00 sep. 11, 2009 page 57 of 566 rej09b0211-0700 section 4 exception handling 4.1 exception handling types and priority as table 4.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. exception handling is prioritized as shown in table 4.1. if two or more exceptions occur simultaneously, they are accepted and processed in order of priority. excep tion sources, the stack structure, and operation of the cpu vary depending on the interrupt control mode. for details on the interrupt control mode, refer to section 5, interrupt controller. table 4.1 exception types and priority priority exception type start of exception handling high reset starts immediately after a low-to-high transition at the res pin, or when the watchdog timer overflows. the cpu enters the reset state when the res pin is low. trace * 1 starts when execution of the current instruction or exception handling ends, if the trace (t) bit in the exr is set to 1. direct transition starts when a direction transition occurs as the result of sleep instruction execution. interrupt starts when execution of the current instruction or exception handling ends, if an interrupt request has been issued * 2 . low trap instruction * 3 started by execution of a trap instruction (trapa). notes: 1. traces are enabled only in interrupt control mode 2. trace exception handling is not executed after execution of an rte instruction. 2. interrupt detection is not performed on completion of andc, orc, xorc, or ldc instruction execution, or on completion of reset exception handling. 3. trap instruction exception handling requests are accepted at all times in program execution state. 4.2 exception sources and exception vector table different vector addresses are a ssigned to different exception sources. table 4.2 lists the exception sources and their vector addresses. since the usable modes differ depending on the product, for details on each product, refer to section 3, mcu operating modes. section 4 exception handling rev. 7.00 sep. 11, 2009 page 58 of 566 rej09b0211-0700 table 4.2 exception handling vector table vector address * 1 exception source vector number normal mode * 2 advanced mode power-on reset 0 h'0000 to h'0001 h'0000 to h'0003 manual reset * 2 1 h'0002 to h'0003 h'0004 to h'0007 reserved for system use 2 h'0004 to h'0005 h'0008 to h'000b 3 h'0006 to h'0007 h'000c to h'000f 4 h'0008 to h'0019 h'0010 to h'0013 trace 5 h'000a to h'000b h'0014 to h'0017 interrupt (direct transitions) * 2 6 h'000c to h'000d h'0018 to h'001b interrupt (nmi) 7 h'000e to h'000f h'001c to h'001f trap instruction (#0) 8 h'0010 to h'0011 h'0020 to h'0023 (#1) 9 h'0012 to h'0013 h'0024 to h'0027 (#2) 10 h'0014 to h'0015 h'0028 to h'002b (#3) 11 h'0016 to h'0017 h'002c to h'002f reserved for system use 12 h'0018 to h'0019 h'0030 to h'0033 13 h'001a to h'001b h'0034 to h'0037 14 h'001c to h'001d h'0038 to h'003b 15 h'001e to h'001f h'003c to h'003f external interrupt irq0 16 h'0020 to h'0021 h'0040 to h'0043 irq1 17 h'0022 to h'0023 h'0044 to h'0047 irq2 18 h'0024 to h'0025 h'0048 to h'004b irq3 19 h'0026 to h'0027 h'004c to h'004f irq4 20 h'0028 to h'0029 h'0050 to h'0053 irq5 21 h'002a to h'002b h'0054 to h'0057 reserved for system use 22 h'002c to h'002d h'0058 to h'005b 23 h'002e to h'002f h'005c to h'005f internal interrupt * 3 24 ? 127 h'0030 to h'0031 ? h'00fe to h'00ff h'0060 to h'0063 ? h'01fc to h'01ff notes: 1. lower 16 bits of the address. 2. not available in this lsi. 3. for details of internal interrupt vectors, see section 5.5, interrupt exception handling vector table. section 4 exception handling rev. 7.00 sep. 11, 2009 page 59 of 566 rej09b0211-0700 4.3 reset a reset has the highest exception priority. when the res pin goes low, all processing halts and this lsi enters the reset. to ensure that this lsi is reset, hold the res pin low for at least 20 ms at power-up. to reset the chip during operation, hold the res pin low for at least 20 states. a reset initializes the internal state of the cpu and the registers of on-chip supporting modules. the chip can also be reset by overflow of the watchdog timer. for details see section 13, watchdog timer. the interrupt control mode is 0 immediately after reset. 4.3.1 reset exception handling when the res pin goes high after being held low for the necessary time, this lsi starts reset exception handling as follows: 1. the internal state of the cpu and the registers of the on-chip supporting modules are initialized, the t bit is cleared to 0 in exr, and the i bit is set to 1 in exr and ccr. 2. the reset exception handling vector address is read and transferred to the pc, and program execution starts from the ad dress indicated by the pc. figures 4.1 and 4.2 show examples of the reset sequence. section 4 exception handling rev. 7.00 sep. 11, 2009 page 60 of 566 rej09b0211-0700 res hi g h vector fetch internal processin g prefetch of first pro g ram instruction (1)(3) reset exception handlin g vector address(when reset, (1)=h'000000, (3)=h'000002) (2)(4) start address (contents of reset exception handlin g vector address) (5) start address ((5)=(2)(4)) (6) first pro g ram instruction internal address bus internal read si g nal internal write si g nal internal data bus (1) (2) (4) (6) (3) (5) figure 4.1 reset sequence (advanced mode with on-chip rom enabled) section 4 exception handling rev. 7.00 sep. 11, 2009 page 61 of 566 rej09b0211-0700 res rd hwr , lwr d15 to d0 hi g h * * * address bus vector fetch internal processin g prefetch of first pro g ram instruction (1) (2) (4) (6) (3) (5) (1)(3) reset exception handlin g vector address(when reset, (1)=h'000000, (3)=h'000002) (2)(4) start address (contents of reset exception handlin g vector address) (5) start address ((5)=(2)(4)) (6) first pro g ram instruction note: * three pro g ram wait states are inserted. figure 4.2 reset sequence (advanced mode with on-chip rom disabled: cannot be used in this lsi) 4.3.2 interrupts after reset if an interrupt is accepted after a reset and before the stack pointer (sp) is initialized, the pc and ccr will not be saved correctly, leading to a program crash. to prevent this, all interrupt requests, including nmi, are disabled immedi ately after a reset. since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: mov.l #xx: 32, sp). 4.3.3 state of on-chip supporting modules after reset release after reset release, mstpcra to mstpcrc are initialized to h'3f, h'ff, and h'ff, respectively, and all modules except the dtc enter module stop mode. consequently, on-chip supporting module registers cannot be read or written to. re gister reading and writin g is enabled when the module stop mode is exited. section 4 exception handling rev. 7.00 sep. 11, 2009 page 62 of 566 rej09b0211-0700 4.4 traces traces are enabled in interrupt control mode 2. trace mode is not activated in interrupt control mode 0, irrespective of the state of the t bit. for details of interrupt control modes, see section 5, interrupt controller. if the t bit in exr is set to 1, trace mode is activated. in trac e mode, a trace exception occurs on completion of each instruction. trace mode is not affected by interrupt masking. table 4.3 shows the state of ccr and exr after execution of trace exception handling. trace mode is canceled by clearing the t bit in exr to 0. the t bit saved on the stack retains its value of 1, and when control is returned from the trace excep tion handling routine by the rte instruction, trace mode resumes. trace exception handling is not carried out after execution of the rte instruction. interrupts are accepted even within th e trace exception handling routine. table 4.3 status of ccr and exr after trace exception handling ccr exr interrupt control mode i ui i2 to i0 t 0 trace exception handling cannot be used. 2 1 ? ? 0 legend: 1: set to 1 0: cleared to 0 ?: retains value prior to execution 4.5 interrupts interrupts are controlled by the interrupt controller. the interrupt controller has two interrupt control modes and can assign interrupts other than nmi to eight priority/mask levels to enable multiplexed interrupt control. the source to start interrupt exception handling and the vector address differ depending on the product. for deta ils, refer to section 5, interrupt controller. interrupt exception handling is conducted as follows: 1. the values in the program counter (pc), condition code register (ccr), and extended control register (exr) are saved to the stack. 2. the interrupt mask bit is updated and the t bit is cleared to 0. 3. a vector address corresponding to the interrupt so urce is generated, the st art address is loaded from the vector table to the pc, and program execution begins from that address. section 4 exception handling rev. 7.00 sep. 11, 2009 page 63 of 566 rej09b0211-0700 4.6 trap instruction trap instruction exception handling starts when a trapa instruction is executed. trap instruction exception handling can be executed at a ll times in the program execution state. trap instruction exception handling is conducted as follows: 1. the values in the program counter (pc), condition code register (ccr), and extended control register (exr) are saved to the stack. 2. the interrupt mask bit is updated and the t bit is cleared. 3. a vector address corresponding to the interrupt source is generated, the start address is loaded from the vector table to the pc, and prog ram execution starts from that address. the trapa instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code. table 4.4 shows the status of ccr and exr after execution of trap instruction exception handling. table 4.4 status of ccr and exr after trap instruction exception handling ccr exr interrupt control mode i ui i2 to i0 t 0 1 ? ? ? 2 1 ? ? 0 legend: 1: set to 1 0: cleared to 0 ?: retains value prior to execution section 4 exception handling rev. 7.00 sep. 11, 2009 page 64 of 566 rej09b0211-0700 4.7 stack status after exception handling figure 4.3 shows the stack after completion of trap instruction exception handling and interrupt exception handling. ccr ccr * 1 pc (16 bits) sp exr reserved * 1 ccr ccr * 1 pc (16 bits) sp ccr pc (24 bits) sp exr reserved * 1 ccr pc (24 bits) sp (a) normal modes * 2 (b) advanced modes interrupt control mode 0 interrupt control mode 2 interrupt control mode 0 interrupt control mode 2 notes: 1. 2. i g nored on return. normal modes are not available in this lsi. figure 4.3 stack status after exception handling section 4 exception handling rev. 7.00 sep. 11, 2009 page 65 of 566 rej09b0211-0700 4.8 usage note when accessing word data or longword data, this lsi assumes that the lowest address bit is 0. the stack should always be accessed by word transfer in struction or longword transfer instruction, and the value of the stack pointer (sp, er7) should always be kept even. use the following instructions to save registers: push.w rn (or mov.w rn, @-sp) push.l ern (or mov.l ern, @-sp) use the following instructions to restore registers: pop.w rn (or mov.w @sp+, rn) pop.l ern (or mov.l @sp+, ern) setting sp to an odd value may lead to a malfunction. figure 4.4 shows an example of what happens when the sp value is odd. sp ccr: pc: r1l: sp: condition code register program counter general register r1l stack pointer ccr sp sp r1l h'fffefa h'fffefb h'fffefc h'fffefd h'fffefe h'fffeff pc pc trapa instruction executed sp set to h'fffeff data saved above sp mov.b r1l, @-er7 executed contents of ccr lost address legend: note: this diagram illustrates an example in which the interrupt control mode is 0, in advanced mode. figure 4.4 operation when sp value is odd section 4 exception handling rev. 7.00 sep. 11, 2009 page 66 of 566 rej09b0211-0700 section 5 interrupt controller rev. 7.00 sep. 11, 2009 page 67 of 566 rej09b0211-0700 section 5 interrupt controller 5.1 features ? two interrupt control modes ? any of two interrupt control modes can be set by means of the intm1 and intm0 bits in the system control register (syscr). ? priorities settable with ipr ? an interrupt priority register (ipr) is provided for setting interrupt priorities. eight priority levels can be set for each module for all interrupts except nmi. nmi is assigned the highest priority level of 8, and can be accepted at all times. ? independent vector addresses ? all interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine. ? seven external interrupts ? nmi is the highest-priority interrupt, and is accepted at all times. rising edge or falling edge can be selected for nmi. falling edge, ri sing edge, or both edge detection, or level sensing, can be selected for irq0 to irq5. ? dtc control ? the dtc can be activated by an interrupt request. note: no dtc is implemented in the h8s/2614 and h8s/2616. section 5 interrupt controller rev. 7.00 sep. 11, 2009 page 68 of 566 rej09b0211-0700 a block diagram of the interrupt controller is shown in figure 5.1. syscr nmi input irq input internal interrupt request swdtend to tei2 nmieg intm1, intm0 nmi input unit irq input unit isr iscr ier ipr interrupt controller priority determination interrupt request vector number i i2 to i0 ccr exr cpu iscr: ier: isr: ipr: syscr: irq sense control re g ister irq enable re g ister irq status re g ister interrupt priority re g ister system control re g ister le g end: figure 5.1 block diagram of interrupt controller section 5 interrupt controller rev. 7.00 sep. 11, 2009 page 69 of 566 rej09b0211-0700 5.2 input/output pins table 5.1 summarizes the pins of the interrupt controller. table 5.1 pin configuration name i/o function nmi input nonmaskable external interrupt rising or falling edge can be selected irq5 irq4 irq3 irq2 irq1 irq0 input input input input input input maskable external interrupts rising, falling, or both edges, or level sensing, can be selected 5.3 register descriptions the interrupt controller has the following registers. for details on system control register (syscr), refer to section 3.2.2, system control register (syscr). for details on register addresses and register states during each process, refer to appendix a, on-chip i/o register. ? system control register (syscr) ? irq sense control register h (iscrh) ? irq sense control register l (iscrl) ? irq enable register (ier) ? irq status register (isr) ? interrupt priority register a (ipra) ? interrupt priority register b (iprb) ? interrupt priority register c (iprc) ? interrupt priority register d (iprd) ? interrupt priority register e (ipre) ? interrupt priority register f (iprf) ? interrupt priority register g (iprg) ? interrupt priority register h (iprh) ? interrupt priority register j (iprj) ? interrupt priority register k (iprk) ? interrupt priority register m (iprm) section 5 interrupt controller rev. 7.00 sep. 11, 2009 page 70 of 566 rej09b0211-0700 5.3.1 interrupt priority registers a to h, j, k, m (ipra to iprh,iprj, iprk, iprm) the ipr registers are eleven 8-bit readable/writable registers that set priorities (levels 7 to 0) for interrupts other than nmi. the correspondence between interrupt sources and ipr settings is shown in table 5.2. setting a value in the range from h'0 to h'7 in the 3-bit groups of bits 0 to 2 and 4 to 6 sets the priority of the corresponding interrupt. bit bit name initial value r/w description 7 ? 0 ? reserved these bits are always read as 0. 6 5 4 ipr6 ipr5 ipr4 1 1 1 r/w r/w r/w sets the priority of the corresponding interrupt source. 000: priority level 0 (lowest) 001: priority level 1 010: priority level 2 011: priority level 3 100: priority level 4 101: priority level 5 110: priority level 6 111: priority level 7 (highest) 3 ? 0 ? reserved these bits are always read as 0. 2 1 0 ipr2 ipr1 ipr0 1 1 1 r/w r/w r/w sets the priority of the corresponding interrupt source. 000: priority level 0 (lowest) 001: priority level 1 010: priority level 2 011: priority level 3 100: priority level 4 101: priority level 5 110: priority level 6 111: priority level 7 (highest) section 5 interrupt controller rev. 7.00 sep. 11, 2009 page 71 of 566 rej09b0211-0700 5.3.2 irq enable register (ier) ier is an 8-bit readable/writable register that controls the enabling and disabling of interrupt requests irq0 to irq5. bit bit name initial value r/w description 7, 6 ? all 0 r/w reserved only 0 should be written to these bits. 5 irq5e 0 r/w irq5 enable the irq5 interrupt request is enabled when this bit is 1. 4 irq4e 0 r/w irq4 enable the irq4 interrupt request is enabled when this bit is 1. 3 irq3e 0 r/w irq3 enable the irq3 interrupt request is enabled when this bit is 1. 2 irq2e 0 r/w irq2 enable the irq2 interrupt request is enabled when this bit is 1. 1 irq1e 0 r/w irq1 enable the irq1 interrupt request is enabled when this bit is 1. 0 irq0e 0 r/w irq0 enable the irq0 interrupt request is enabled when this bit is 1. 5.3.3 irq sense control registers h and l (iscrh, iscrl) the iscr registers are 16-bit readab le/writable registers that select the source that generates an interrupt request at pins irq0 to irq5 . section 5 interrupt controller rev. 7.00 sep. 11, 2009 page 72 of 566 rej09b0211-0700 bit bit name initial value r/w description 15 to 12 ? all 0 r/w reserved only 0 should be written to these bits. 11 10 irq5scb irq5sca 0 0 r/w r/w irq5 sense control b irq5 sense control a 00: interrupt request generated at irq5 input level low 01: interrupt request generated at falling edge of irq5 input 10: interrupt request generated at rising edge of irq5 input 11: interrupt request generated at both falling and rising edges of irq5 input 9 8 irq4scb irq4sca 0 0 r/w r/w irq4 sense control b irq4 sense control a 00: interrupt request generated at irq4 input level low 01: interrupt request generated at falling edge of irq4 input 10: interrupt request generated at rising edge of irq4 input 11: interrupt request generated at both falling and rising edges of irq4 input 7 6 irq3scb irq3sca 0 0 r/w r/w irq3 sense control b irq3 sense control a 00: interrupt request generated at irq3 input level low 01: interrupt request generated at falling edge of irq3 input 10: interrupt request generated at rising edge of irq3 input 11: interrupt request generated at both falling and rising edges of irq3 input section 5 interrupt controller rev. 7.00 sep. 11, 2009 page 73 of 566 rej09b0211-0700 bit bit name initial value r/w description 5 4 irq2scb irq2sca 0 0 r/w r/w irq2 sense control b irq2 sense control a 00: interrupt request generated at irq2 input level low 01: interrupt request generated at falling edge of irq2 input 10: interrupt request generated at rising edge of irq2 input 11: interrupt request generated at both falling and rising edges of irq2 input 3 2 irq1scb irq1sca 0 0 r/w r/w irq1 sense control b irq1 sense control a 00: interrupt request generated at irq1 input level low 01: interrupt request generated at falling edge of irq1 input 10: interrupt request generated at rising edge of irq1 input 11: interrupt request generated at both falling and rising edges of irq1 input 1 0 irq0scb irq0sca 0 0 r/w r/w irq0 sense control b irq0 sense control a 00: interrupt request generated at irq0 input level low 01: interrupt request generated at falling edge of irq0 input 10: interrupt request generated at rising edge of irq0 input 11: interrupt request generated at both falling and rising edges of irq0 input section 5 interrupt controller rev. 7.00 sep. 11, 2009 page 74 of 566 rej09b0211-0700 5.3.4 irq status register (isr) isr is an 8-bit readable/writable register that indicates the status of irq0 to irq5 interrupt requests. bit bit name initial value r/w description 7, 6 ? all 0 r/w reserved only 0 should be written to these bits. 5 4 3 2 1 0 irq5f irq4f irq3f irq2f irq1f irq0f 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w [setting condition] ? when the interrupt source selected by the iscr registers occurs [clearing conditions] ? cleared by reading irqnf flag when irqnf = 1, then writing 0 to irqnf flag ? when interrupt exception handling is executed when low-level detection is set and irqn input is high ? when irqn interrupt exception handling is executed when falling, rising, or both-edge detection is set ? when the dtc is activated by an irqn interrupt, and the disel bit in mrb of the dtc is cleared to 0 (n = 5 to 0) section 5 interrupt controller rev. 7.00 sep. 11, 2009 page 75 of 566 rej09b0211-0700 5.4 interrupt 5.4.1 external interrupts there are seven external interrupts: nmi and ir q0 to irq5. these interrupts can be used to restore this lsi from software standby mode. nmi interrupt: nmi is the highest-priority interrupt, and is always accepted by the cpu regardless of the interrupt control mode or the status of the cpu interrupt mask bits. the nmieg bit in syscr can be used to select whether an interrupt is requested at a rising edge or a falling edge on the nmi pin. irq0 to irq5 interrupts: interrupts irq0 to irq5 are requested by an input signal at pins irq0 to irq5 . interrupts irq0 to irq5 have the following features: ? using iscr, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, at pins irq0 to irq5 . ? enabling or disabling of interrupt requests irq0 to irq5 can be selected with ier. ? the interrupt priority level can be set with ipr. ? the status of interrupt requests irq0 to irq5 is indicated in isr. isr fl ags can be cleared to 0 by software. the detection of irq0 to irq5 interrupts does not depend on whether the relevant pin has been set for input or output. however, when a pin is used as an external interrupt input pin, do not clear the corresponding ddr to 0; and use the pin as an i/o pin for another function. a block diagram of interrupts irq0 to irq5 is shown in figure 5.2. irqn interrupt request irqne irqnf s r q clear si g nal ed g e/level detection circuit irqnsca, irqnscb irqn input note: n = 5 to 0 figure 5.2 block diagram of interrupts irq0 to irq5 section 5 interrupt controller rev. 7.00 sep. 11, 2009 page 76 of 566 rej09b0211-0700 5.4.2 internal interrupts the sources for internal interrupts from on-chip supporting modules have the following features: ? for each on-chip supporting module there are flag s that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts. if both of these are set to 1 for a particular interrupt source, an interrupt request is issued to the interrupt controller. ? the interrupt priority level can be set by means of ipr. ? the dtc can be activated by a tpu, sci, or other interrupt request. ? when the dtc is activated by an interrupt request, it is not affected by the interrupt control mode or cpu interrupt mask bit. 5.5 interrupt exception handling vector table table 5.2 shows interrupt exception handling sources , vector addresses, and interrupt priorities. for default priorities, the lower the vector number, the higher the priority. priorities among modules can be set by means of the ipr. modules set at the same priority will conform to their default priorities. priorities within a module are fixed. note: dtc, pc break controller, and mmt interrupt sources are not implemented in the h8s/2614 and h8s/2616. section 5 interrupt controller rev. 7.00 sep. 11, 2009 page 77 of 566 rej09b0211-0700 table 5.2 interrupt sources, vector addresses, and interrupt priorities vector address * interrupt source origin of interrupt source vector number advanced mode ipr priority nmi 7 h'001c high external pin irq0 16 h'0040 ipra6 to ipra4 irq1 17 h'0044 ipra2 to ipra0 irq2 18 h'0048 iprb6 to iprb4 irq3 19 h'004c irq4 20 h'0050 iprb2 to iprb0 irq5 21 h'0054 ? reserved for system use 22 h'0058 reserved for system use 23 h'005c dtc swdtend 24 h'0060 iprc2 to iprc0 watchdog timer 0 wovi0 25 h'0064 iprd6 to iprd4 pc break pc break 27 h'006c ipre6 to ipre4 a/d adi 28 h'0070 ipre2 to ipre0 tgia_0 32 h'0080 iprf6 to iprf4 tpu channel 0 tgib_0 33 h'0084 tgic_0 34 h'0088 tgid_0 35 h'008c tciv_0 36 h'0090 tgia_1 40 h'00a0 iprf2 to iprf0 tpu channel 1 tgib_1 41 h'00a4 tciv_1 42 h'00a8 tciu_1 43 h'00ac tgia_2 44 h'00b0 iprg6 to iprg4 tpu channel 2 tgib_2 45 h'00b4 tciv_2 46 h'00b8 tciu_2 47 h'00bc tgia_3 48 h'00c0 iprg2 to iprg0 tpu channel 3 tgib_3 49 h'00c4 tgic_3 50 h'00c8 low section 5 interrupt controller rev. 7.00 sep. 11, 2009 page 78 of 566 rej09b0211-0700 vector address * interrupt source origin of interrupt source vector number advanced mode ipr priority tgid_3 51 h'00cc high tpu channel 3 tciv_3 52 h'00d0 tgia_4 56 h'00e0 iprh6 to iprh4 tpu channel 4 tgib_4 57 h'00e4 tciv_4 58 h'00e8 tciu_4 59 h'00ec tgia_5 60 h'00f0 iprh2 to iprh0 tpu channel 5 tgib_5 61 h'00f4 tciv_5 62 h'00f8 tciu_5 63 h'00fc eri_0 80 h'0140 iprj2 to iprj0 sci channel 0 rxi_0 81 h'0144 txi_0 82 h'0148 tei_0 83 h'014c eri_1 84 h'0150 iprk6 to iprk4 sci channel 1 rxi_1 85 h'0154 txi_1 86 h'0158 tei_1 87 h'015c eri_2 88 h'0160 iprk2 to iprk0 sci channel 2 rxi_2 89 h'0164 txi_2 90 h'0168 tei_2 91 h'016c hcan ers0, ovr0 104 h'01a0 iprm6 to iprm4 rm0 105 h'01a4 rm1 106 h'01a8 sle0 107 h'01ac mmt tgimn 108 h'01b0 iprm2 to iprm0 tginn 109 h'01b4 poein 110 h'01b8 ? reserved for system use 111 h'01bc low note: * lower 16 bits of the start address. section 5 interrupt controller rev. 7.00 sep. 11, 2009 page 79 of 566 rej09b0211-0700 5.6 interrupt control modes and interrupt operation the interrupt controller has two modes: interrupt control mode 0 and interrupt control mode 2. interrupt operations differ depending on the interrupt control mode. the interrupt control mode is selected by syscr. table 5.3 shows the differences between interrupt control mode 0 and interrupt control mode 2. table 5.3 interrupt control modes interrupt control mode priority setting registers interrupt mask bits description 0 default i the priorities of interrupt sources are fixed at the default settings. interrupt sources, except for nmi, are masked by the i bit. 2 ipr i2 to i0 8 priority levels other than nmi can be set with ipr. 8-level interrupt mask control is performed by bits i2 to i0. 5.6.1 interrupt control mode 0 in interrupt control mode 0, interrupt requests other than for nmi are masked by the i bit of the ccr in the cpu. figure 5.3 shows a flowchart of the interrupt acceptance operation in this case. 1. if an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. if the i bit is set to 1, only an nmi interrupt is accepted, and other interrupt requests are held pending. if the i bit is cleared, an interrupt request is accepted. 3. interrupt requests are sent to the interrupt c ontroller, the highest-ranke d interrupt according to the priority system is accepted, and ot her interrupt requests are held pending. 4. when the cpu accepts an interrupt request , it starts interrupt exception handling after execution of the current instru ction has been completed. 5. the pc and ccr are saved to the stack area by interrupt exception handling. the pc saved on the stack shows the address of the first instruc tion to be executed after returning from the interrupt handling routine. 6. next, the i bit in ccr is set to 1. this masks all interrupts except nmi. section 5 interrupt controller rev. 7.00 sep. 11, 2009 page 80 of 566 rej09b0211-0700 7. the cpu generates a vector address for th e accepted interrupt and st arts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. pro g ram execution status interrupt g enerated? nmi irq0 irq1 tei_2 i = 0 save pc and ccr i 1 read vector address branch to interrupt handlin g routine yes no yes yes yes no no no yes yes no hold pendin g figure 5.3 flowchart of proce dure up to interrupt acceptance in interrupt control mode 0 section 5 interrupt controller rev. 7.00 sep. 11, 2009 page 81 of 566 rej09b0211-0700 5.6.2 interrupt control mode 2 in interrupt control mode 2, mask control is applied to eight levels for interrupt requests other than nmi by comparing the exr interrupt mask level (i2 to i0 bits) in the cpu and the ipr setting. figure 5.4 shows a flowchart of the inte rrupt acceptance operation in this case. 1. if an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. when interrupt requests are sent to the interrupt controller, the interrupt with the highest priority according to the interrupt priority levels set in ipr is selected, and lower-priority interrupt requests are held pending. if a number of interrupt requests with the same priority are generated at the same time, the interrupt request with the highest priority according to the priority system shown in table 5.2 is selected. 3. next, the priority of the selected interrupt request is compared with the interrupt mask level set in exr. an interrupt request with a priority no higher than the mask level set at that time is held pending, and only an interrupt request with a priority higher than the interrupt mask level is accepted. 4. when the cpu accepts an interrupt request , it starts interrupt exception handling after execution of the current instru ction has been completed. 5. the pc, ccr, and exr are saved to the stack area by interrupt exception handling. the pc saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. 6. the t bit in exr is cleared to 0. the interrupt mask level is rewritten with the priority level of the accepted interrupt. if the accepted interrupt is nmi, the in terrupt mask level is set to h'7. 7. the cpu generates a vector address for th e accepted interrupt and st arts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. section 5 interrupt controller rev. 7.00 sep. 11, 2009 page 82 of 566 rej09b0211-0700 yes pro g ram execution status interrupt g enerated? nmi level 6 interrupt? mask level 5 or below? level 7 interrupt? mask level 6 or below? save pc, ccr, and exr clear t bit to 0 update mask level read vector address branch to interrupt handlin g routine hold pendin g level 1 interrupt? mask level 0? yes yes no yes yes yes no yes yes no no no no no no figure 5.4 flowchart of procedure up to interrupt acceptance in control mode 2 section 5 interrupt controller rev. 7.00 sep. 11, 2009 page 83 of 566 rej09b0211-0700 5.6.3 interrupt exception handling sequence figure 5.5 shows the interrupt exception handling sequence. the example shown is for the case where interrupt control mode 0 is set in advan ced mode, and the program area and stack area are in on-chip memory. section 5 interrupt controller rev. 7.00 sep. 11, 2009 page 84 of 566 rej09b0211-0700 (14) (12) (10) (6) (4) (2) (1) (5) (7) (9) (11) (13) interrupt service routine instruction prefetch internal operation vector fetch stack instruction prefetch internal operation interrupt acceptance interrupt level determination wait for end of instruction interrupt request si g nal internal address bus internal read si g nal internal write si g nal internal data bus (3) (1) (2) (4) (3) (5) (7) instruction prefetch address (not executed. this is the contents of the saved pc, the return address) instruction code (not executed) instruction prefetch address (not executed) sp-2 sp-4 saved pc and saved ccr vector address interrupt handlin g routine start address (vector address contents) interrupt handlin g routine start address ((13) = (10)(12)) first instruction of interrupt handlin g routine (6) (8) (9) (11) (10) (12) (13) (14) (8) figure 5.5 interrupt exception handling section 5 interrupt controller rev. 7.00 sep. 11, 2009 page 85 of 566 rej09b0211-0700 5.6.4 interrupt response times table 5.4 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. the execution status symbols used in table 5.4 are explained in table 5.5. this lsi is capable of fast wo rd transfer to on-chip memory, has the program area in on-chip rom and the stack area in on-chip ram, enabling high-speed processing. table 5.4 interrupt response times normal mode * 5 advanced mode no. execution status interrupt control mode 0 interrupt control mode 2 interrupt control mode 0 interrupt control mode 2 1 interrupt priority determination * 1 3 3 3 3 2 number of wait states until executing instruction ends * 2 1 to 19 + 2 s i 1 to 19 + 2 s i 1 to 19 + 2 s i 1 to 19 + 2 s i 3 pc, ccr, exr stack save 2 s k 3 s k 2 s k 3 s k 4 vector fetch s i s i 2 s i 2 s i 5 instruction fetch * 3 2 s i 2 s i 2 s i 2 s i 6 internal processing * 4 2 2 2 2 total (using on-chip memory) 11 to 31 12 to 32 12 to 32 13 to 33 notes: 1. two states in case of internal interrupt. 2. refers to mulxs and divxs instructions. 3. prefetch after interrupt acceptance and interrupt handling routine prefetch. 4. internal processing after interrupt acceptance and internal processing after vector fetch. 5. not available in this lsi. section 5 interrupt controller rev. 7.00 sep. 11, 2009 page 86 of 566 rej09b0211-0700 table 5.5 number of states in interru pt handling routine execution status object of access external device * 8 bit bus 16 bit bus symbol internal memory 2-state access 3-state access 2-state access 3-state access instruction fetch s i 1 4 6 + 2m 2 3 + m branch address read s j stack manipulation s k legend: m: number of wait states in an external device access. note: * cannot be used in this lsi. 5.6.5 dtc activation by interrupt the dtc can be activated by an in terrupt. for details, see section 8, data transfer controller (dtc). note: no dtc is implemented in the h8s/2614 and h8s/2616. 5.7 usage notes 5.7.1 contention between interru pt generation and disabling when an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective after execution of the instruction. when an interrupt enable bit is cleared to 0 by an instruction su ch as bclr or mov, and if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction. however, if there is an interrupt request of higher priority than that interrupt, interrupt exception handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be ignored. the same also applies when an inte rrupt source flag is cleared to 0. figure 5.6 shows an example in which the tgiea bit in the tpu's tier_0 register is cleared to 0. the above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked. section 5 interrupt controller rev. 7.00 sep. 11, 2009 page 87 of 566 rej09b0211-0700 internal address bus internal write si g nal tciev tcfv tciv interrupt si g nal tier_0 write cycle by cpu tcivexception handlin g tier_0 address figure 5.6 contention between in terrupt generation and disabling 5.7.2 instructions that disable interrupts the instructions that disable interrupts are ldc, andc, orc, and xorc. after any of these instructions are executed, all interrupts including nmi are disabled and the next instruction is always executed. when the i bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.7.3 when interrupts are disabled there are times when interr upt acceptance is disabled by the interrupt controller. the interrupt controller disables interrupt accep tance for a 3-state period after the cpu has updated the mask level with an ldc, andc, orc, or xorc instruction. section 5 interrupt controller rev. 7.00 sep. 11, 2009 page 88 of 566 rej09b0211-0700 5.7.4 interrupts during execution of eepmov instruction interrupt operation differs between the eepmov.b instruction and the eepmov.w instruction. with the eepmov.b instruction, an interrupt request (including nmi) issued during the transfer is not accepted until the move is completed. with the eepmov.w instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle. the pc value saved on the stack in this case is the address of the next instruction. therefore, if an interrupt is generated during execution of an eepmov.w instruction, the following coding should be used. l1: eepmov.w mov.w r4,r4 bne l1 section 6 pc break controller (pbc) rev. 7.00 sep. 11, 2009 page 89 of 566 rej09b0211-0700 section 6 pc break controller (pbc) the pc break controller (pbc) provides functions that simplify program debugging. using these functions, it is easy to create a self-monitoring debugger, enabling programs to be debugged with the chip alone, without using an in-circuit emulator. a block diagram of the pc break controller is shown in figure 6.1. note: no pbc is implemented in the h8s/2614 and h8s/2616. 6.1 features ? two break channels (a and b) ? 24-bit break address ? bit masking possible ? four types of break compare conditions ? instruction fetch ? data read ? data write ? data read/write ? bus master ? either cpu or cpu/dtc can be selected ? the timing of pc break exception handling after the occurrence of a break condition is as follows: ? immediately before execution of the instruction fetched at the set address (instruction fetch) ? immediately after execution of the instruction that accesses data at the set address (data access) ? module stop mode can be set section 6 pc break controller (pbc) rev. 7.00 sep. 11, 2009 page 90 of 566 rej09b0211-0700 output control output control mask control pc break interrupt match si g nal match si g nal mask control bara bcra barb bcrb comparator control lo g ic comparator control lo g ic internal address access status figure 6.1 block diagram of pc break controller 6.2 register descriptions the pc break controller has the following registers. for details on register addresses and register states during each process, refer to appendix a, on-chip i/o register. ? break address register a (bara) ? break address register b (barb) ? break control register a (bcra) ? break control register b (bcrb) 6.2.1 break address register a (bara) bara is a 32-bit readable/writable register that specifies the channel a break address. bit bit name initial value r/w description 31 to 24 ? undefined ? reserved these bits are read as an undefined value and cannot be modified. 23 to 0 baa23 to baa0 h'000000 r/w these bits set the channel a pc break address. section 6 pc break controller (pbc) rev. 7.00 sep. 11, 2009 page 91 of 566 rej09b0211-0700 6.2.2 break address register b (barb) barb is the channel b break address register. the bit configuration is the same as for bara. 6.2.3 break control register a (bcra) bcra controls channel a pc breaks. bcra also contains a condition match flag. bit bit name initial value r/w description 7 cmfa 0 r/w condition match flag a [setting condition] ? when a condition set for channel a is satisfied [clearing condition] ? when 0 is written to cmfa after reading cmfa = 1 6 cda 0 r/w cpu cycle/dtc cycle select a selects the channel a break condition bus master. 0: cpu 1: cpu or dtc 5 4 3 bamra2 bamra1 bamra0 0 0 0 r/w r/w r/w break address mask register a2 to a0 these bits specify which bits of the break address set in bara are to be masked. 000: baa23 to 0 (all bits are unmasked) 001: baa23 to 1 (lowest bit is masked) 010: baa23 to 2 (lower 2 bits are masked) 011: baa23 to 3 (lower 3 bits are masked) 100: baa23 to 4 (lower 4 bits are masked) 101: baa23 to 8 (lower 8 bits are masked) 110: baa23 to 12 (lower 12 bits are masked) 111: baa23 to 16 (lower 16 bits are masked) 2 1 csela1 csela0 0 0 r/w r/w break condition select a selects break condition of channel a. 00: instruction fetch is used as break condition 01: data read cycle is used as break condition 10: data write cycle is used as break condition 11: data read/write cycle is used as break condition 0 biea 0 r/w break interrupt enable a when this bit is 1, the pc break interrupt request of channel a is enabled. section 6 pc break controller (pbc) rev. 7.00 sep. 11, 2009 page 92 of 566 rej09b0211-0700 6.2.4 break control register b (bcrb) bcrb is the channel b break control register. the bit configuration is the same as for bcra. 6.3 operation the operation flow from break condition setting to pc break interrupt exception handling is shown in section 6.3.1, pc break interrupt due to instruction fetch, and 6.3.2, pc break interrupt due to data access, taking the example of channel a. 6.3.1 pc break interrupt due to instruction fetch 1. set the break address in bara. for a pc break caused by an instruction fetch, set the address of the first instruction byte as the break address. 2. set the break conditions in bcr. set bit 6 (cda) to 0 to select the cpu because the bus master mu st be the cpu for a pc break caused by an instruction fetch. set the address bits to be masked to bits 3 to 5 (bama2 to bama0). set bits 1 and 2 (csela1 and csela0) to 00 to specify an instruction fetch as the break condition. set bit 0 (biea) to 1 to enable break interrupts. 3. when the instruction at the set address is fetc hed, a pc break request is generated immediately before execution of the fetched instruction, and the condition match flag (cmfa) is set. 4. after priority determination by the interrupt controller, pc break interrupt exception handling is started. 6.3.2 pc break interrupt due to data access 1. set the break address in bara. for a pc break caused by a data access, set the ta rget rom, ram, i/o, or external address space address as the break address. stack operati ons and branch address reads are included in data accesses. 2. set the break conditions in bcra. select the bus master with bit 6 (cda). set the address bits to be masked to bits 3 to 5 (bama2 to bama0). set bits 1 and 2 (csela1 and csela0) to 01, 10, or 11 to specify data access as the break condition. set bit 0 (biea) to 1 to enable break interrupts. 3. after execution of the instruction that perfor ms a data access on the set address, a pc break request is generated and the condition match flag (cmfa) is set. 4. after priority determination by the interrupt controller, pc break interrupt exception handling is started. section 6 pc break controller (pbc) rev. 7.00 sep. 11, 2009 page 93 of 566 rej09b0211-0700 6.3.3 notes on pc break interrupt handling ? when a pc break interrupt is generated at the transfer address of an eepmov.b instruction pc break exception handling is ex ecuted after all data transfers have been completed and the eepmov.b instruction has ended. ? when a pc break interrupt is gene rated at a dtc transfer address pc break exception handling is executed after the dtc has completed the specified number of data transfers, or after data for which the disel bit is set to 1 has been transferred. 6.3.4 operation in transitions to power-down modes the operation when a pc break interrupt is set for an instruction fetch at the address after a sleep instruction is shown below. ? when the sleep instruction ca uses a transition fr om high-speed (medium-speed) mode to sleep mode: after execution of the sleep instru ction, a transition is not made to sleep mode, and pc break interrupt handling is executed. after execution of pc break interrupt handling, the instruction at the address after the sleep instru ction is executed (figure 6.2 (a)). ? when the sleep instruction causes a transition to software standby mode: after execution of the sleep inst ruction, a transition is made to the respective mode, and pc break interrupt handling is not executed. however, the cmfa or cmfb flag is set (figure 6.2 (b)). sleep instruction execution sleep instruction execution transition to respective mode pc break exception handlin g execution of instruction after sleep instruction (a) (b) figure 6.2 operation in power-down mode transitions section 6 pc break controller (pbc) rev. 7.00 sep. 11, 2009 page 94 of 566 rej09b0211-0700 6.3.5 when instruction executi on is delayed by one state while the break interrupt enable bit is set to 1, instruction execution is one state later than usual. ? for 1-word branch instructions (bcc d:8, bsr, jsr, jmp, trapa, rte, and rts) in on-chip rom or ram. ? when break interruption by instruction fetch is set, the set address indicates on-chip rom or ram space, and that address is used for data access, the instruction th at executes the data access is one state later than in normal operation. ? when break interruption by instruction fetch is set and a break interrupt is generated, if the executing instruction immediately preceding the set instruction has one of the addressing modes shown below, and that address indicates on-chip rom or ram, the instruction will be one state later than in normal operation. addressing modes: @ern, @(d:16,ern), @(d:32,ern), @-ern/ern+, @aa:8, @aa:24, @aa:32, @(d:8,pc), @(d:16,pc), @@aa:8 ? when break interruption by instruction fetch is set and a break interrupt is generated, if the executing instruction immediately preceding the set instruction is nop or sleep, or has #xx,rn as its addressing mode, and that instruction is located in on-chip rom or ram, the instruction will be one state later than in normal operation. section 6 pc break controller (pbc) rev. 7.00 sep. 11, 2009 page 95 of 566 rej09b0211-0700 6.4 usage notes 6.4.1 module stop mode setting pbc operation can be disabled or enabled usi ng the module stop control register. the initial setting is for pbc operation to be halted. regi ster access is enabled by clearing module stop mode. for details, refer to section 20, power-down modes. 6.4.2 pc break interrupts the pc break interrupt is shared by channels a and b. the channel from which the request was issued must be determined by the interrupt handler. 6.4.3 cmfa and cmfb the cmfa and cmfb flags are not automatically cleared to 0, so 0 must be written to cmfa or cmfb after first reading the flag while it is set to 1. if the flag is left set to 1, another interrupt will be requested after interrupt handling ends. 6.4.4 pc break interrupt when dtc is bus master a pc break interrupt generated wh en the dtc is the bus master is accepted after the bus has been transferred to the cpu by the bus controller. 6.4.5 pc break set for instruction fetch at address following bsr, jsr, jmp, trapa, rte, or rts instruction when a pc break is set for an in struction fetch at an address following a bsr, jsr, jmp, trapa, rte, or rts instruction: even if the instruction at the address follo wing a bsr, jsr, jmp, trapa, rte, or rts instruction is fetched, it is not executed, and so a pc break interrupt is not generated by the instruction fetch at the next address. 6.4.6 i bit set by ldc, andc, orc, or xorc instruction when the i bit is set by an ldc, andc, orc, or xorc instruction, a pc break interrupt becomes valid two states after the end of the executing instruction. if a pc break interrupt is set for the instruction following one of these instructions, since interrupts, including nmi, are disabled for a 3-state period in the case of ld c, andc, orc, and xor, the next instruction is always executed. for details, see section 5, interrupt controller. section 6 pc break controller (pbc) rev. 7.00 sep. 11, 2009 page 96 of 566 rej09b0211-0700 6.4.7 pc break set for instruction fetc h at address following bcc instruction when a pc break is set for an instruction fetch at an address following a bcc instruction: a pc break interrupt is generate d if the instruction at the next address is executed in accordance with the branch condition, and is not generated if the instruction at the next address is not executed. 6.4.8 pc break set for instruction fetch at branch destination address of bcc instruction when a pc break is set for an instruction fetch at the branch destination address of a bcc instruction: a pc break interrupt is generated if the instruction at the branch destination is executed in accordance with the branch condition, and is not generated if the instruction at the branch destination is not executed. section 7 bus controller rev. 7.00 sep. 11, 2009 page 97 of 566 rej09b0211-0700 section 7 bus controller the h8s/2600 cpu is driven by a system clock, denoted by the symbol ?. the bus controller controls a memory cycle and a bus cycle. different methods are used to access on-chip memory and on-chip support modules. the bus controller also has a bus arbitration function, and controls the operation of the internal bus masters: the cpu and data transfer controller (dtc). note: the dtc, mmt, and poe are not supported in h8s/2614 and h8s/2616. 7.1 basic timing the period from one rising edge of ? to the next is referred to as a "state". the memory cycle or bus cycle consists of one, two, three, or four states. different methods are used to access on-chip memory, on-chip support modules, and the external address space. 7.1.1 on-chip memory access timing (rom, ram) on-chip memory is accessed in one state. the data bus is 16 bits wide, permitting both byte and word transfer instruction. figure 7.1 shows the on-chip memory access cycle. t 1 internal address bus bus cycle address read data write data internal read si g nal internal data bus internal write si g nal internal data bus read access write access figure 7.1 on-chip memory access cycle section 7 bus controller rev. 7.00 sep. 11, 2009 page 98 of 566 rej09b0211-0700 7.1.2 on-chip support module access timing the on-chip support modules, except for hcan, mmt, and poe, are accessed in two states. the data bus is either 8 bits or 16 bits wide, depending on the particular internal i/o register being accessed. for details, refer to appendix a, on-c hip i/o register. figur e 7.2 shows access timing for the on-chip supporting modules. t 1 t 2 internal address bus bus cycle address read data write data internal read si g nal internal data bus internal write si g nal internal data bus read access write access figure 7.2 on-chip support module access cycle section 7 bus controller rev. 7.00 sep. 11, 2009 page 99 of 566 rej09b0211-0700 7.1.3 on-chip hcan module access timing on-chip hcan module access is performed in four states. the data bus width is 16 bits. wait states can be inserted by means of a wait re quest from the hcan. on-chip hcan module access timing is shown in figures 7.3. t 1 t 3 t 2 t w t w t 4 internal address bus bus cycle address read data write data hcan read si g nal internal data bus hcan write si g nal internal data bus read write figure 7.3 on-chip hcan module a ccess cycle (wait states inserted) section 7 bus controller rev. 7.00 sep. 11, 2009 page 100 of 566 rej09b0211-0700 7.1.4 on-chip mmt module access timing on-chip mmt module and poe access are performed in three states. the data width is 16 bits. on-chip mmt module access timings are shown in figure 7.4. t 1 t 2 t 3 internal address bus bus cycle address read data write data mmt read si g nal internal data bus mmt write si g nal internal data bus read write figure 7.4 on-chip mmt module access cycle section 7 bus controller rev. 7.00 sep. 11, 2009 page 101 of 566 rej09b0211-0700 7.2 bus arbitration the bus controller has a bus arbiter th at arbitrates bus master operations. there are two bus masters, the cpu and dtc, which perform read/write operations when they control the bus. note: no dtc is implemented in the h8s/2614 and h8s/2616. 7.2.1 order of priority of the bus masters each bus master requests the bus by means of a bus request signal. the bus arbiter detects the bus masters? bus request signals, and if the bus is requested, sends a bus request acknowledge signal to the bus master making the request. if there are bus requests from more than one bus master, the bus request acknowledge signal is sent to the one with the highest priority. when a bus master receives the bus request acknowledge signal, it takes possession of the bus until that signal is canceled. the order of priority of the bus masters is as follows: (high) dtc > cpu (low) 7.2.2 bus transfer timing even if a bus request is received from a bus mast er with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately. the cpu is the lowest-priority bus ma ster, and if a bus request is received from the dtc, the bus arbiter transfers the bus to the bus master that issued the request. the timing for transfer of the bus is as follows: ? the bus is transferred at a break between bus cy cles. however, if a bus cycle is executed in discrete operations, as in the case of a longwor d-size access, the bus is not transferred between such operations. for details, refer to section 2.7, bus states during instruction execution, in the h8s/2600 series, h8s/2000 series software manual. ? if the cpu is in sleep mode, it transfers the bus immediately. the dtc can release the bus after a vector read, a re gister information read (3 states), a single data transfer, or a register information write (3 states ). it does not release the bus during a register information read (3 states), a si ngle data transfer, or a register information write (3 states). section 7 bus controller rev. 7.00 sep. 11, 2009 page 102 of 566 rej09b0211-0700 section 8 data transfer controller (dtc) rev. 7.00 sep. 11, 2009 page 103 of 566 rej09b0211-0700 section 8 data transfer controller (dtc) this lsi includes a data transfer controller (dtc ). the dtc can be activated by an interrupt or software, to transfer data. figure 8.1 shows a block diagram of the dtc. the dtc?s register information is stored in th e on-chip ram. when the dtc is used, the rame bit in syscr must be set to 1. a 32-bit bus connects the dtc to the on-chip ram (1 kbyte), enabling 32-bit/1-state reading and writing of the dtc register information. note: no dtc is implemented in the h8s/2614 and h8s/2616. 8.1 features ? transfer is possible over any number of channels ? three transfer modes ? normal, repeat, and block transfer modes are available ? one activation source can trigger a number of data transfers (chain transfer) ? the direct specification of 16 -mbyte address space is possible ? activation by software is possible ? transfer can be set in byte or word units ? a cpu interrupt can be requested for the interrupt that activated the dtc ? module stop mode can be set section 8 data transfer controller (dtc) rev. 7.00 sep. 11, 2009 page 104 of 566 rej09b0211-0700 internal address bus dtcer a to dtcer g dtvecr interrupt controller interrupt request dtc on-chip ram internal data bus cpu interrupt request mra mrb cra crb dar sar mra, mrb: cra, crb: sar: dar: dtcera to dtcerg: dtvecr: dtc mode re g isters a and b dtc transfer count re g isters a and b dtc source address re g ister dtc destination address re g ister dtc enable re g isters a to g dtc vector re g ister le g end: dtc service request control lo g ic re g ister information figure 8.1 block diagram of dtc section 8 data transfer controller (dtc) rev. 7.00 sep. 11, 2009 page 105 of 566 rej09b0211-0700 8.2 register configuration the dtc has the following registers. ? dtc mode register a (mra) ? dtc mode register b (mrb) ? dtc source address register (sar) ? dtc destination address register (dar) ? dtc transfer count register a (cra) ? dtc transfer count register b (crb) these six registers cannot be directly accessed from the cpu. when activated, the dtc reads a set of register information that is stored in on-chip ram to the corresponding dtc registers and transfers data. after the data transfer, it writes a set of updated register information back to the ram. ? dtc enable registers (dtcer) ? dtc vector register (dtvecr) for details on register addresses and register states during each process, refer to appendix a, on- chip i/o register. section 8 data transfer controller (dtc) rev. 7.00 sep. 11, 2009 page 106 of 566 rej09b0211-0700 8.2.1 dtc mode register a (mra) mra is an 8-bit register that selects the dtc operating mode. bit bit name initial value r/w description 7 6 sm1 sm0 undefined undefined ? ? source address mode 1 and 0 these bits specify an sar operation after a data transfer. 0x: sar is fixed 10: sar is incremented after a transfer (by +1 when sz = 0; by +2 when sz = 1) 11: sar is decremented after a transfer (by ?1 when sz = 0; by ?2 when sz = 1) 5 4 dm1 dm0 undefined undefined ? ? destination address mode 1 and 0 these bits specify a dar operation after a data transfer. 0x: dar is fixed 10: dar is incremented after a transfer (by +1 when sz = 0; by +2 when sz = 1) 11: dar is decremented after a transfer (by ?1 when sz = 0; by ?2 when sz = 1) 3 2 md1 md0 undefined undefined ? ? dtc mode these bits specify the dtc transfer mode. 00: normal mode 01: repeat mode 10: block transfer mode 11: setting prohibited 1 dts undefined ? dtc transfer mode select specifies whether the source side or the destination side is set to be a repeat area or block area, in repeat mode or block transfer mode. 0: destination side is repeat area or block area 1: source side is repeat area or block area 0 sz undefined ? dtc data transfer size specifies the size of data to be transferred. 0: byte-size transfer 1: word-size transfer legend: x: don?t care section 8 data transfer controller (dtc) rev. 7.00 sep. 11, 2009 page 107 of 566 rej09b0211-0700 8.2.2 dtc mode register b (mrb) mrb is an 8-bit register that selects the dtc operating mode. bit bit name initial value r/w description 7 chne undefined ? dtc chain transfer enable when this bit is set to 1, a chain transfer will be performed. for details, refer to section 8.5.4, chain transfer. in data transfer with chne set to 1, determination of the end of the specified number of transfers, clearing of the interrupt source flag, and clearing of dtcer, are not performed. 6 disel undefined ? dtc interrupt select when this bit is set to 1, a cpu interrupt request is generated every time after the end of a data transfer. when this bit is set to 0, a cpu interrupt request is generated at the time when the specified number of data transfer ends. 5 to 0 ? undefined ? reserved these bits have no effect on dtc operation. only 0 should be written to these bits. 8.2.3 dtc source address register (sar) sar is a 24-bit register that designates the source address of data to be transferred by the dtc. for word-size transfer, specify an even source address. 8.2.4 dtc destination address register (dar) dar is a 24-bit register that designates the destination address of data to be transferred by the dtc. for word-size transfer, specify an even destination address. 8.2.5 dtc transfer count register a (cra) cra is a 16-bit register that designates the number of times data is to be transferred by the dtc. in normal mode, the entire cra functions as a 16-bit transfer counter (1 to 65,536). it is decremented by 1 every time data is transferred, and transfer ends when the count reaches h'0000. in repeat mode or block transfer mode, the cra is divided into two parts; the upper 8 bits (crah) and the lower 8 bits (cral). crah holds the number of transfers while cral section 8 data transfer controller (dtc) rev. 7.00 sep. 11, 2009 page 108 of 566 rej09b0211-0700 functions as an 8-bit transfer counter (1 to 256). cral is decremented by 1 every time data is transferred, and the contents of crah are sent when the count reaches h'00. 8.2.6 dtc transfer count register b (crb) crb is a 16-bit register that designates the number of times data is to be transferred by the dtc in block transfer mode. it functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1 every time data is transferred, and transf er ends when the count reaches h'0000. 8.2.7 dtc enable registers (dtcer) dtcer is comprised of seven registers; dtcera to dtcerg, and is a register that specifies dtc activation interrupt sources. the correspondence between interrupt sources and dtce bits is shown in table 8.1. for dtce bit setting, use bit manipulation instructions such as bset and bclr for reading and writing. if all interrupts are masked, multiple activation sources can be set at one time (only at the initial setting) by writing data after executing a dummy read on the relevant register. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 dtce7 dtce6 dtce5 dtce4 dtce3 dtce2 dtce1 dtce0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w dtc activation enable setting this bit to 1 specifies a relevant interrupt source as a dtc activation source. [clearing conditions] ? when the disel bit is 1 and the data transfer has ended ? when the specified number of transfers have ended these bits are not cleared when the disel bit is 0 and the specified number of transfers have not been completed section 8 data transfer controller (dtc) rev. 7.00 sep. 11, 2009 page 109 of 566 rej09b0211-0700 8.2.8 dtc vector register (dtvecr) dtvecr is an 8-bit readable/writable register that enables or disables dtc activation by software, and sets a vector number for the software activation interrupt. bit bit name initial value r/w description 7 swdte 0 r/w dtc software activation enable setting this bit to 1 activates dtc. only 1 can be written to this bit. [clearing conditions] ? when the disel bit is 0 and the specified number of transfers have not ended ? when 0 s written to the disel bit after a software-activated data transfer end interrupt (swdtend) request has been sent to the cpu. when the disel bit is 1 and data transfer has ended or when the specified number of transfers have ended, this bit will not be cleared. 6 5 4 3 2 1 0 dtvec6 dtvec5 dtvec4 dtvec3 dtvec2 dtvec1 dtvec0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w dtc software activation vectors 0 to 6 these bits specify a vector number for dtc software activation. the vector address is expressed as h'0400 + (vector number 2). for example, when dtvec6 to dtvec0 = h'10, the vector address is h'0420. when the bit swdte is 0, these bits can be written. 8.3 activation sources the dtc operates when activated by an interrupt or by a write to dtvecr by software. an interrupt request can be directed to the cpu or dtc, as designated by the corresponding dtcer bit. at the end of a data transfer (or the last c onsecutive transfer in the cas e of chain transfer), the activation source or corresponding dtcer bit is cl eared. the activation source flag, in the case of rxi_0, for example, is the rdrf flag of sci_0. when an interrupt has been designated a dtc activation source, the existing cpu mask level and interrupt controller priorities have no effect. if there is more than one activation source at the same time, the dtc operates in accordance with the default priorities. figure 8.2 shows a block diagram of activation source control. for details, see section 5, interrupt controller. section 8 data transfer controller (dtc) rev. 7.00 sep. 11, 2009 page 110 of 566 rej09b0211-0700 cpu dtc dtcer source fla g cleared on-chip supportin g module irq interrupt interrupt request clear clear controller clear request interrupt controller selection circuit interrupt mask select dtvecr figure 8.2 block diagram of dtc activation source control 8.4 location of register info rmation and dtc vector table locate the register informatio n in the on-chip ram (addresses: h'ffebc0 to h'ffefbf). register information should be located at an address that is a multiple of four within the range. locating the register information in address space is shown in figure 8.3. locate the mra, sar, mrb, dar, cra, and crb registers, in that order, from the start address of the register information. in the case of chain transfer, register information should be located in consecutive areas and the register information start address should be located at the vector address corresponding to the interrupt source. the dtc reads the start address of the register information from the vector address set for each activation source, and then r eads the register information from that start address. when the dtc is activated by software, th e vector address is obtained from: h'0400 + (dtvecr[6:0] 2). for example, if dtvecr is h'10, the vector address is h'0420. the configuration of the vector address is the same in both normal and advanced modes, a 2-byte unit being used in both cases. these two bytes specify th e lower bits of the register information start address. section 8 data transfer controller (dtc) rev. 7.00 sep. 11, 2009 page 111 of 566 rej09b0211-0700 mra 0123 sar mrb dar cra crb mra sar mrb dar cra crb lower address 4 bytes re g ister information re g ister information for 2nd transfer in chain transfer re g ister information start address chain transfer figure 8.3 correspondence between dtc v ector address and register information section 8 data transfer controller (dtc) rev. 7.00 sep. 11, 2009 page 112 of 566 rej09b0211-0700 table 8.1 interrupt sources, dtc vect or addresses, and corresponding dtces interrupt source origin of interrupt source vector number dtc vector address dtce * priority software write to dtvecr dtvecr h'0400 + (vector number 2) ? high external pin irq0 16 h'0420 dtcea7 irq1 17 h'0422 dtcea6 irq2 18 h'0424 dtcea5 irq3 19 h'0426 dtcea4 irq4 20 h'0428 dtcea3 irq5 21 h'042a dtcea2 reserved for 22 h'042c dtcea1 system use 23 h'042e dtcea0 a/d adi (a/d conversion end) 28 h'0438 dtceb6 tgia_0 32 h'0440 dtceb5 tpu channel 0 tgib_0 33 h'0442 dtceb4 tgic_0 34 h'0444 dtceb3 tgid_0 35 h'0446 dtceb2 tgia_1 40 h'0450 dtceb1 tpu channel 1 tgib_1 41 h'0452 dtceb0 tgia_2 44 h'0458 dtcec7 tpu channel 2 tgib_2 45 h'045a dtcec6 tgia_3 48 h'0460 dtcec5 tpu channel 3 tgib_3 49 h'0462 dtcec4 tgic_3 50 h'0464 dtcec3 tgid_3 51 h'0466 dtcec2 tgia_4 56 h'0470 dtcec1 tpu channel 4 tgib_4 57 h'0472 dtcec0 tgia_5 60 h'0478 dtced5 tpu channel 5 tgib_5 61 h'047a dtced4 low section 8 data transfer controller (dtc) rev. 7.00 sep. 11, 2009 page 113 of 566 rej09b0211-0700 interrupt source origin of interrupt source vector number dtc vector address dtce * priority ? 64 h'0480 dtced3 high reserved for system use 65 h'0482 dtced2 68 h'0488 dtced1 69 h'048a dtced0 72 h'0490 dtcee7 73 h'0492 dtcee6 74 h'0494 dtcee5 75 h'0496 dtcee4 rxi_0 81 h'04a2 dtcee3 sci channel 0 txi_0 82 h'04a4 dtcee2 rxi_1 85 h'04aa dtcee1 sci channel 1 txi_1 86 h'04ac dtcee0 rxi_2 89 h'04b2 dtcef7 sci channel 2 txi_2 90 h'04b4 dtcef6 hcan reserved for system use 104 h'04d0 dtceg7 rm0 105 h'04d2 dtceg6 106 h'04d4 dtceg5 reserved for system use 107 h'04d6 dtceg4 mmt tgimn 108 h'04d8 dtceg3 tginn 109 h'04da dtceg2 ? 110 h'04dc dtceg1 reserved for system use 111 h'04de dtceg0 low note: * dtce bits with no corresponding interrupt are reserved, and should be written with 0. section 8 data transfer controller (dtc) rev. 7.00 sep. 11, 2009 page 114 of 566 rej09b0211-0700 8.5 operation register information is stored in on-chip me mory. when activated, th e dtc reads register information in on-chip memory and transfers data. after the data transfer, the dtc writes updated register information back to the memory. the pre-storage of register information in memory makes it possible to transfer data over any required number of channels. the transfer mode can be specified as normal, repeat, and block transfer mode. setting the chne bit in mrb to 1 makes it possible to perform a number of transfers with a single activa tion source (chain transfer). the 24-bit sar designates the dtc transfer source address, and the 24-bit dar designates the transfer destination address. after each transfer, sar and dar are independently incremented, decremented, or left fixed depending on its register information. start end read dtc vector read re g ister information data transfer write re g ister information clear an activation fla g interrupt exception handlin g clear dtcer chne = 1 next transfer yes yes no transfer counter = 0 or disel = 1 no figure 8.4 flowchart of dtc operation section 8 data transfer controller (dtc) rev. 7.00 sep. 11, 2009 page 115 of 566 rej09b0211-0700 8.5.1 normal mode in normal mode, one operation transfers one byte or one word of data. table 8.2 lists the register information in normal mode. from 1 to 65,536 transfers can be specified. once the specified number of transfers have been completed, a cpu interrupt can be requested. table 8.2 register information in normal mode name abbreviation function dtc source address register sar designates source address dtc destination address register dar designates destination address dtc transfer count register a cra designates transfer count dtc transfer count register b crb not used sar dar transfer figure 8.5 memory mapping in normal mode section 8 data transfer controller (dtc) rev. 7.00 sep. 11, 2009 page 116 of 566 rej09b0211-0700 8.5.2 repeat mode in repeat mode, one operation transfers one byte or one word of data. table 8.3 lists the register information in repeat mode. from 1 to 256 transfers can be specified. once the specified number of transfers have ended, the initial state of the transfer counter and the address register specified as the repeat area is restored, and transfer is repeated. in repeat mode the transfer counter value does not reach h'00, and therefore cpu interrupts cannot be requested when disel = 0. table 8.3 register information in repeat mode name abbreviation function dtc source address register sar designates source address dtc destination address register dar designates destination address dtc transfer count register ah crah holds number of transfers dtc transfer count register al cral designates transfer count dtc transfer count register b crb not used sar or dar dar or sar repeat area transfer figure 8.6 memory mapping in repeat mode section 8 data transfer controller (dtc) rev. 7.00 sep. 11, 2009 page 117 of 566 rej09b0211-0700 8.5.3 block transfer mode in block transfer mode, one operation transfers one block of data. either the transfer source or the transfer destination is designated as a block area. table 8.4 lists the register information in block transfer mode. the block size can be between 1 and 256. when the transfer of one block ends, the initial state of the block size counter and the address register speci fied as the block area is restored. the other address register is then incremente d, decremented, or left fixed. from 1 to 65,536 transfers can be specified. once the specified number of transfers have been completed, a cpu interrupt is requested. table 8.4 register information in block transfer mode name abbreviation function dtc source address register sar designates source address dtc destination address register dar designates destination address dtc transfer count register ah crah holds block size dtc transfer count register al cral designates block size count dtc transfer count register b crb transfer count section 8 data transfer controller (dtc) rev. 7.00 sep. 11, 2009 page 118 of 566 rej09b0211-0700 first block transfer block area nth block dar or sar sar or dar figure 8.7 memory mapping in block transfer mode section 8 data transfer controller (dtc) rev. 7.00 sep. 11, 2009 page 119 of 566 rej09b0211-0700 8.5.4 chain transfer setting the chne bit in mrb to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. sar, dar, cra, crb, mra, and mrb, which define data transfers, can be set independently. figure 8.8 shows the memory map for chain transfer. when activated, the dtc r eads the register information start addr ess stored at the vector address, and then reads the first register in formation at that start address. after the data transfer, the chne bit will be tested. when it has been set to 1, dtc reads the next register information located in a consecutive area and performs the data transfer. these sequences are repeated until the chne bit is cleared to 0. in the case of transfer with chne set to 1, an interrupt request to the cpu is not generated at the end of the specified number of transfers or by setting of the disel bit to 1, and the interrupt source flag for the activation source is not affected. dtc vector address re g ister information chne = 1 re g ister information chne = 0 re g ister information start address source destination source destination figure 8.8 chain transfer operation section 8 data transfer controller (dtc) rev. 7.00 sep. 11, 2009 page 120 of 566 rej09b0211-0700 8.5.5 interrupts an interrupt request is issued to the cpu when the dtc has completed the specified number of data transfers, or a data transfer for which the disel bit was set to 1. in the case of interrupt activation, the interrupt set as the activation sour ce is generated. these interrupts to the cpu are subject to cpu mask level and interrupt controller priority level control. in the case of software activation, a software-ac tivated data transfer end interrupt (swdtend) is generated. when the disel bit is 1 and one data transfer has been completed, or the specified number of transfers have been completed, after data transfer ends the swdte bit is held at 1 and an swdtend interrupt is generated. the interrupt handling routine will then clear the swdte bit to 0. when the dtc is activated by software, an swdtend interrupt is not generated during a data transfer wait or during data transfer even if the swdte bit is set to 1. 8.5.6 operation timing dtc activation request dtc request address vector read read write data transfer transfer information write transfer information read figure 8.9 dtc operation timing (example in normal mode or repeat mode) section 8 data transfer controller (dtc) rev. 7.00 sep. 11, 2009 page 121 of 566 rej09b0211-0700 dtc activation request dtc request address vector read read write read write data transfer transfer information write transfer information read figure 8.10 dtc operation timing (example of block transfer mode, with block size of 2) dtc activation request dtc request address vector read read write read write data transfer data transfer transfer information write transfer information write transfer information read transfer information read figure 8.11 dtc operation timing (example of chain transfer) 8.5.7 number of dtc execution states table 8.5 lists execution status for a single dtc data transfer, and table 8.6 shows the number of states required for eac h execution status. section 8 data transfer controller (dtc) rev. 7.00 sep. 11, 2009 page 122 of 566 rej09b0211-0700 table 8.5 dtc execution status mode vector read i register information read/write j data read k data write l internal operations m normal 1 6 1 1 3 repeat 1 6 1 1 3 block transfer 1 6 n n 3 legend: n: block size (initial setting of crah and cral) table 8.6 number of states requi red for each execution status object to be accessed on- chip ram on- chip rom on-chip i/o registers external devices * bus width 32 16 8 16 8 16 access states 1 1 2 2 2 3 2 3 vector read s i ? 1 ? ? 4 6 + 2m 2 3 + m register information read/write s j 1 ? ? ? ? ? ? ? byte data read s k 1 1 2 2 2 3 + m 2 3 + m word data read s k 1 1 4 2 4 6 + 2m 2 3 + m byte data write s l 1 1 2 2 2 3 + m 2 3 + m word data write s l 1 1 4 2 4 6 + 2m 2 3 + m execution status internal operation s m 1 note: * cannot be used in this lsi. the number of execution states is calculated from using the formula below. note that is the sum of all transfers activated by one activation event (the number in which the chne bit is set to 1, plus 1). number of execution states = i s i + (j s j + k s k + l s l ) + m s m for example, when the dtc vector address table is located in the on-chip rom, normal mode is set, and data is transferred from on-chip rom to an internal i/o register, then the time required for the dtc operation is 13 states. the time from activation to the end of the data write is 10 states. section 8 data transfer controller (dtc) rev. 7.00 sep. 11, 2009 page 123 of 566 rej09b0211-0700 8.6 procedures for using dtc 8.6.1 activation by interrupt the procedure for using the dtc with interrupt activation is as follows: 1. set the mra, mrb, sar, dar, cra, and crb register information in on-chip ram. 2. set the start address of the register information in the dtc vector address. 3. set the corresponding bit in dtcer to 1. 4. set the enable bits for the interrupt sources to be used as the activation sources to 1. the dtc is activated when an interrupt used as an activation source is generated. 5. after one data transfer has been completed, or after the specified number of data transfers have been completed, the dtce bit is cleared to 0 and a cpu interrupt is requested. if the dtc is to continue transferring data, set the dtce bit to 1. 8.6.2 activation by software the procedure for using the dtc with software activation is as follows: 1. set the mra, mrb, sar, dar, cra, and crb register information in on-chip ram. 2. set the start address of the register information in the dtc vector address. 3. check that the swdte bit is 0. 4. write 1 to swdte bit and the vector number to dtvecr. 5. check the vector number written to dtvecr. 6. after one data transfer has been completed, if the disel bit is 0 and a cpu interrupt is not requested, the swdte bit is cleared to 0. if the dtc is to continue transferring data, set the swdte bit to 1. when the disel bit is 1, or after the specified number of data transfers have been completed, the swdte bit is held at 1 and a cpu interrupt is requested. 8.7 examples of use of the dtc 8.7.1 normal mode an example is shown in which the dtc is used to receive 128 bytes of data via the sci. 1. set mra to a fixed source address (sm1 = sm0 = 0), incrementing destination address (dm1 = 1, dm0 = 0), normal mode (md1 = md0 = 0), and byte size (sz = 0). the dts bit can have any value. set mrb for one data transfer by one interrupt (chne = 0, disel = 0). set the sci rdr address in sar, the star t address of the ram area where the data will be received in dar, and 128 (h'0080) in cra. crb can be set to any value. section 8 data transfer controller (dtc) rev. 7.00 sep. 11, 2009 page 124 of 566 rej09b0211-0700 2. set the start address of the register information at the dtc vector address. 3. set the corresponding bit in dtcer to 1. 4. set the sci to the appropriate receive mode. set the rie bit in scr to 1 to enable th e reception complete (rxi) interrupt. since the generatio n of a receive error during the sci reception operation will disable subsequent reception, the cpu should be enabled to accept receive error interrupts. 5. each time the reception of one byte of data ha s been completed on the sci, the rdrf flag in ssr is set to 1, an rxi interrupt is generated, and the dtc is activated. the receive data is transferred from rdr to ram by the dtc. dar is incremented and cra is decremented. the rdrf flag is automa tically cleared to 0. 6. when cra becomes 0 after the 128 data transfers have been completed, the rdrf flag is held at 1, the dtce bit is cleared to 0, and an rxi interrupt request is sent to the cpu. the interrupt handling routine will perform wrap-up processing. 8.7.2 chain transfer an example of dtc chain transfer is shown in which pulse output is performed using the ppg. chain transfer can be used to perform pulse output data transfer and ppg output trigger cycle updating. repeat mode transfer to the ppg?s ndr is performed in the first half of the chain transfer, and normal mode transfer to the tpu?s tgr in the second half. this is because clearing of the activation source and interrupt generation at the end of the specified number of transfers are restricted to the second half of the chain transfer (transfer when chne = 0). 1. perform settings for transfer to the ppg?s ndr. set mra to incrementing source address (sm1 = 1, sm0 = 0), a fixed destination address (dm1 = dm0 = 0), repeat mode (md1 = 0, md0 = 1), and word size (sz = 1). set the source side as a repeat area (dts = 1). set mrb to chain mode (chne = 1, disel = 0). set the data table start address in sar, the ndrh address in dar, and the data table size in crah and cral. crb can be set to any value. 2. perform settings for transfer to the tpu?s tgr. set mra to incrementing source address (sm1 = 1, sm0 = 0), a fixed destination address (dm1 = dm0 = 0), normal mode (md1 = md0 = 0), and word size (sz = 1). set the data table start address in sar, the tgra address in dar, and the data table size in cra. crb can be set to any value. 3. locate the tpu transfer regi ster information consecutively af ter the ndr transfer register information. 4. set the start address of the ndr transfer register informatio n to the dtc vector address. 5. set the bit corresponding to tgia in dtcer to 1. 6. set tgra as an output compare register (output disabled) with tior, and enable the tgia interrupt with tier. section 8 data transfer controller (dtc) rev. 7.00 sep. 11, 2009 page 125 of 566 rej09b0211-0700 7. set the initial output value in podr, and the ne xt output value in ndr. set bits in ddr and nder for which output is to be performed to 1. using pcr, select the tpu compare match to be used as the output trigger. 8. set the cst bit in tstr to 1, and start the tcnt count operation. 9. each time a tgra compare matc h occurs, the next output value is transferred to ndr and the set value of the next output trigger period is transferred to tgra. the activation source tgfa flag is cleared. 10. when the specified number of transfers are co mpleted (the tpu transfer cra value is 0), the tgfa flag is held at 1, the dtce bit is cleared to 0, and a tgia interrupt request is sent to the cpu. termination processing should be performed in the interrupt handling routine. 8.7.3 software activation an example is shown in which the dtc is used to transfer a block of 128 bytes of data by means of software activation. the transfer source address is h'1000 and the destination address is h'2000. the vector number is h'60, so the vector address is h'04c0. 1. set mra to incrementing source address (sm1 = 1, sm0 = 0), incrementing destination address (dm1 = 1, dm0 = 0), block transfer mode (md1 = 1, md0 = 0), and byte size (sz = 0). the dts bit can have any value. set mrb for one block transfer by one interrupt (chne = 0). set the transfer source address (h'1000) in sar, the destination address (h'2000) in dar, and 128 (h'8080) in cra. set 1 (h'0001) in crb. 2. set the start address of the register information at the dtc vector address (h'04c0). 3. check that the swdte bit in dt vecr is 0. check that there is currently no tran sfer activated by software. 4. write 1 to the swdte bit and the vector number (h'60) to dtvecr. the write data is h'e0. 5. read dtvecr again and check that it is set to the vector number (h'60). if it is not, this indicates that the write failed. this is presumably because an interrupt occurred between steps 3 and 4 and led to a different software activation. to activate this transfer , go back to step 3. 6. if the write was successful, the dtc is activated and a block of 128 bytes of data is transferred. 7. after the transfer, an swdtend interrupt occurs. the interrupt handling routine should clear the swdte bit to 0 and perform other wrap-up processing. section 8 data transfer controller (dtc) rev. 7.00 sep. 11, 2009 page 126 of 566 rej09b0211-0700 8.8 usage notes 8.8.1 module stop mode setting dtc operation can be disabled or enabled usi ng the module stop control register. the initial setting is for dtc operation to be halted. regi ster access is enabled by clearing module stop mode. for details, refer to section 20, power-down modes. 8.8.2 on-chip ram the mra, mrb, sar, dar, cra, and crb regist ers are all located in on-chip ram. when the dtc is used, the rame bit in sy scr must not be cleared to 0. 8.8.3 dtce bit setting for dtce bit setting, use bit manipulation instructions such as bset and bclr. if all interrupts are masked, multiple activation sources can be set at one time (only at the initial setting) by writing data after executing a dummy read on the relevant register. section 9 i/o ports rev. 7.00 sep. 11, 2009 page 127 of 566 rej09b0211-0700 section 9 i/o ports table 9.1 summarizes the port func tions. the pins of each port also have other functions such as input/output or interrupt input pins of on-chip supporting modules. each i/o port includes a data direction register (ddr) that controls input/output, a data register (dr) that stores output data, and a port register (port) used to read the pin states. the input-only ports do not have a dr or ddr register. ports a to d have a built-in input pull-up mos fu nction and a mos input pu ll-up control register (pcr) to control the on/off state of mos input pull-up. ports a to c include an open-dra in control register (odr) that controls the on/off state of the output buffer pmos. all the i/o ports can drive a single ttl load and a 30 pf capacitive load. section 9 i/o ports rev. 7.00 sep. 11, 2009 page 128 of 566 rej09b0211-0700 table 9.1 port functions port description port and other functions name input/output and output type p17/po15/tiocb2/tclkd p16/po14/tioca2/ irq1 p15/po13/tiocb1/tclkc p14/po12/tioca1/ irq0 p13/po11/tiocd0/tclkb p12/po10/tiocc0/tclka p11/po9/tiocb0 port 1 general i/o port also functioning as tpu i/o pins, ppg output pins, and interrupt input pins note: the h8s/2614 and h8s/2616 have no ppg outputs. p10/po8/tioca0 p47/an7 p46/an6 p45/an5 p44/an4 p43/an3 p42/an2 p41/an1 port 4 general input port also functioning as a/d converter analog inputs p40/an0 p93/an11 p92/an10 p91/an9 port 9 general input port also functioning as a/d converter analog inputs p90/an8 pa3/sck2/ poe3 pa2/rxd2/ poe2 pa1/txd2/ poe1 port a general i/o port also functioning as sci_2 i/o pins, poe input pins note: the h8s/2614 and h8s/2616 have no poe input pins. pa0/ poe0 built-in mos input pull-up push-pull or open-drain output selectable section 9 i/o ports rev. 7.00 sep. 11, 2009 page 129 of 566 rej09b0211-0700 port description port and other functions name input/output and output type pb7/tiocb5/pwob pb6/tioca5/pwoa pb5/tiocb4/pvob pb4/tioca4/pvoa pb3/tiocd3/puob pb2/tiocc3/puoa pb1/tiocb3/pco port b general i/o port also functioning as tpu_5, tpu_4, and tpu_3 i/o pins, and mmt i/o pins note: the h8s/2614 and h8s/2616 have no mmt input and output pins. pb0/tioca3/ pci built-in mos input pull-up push-pull or open-drain output selectable pc7 pc6 pc5/sck1/ irq5 pc4/rxd1 pc3/txd1 pc2/sck0/ irq4 pc1/rxd0 port c general i/o port also functioning as sci_1 and sci_0 i/o pins, and interrupt input pins pc0/txd0 built-in mos input pull-up push-pull or open-drain output selectable pd7 pd6 pd5 pd4 pd3 pd2 pd1 port d general i/o port pd0 built-in mos input pull-up pf7/ pf6 pf5 port f general i/o port also functioning as interrupt input pins, an a/d converter start trigger input pin, and a system clock output pin ( ) pf4 pf3/ adtrg / irq3 pf2 pf1 pf0/ irq2 section 9 i/o ports rev. 7.00 sep. 11, 2009 page 130 of 566 rej09b0211-0700 9.1 port 1 port 1 is an 8-bit i/o port and has the following registers. for details on register addresses and register states during each process, refe r to appendix a, on-chip i/o register. ? port 1 data direction register (p1ddr) ? port 1 data register (p1dr) ? port 1 register (port1) 9.1.1 port 1 data di rection register (p1ddr) p1ddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 1. p1ddr cannot be read; if it is, an undefined value will be read. bit bit name initial value r/w description 7 p17ddr 0 w 6 p16ddr 0 w 5 p15ddr 0 w 4 p14ddr 0 w 3 p13ddr 0 w 2 p12ddr 0 w 1 p11ddr 0 w when a pin is specified as a general purpose i/o port, setting this bit to 1 makes the corresponding port 1 pin an output pin. clearing this bit to 0 makes the pin an input pin. 0 p10ddr 0 w section 9 i/o ports rev. 7.00 sep. 11, 2009 page 131 of 566 rej09b0211-0700 9.1.2 port 1 data register (p1dr) p1dr is an 8-bit readable/writable register that stores output data for port 1 pins. bit bit name initial value r/w description 7 p17dr 0 r/w 6 p16dr 0 r/w 5 p15dr 0 r/w 4 p14dr 0 r/w 3 p13dr 0 r/w 2 p12dr 0 r/w 1 p11dr 0 r/w output data for a pin is stored when the pin is specified as a general purpose i/o port. 0 p10dr 0 r/w 9.1.3 port 1 register (port1) port1 is an 8-bit read-only register that shows the pin states. port1 cannot be modified. bit bit name initial value r/w description 7 p17 undefined * r 6 p16 undefined * r 5 p15 undefined * r 4 p14 undefined * r 3 p13 undefined * r 2 p12 undefined * r 1 p11 undefined * r if a port 1 read is performed while p1ddr bits are set to 1, the p1dr values are read. if a port 1 read is performed while p1ddr bits are cleared to 0, the pin states are read. 0 p10 undefined * r note: * determined by the states of pins p17 to p10. section 9 i/o ports rev. 7.00 sep. 11, 2009 page 132 of 566 rej09b0211-0700 9.1.4 pin functions port 1 pins also function as tpu i/o pins, ppg output pins, and interrupt input pins. the correspondence between the register specification and the pin functions is shown below. note: the h8s/2614 and h8s/2616 have no ppg outputs. table 9.2 p17 pin function tpu channel 2 setting * output input or initial value p17ddr ? 0 1 1 nder15 ? ? 0 1 p17 input tiocb2 input pin function tiocb2 output tclkd input p17 output po15 output note: * for details on the tpu channel specification, refer to section 10, 16-bit timer pulse unit (tpu). table 9.3 p16 pin function tpu channel 2 setting * output input or initial value p16ddr ? 0 1 1 nder14 ? ? 0 1 p16 input tioca2 input pin function tioca2 output irq1 input p16 output po14 output note: * for details on the tpu channel specification, refer to section 10, 16-bit timer pulse unit (tpu). section 9 i/o ports rev. 7.00 sep. 11, 2009 page 133 of 566 rej09b0211-0700 table 9.4 p15 pin function tpu channel 1 setting * output input or initial value p15ddr ? 0 1 1 nder13 ? ? 0 1 p15 input tiocb1 input pin function tiocb1 output tclkc input p15 output po13 output note: * for details on the tpu channel specification, refer to section 10, 16-bit timer pulse unit (tpu). table 9.5 p14 pin function tpu channel 1 setting * output input or initial value p14ddr ? 0 1 1 nder12 ? ? 0 1 p14 input tioca1 input pin function tioca1 output irq0 input p14 output po12 output note: * for details on the tpu channel specification, refer to section 10, 16-bit timer pulse unit (tpu). table 9.6 p13 pin function tpu channel 0 setting * output input or initial value p13ddr ? 0 1 1 nder11 ? ? 0 1 p13 input tiocd0 input pin function tiocd0 output tclkb input p13 output po11 output note: * for details on the tpu channel specification, refer to section 10, 16-bit timer pulse unit (tpu). section 9 i/o ports rev. 7.00 sep. 11, 2009 page 134 of 566 rej09b0211-0700 table 9.7 p12 pin function tpu channel 0 setting * output input or initial value p12ddr ? 0 1 1 nder10 ? ? 0 1 p12 input tiocc0 input pin function tiocc0 output tclka input p12 output po10 output note: * for details on the tpu channel specification, refer to section 10, 16-bit timer pulse unit (tpu). table 9.8 p11 pin function tpu channel 0 setting * output input or initial value p11ddr ? 0 1 1 nder9 ? ? 0 1 p11 input pin function tiocb0 output tiocb0 input p11 output po9 output note: * for details on the tpu channel specification, refer to section 10, 16-bit timer pulse unit (tpu). table 9.9 p10 pin function tpu channel 0 setting * output input or initial value p10ddr ? 0 1 1 nder8 ? ? 0 1 p10 input pin function tioca0 output tioca0 input p10 output po8 output note: * for details on the tpu channel specification, refer to section 10, 16-bit timer pulse unit (tpu). section 9 i/o ports rev. 7.00 sep. 11, 2009 page 135 of 566 rej09b0211-0700 9.2 port 4 port 4 is an 8-bit input-only port. port 4 pins also function as a/d converter analog input pins. for details on register addresses, refer to appendix a, on-chip i/o register. ? port 4 register (port4) 9.2.1 port 4 register (port4) port4 is an 8-bit read-only register that shows port 4 pin states. port4 cannot be modified. bit bit name initial value r/w description 7 p47 undefined * r 6 p46 undefined * r 5 p45 undefined * r 4 p44 undefined * r 3 p43 undefined * r 2 p42 undefined * r 1 p41 undefined * r the pin states are always read when a port 4 read is performed. 0 p40 undefined * r note: * determined by the states of pins p47 to p40. section 9 i/o ports rev. 7.00 sep. 11, 2009 page 136 of 566 rej09b0211-0700 9.3 port 9 port 9 is a 4-bit input-only port. port 9 pins also function as a/d converter analog input pins. port 9 has the following registers. for details on register addresses, refer to appendix a, on-chip i/o register. ? port 9 register (port9) 9.3.1 port 9 register (port9) port9 is an 8-bit read-only register that shows port 9 pin states. port9 cannot be modified. bit bit name initial value r/w description 7 ? undefined r 6 ? undefined r 5 ? undefined r 4 ? undefined r 3 p93 undefined * r 2 p92 undefined * r 1 p91 undefined * r the pin states are always read when a port 9 read is performed. 0 p90 undefined * r note: * determined by the states of pins p93 to p90. section 9 i/o ports rev. 7.00 sep. 11, 2009 page 137 of 566 rej09b0211-0700 9.4 port a port a is a 4-bit i/o port that also has other functions. port a has the following registers. for details on register addresses and register states during each processing, refer to appendix a, on- chip i/o register. ? port a data direction register (paddr) ? port a data register (padr) ? port a register (porta) ? port a pull-up mos control register (papcr) ? port a open-drain control register (paodr) 9.4.1 port a data di rection register (paddr) paddr is an 8-bit write-only register, the individual bits of which specify whether the pins of port a are used for input or output. paddr cannot be read; if it is, an undefined value will be read. bit bit name initial value r/w description 7 ? undefined ? 6 ? undefined ? 5 ? undefined ? 4 ? undefined ? reserved 3 pa3ddr 0 w 2 pa2ddr 0 w 1 pa1ddr 0 w when a pin is specified as a general purpose i/o port, setting this bit to 1 makes the corresponding port a pin an output pin. clearing this bit to 0 makes the pin an input pin. 0 pa0ddr 0 w section 9 i/o ports rev. 7.00 sep. 11, 2009 page 138 of 566 rej09b0211-0700 9.4.2 port a data register (padr) padr is an 8-bit readable/writable register that stores output data for port a pins. bit bit name initial value r/w description 7 ? undefined ? 6 ? undefined ? 5 ? undefined ? 4 ? undefined ? reserved these bits are read as an undefined value. 3 pa3dr 0 r/w 2 pa2dr 0 r/w 1 pa1dr 0 r/w output data for a pin is stored when the pin is specified as a general purpose i/o port. 0 pa0dr 0 r/w 9.4.3 port a register (porta) porta is an 8-bit read-only register that shows port a pin states. porta cannot be modified. bit bit name initial value r/w description 7 ? undefined ? 6 ? undefined ? 5 ? undefined ? 4 ? undefined ? reserved these bits are read as an undefined value. 3 pa3 undefined * r 2 pa2 undefined * r 1 pa1 undefined * r if a port a read is performed while paddr bits are set to 1, the padr values are read. if a port a read is performed while paddr bits are cleared to 0, the pin states are read. 0 pa0 undefined * r note: * determined by the states of pins pa3 to pa0. section 9 i/o ports rev. 7.00 sep. 11, 2009 page 139 of 566 rej09b0211-0700 9.4.4 port a pull-up mos control register (papcr) papcr is an 8-bit register that controls the mos input pull-up function. bit bit name initial value r/w description 7 ? undefined ? 6 ? undefined ? 5 ? undefined ? 4 ? undefined ? reserved these bits are read as an undefined value. 3 pa3pcr 0 r/w 2 pa2pcr 0 r/w 1 pa1pcr 0 r/w when a pin is specified as an input port, setting the corresponding bit to 1 turns on the mos input pull- up for that pin. 0 pa0pcr 0 r/w 9.4.5 port a open-drain control register (paodr) paodr is an 8-bit read/write register that specifies the output type of port a. bit bit name initial value r/w description 7 ? undefined ? 6 ? undefined ? 5 ? undefined ? 4 ? undefined ? reserved these bits are read as an undefined value. 3 pa3odr 0 r/w 2 pa2odr 0 r/w 1 pa1odr 0 r/w 0 pa0odr 0 r/w when a pin is specified as an output port, setting the corresponding bit to 1 specifies pin output to open-drain and the mos input pull-up to the off state. clearing this bit to 0 specifies that to push- pull output. section 9 i/o ports rev. 7.00 sep. 11, 2009 page 140 of 566 rej09b0211-0700 9.4.6 pin functions port a pins also function as sci_2 i/o, interrupt input, and poe input pins. the correspondence between the register specification and the pin functions is shown below. note: the h8s/2614 and h8s/2616 have no poe input pins. table 9.10 pa3 pin function poe3e 0 1 cke1 0 1 ? c/a 0 1 ? ? cke0 0 1 ? ? ? pa3ddr 0 1 ? ? ? ? pin function pa3 input pa3 output sck2 output sck2 output sck2 input poe3 input table 9.11 pa2 pin function poe2e 0 1 re 0 1 ? pa2ddr 0 1 ? ? pin function pa2 input pa2 output rxd2 input poe2 input table 9.12 pa1 pin function poe1e 0 1 te 0 1 ? pa1ddr 0 1 ? ? pin function pa1 input pa1 output txd2 output poe1 input table 9.13 pa0 pin function poe0e 0 1 pa0ddr 0 1 ? pin function pa0 input pa0 output poe0 input section 9 i/o ports rev. 7.00 sep. 11, 2009 page 141 of 566 rej09b0211-0700 9.5 port b port b is an 8-bit i/o port that also has other functions. port b has the following registers. for details on register addresses and register states during each processing, refer to appendix a, on- chip i/o register. ? port b data direction register (pbddr) ? port b data register (pbdr) ? port b register (portb) ? port b pull-up mos control register (pbpcr) ? port b open-drain control register (pbodr) 9.5.1 port b data directio n register (pbddr) pbddr is an 8-bit write-only register, the individual bits of which specify whether the pins of port b are used for input or output. pbddr cannot be read; if it is, an undefined value will be read. bit bit name initial value r/w description 7 pb7ddr 0 w 6 pb6ddr 0 w 5 pb5ddr 0 w 4 pb4ddr 0 w 3 pb3ddr 0 w 2 pb2ddr 0 w 1 pb1ddr 0 w when a pin is specified as a general purpose i/o port, setting this bit to 1 makes the corresponding port 1 pin an output pin. clearing this bit to 0 makes the pin an input pin. 0 pb0ddr 0 w section 9 i/o ports rev. 7.00 sep. 11, 2009 page 142 of 566 rej09b0211-0700 9.5.2 port b data register (pbdr) pbdr is an 8-bit readable/writable register that stores output data for the port b pins. bit bit name initial value r/w description 7 pb7dr 0 r/w 6 pb6dr 0 r/w 5 pb5dr 0 r/w 4 pb4dr 0 r/w 3 pb3dr 0 r/w 2 pb2dr 0 r/w 1 pb1dr 0 r/w output data for a pin is stored when the pin is specified as a general purpose i/o port. 0 pb0dr 0 r/w 9.5.3 port b register (portb) portb is an 8-bit read-only register that shows port b pin states. portb cannot be modified. bit bit name initial value r/w description 7 pb7 undefined * r 6 pb6 undefined * r 5 pb5 undefined * r 4 pb4 undefined * r 3 pb3 undefined * r 2 pb2 undefined * r 1 pb1 undefined * r if a port b read is performed while pbddr bits are set to 1, the pbdr values are read. if a port b read is performed while pbddr bits are cleared to 0, the pin states are read. 0 pb0 undefined * r note: * determined by the states of pins pb7 to pb0. section 9 i/o ports rev. 7.00 sep. 11, 2009 page 143 of 566 rej09b0211-0700 9.5.4 port b pull-up mos control register (pbpcr) pbpcr is an 8-bit read/write register that controls the on/off state of mos input pull-up of port b. bit bit name initial value r/w description 7 pb7pcr 0 r/w 6 pb6pcr 0 r/w 5 pb5pcr 0 r/w 4 pb4pcr 0 r/w 3 pb3pcr 0 r/w 2 pb2pcr 0 r/w 1 pb1pcr 0 r/w when a pin is specified as an input port, setting the corresponding bit to 1 turns on the mos input pull- up for that pin. 0 pb0pcr 0 r/w 9.5.5 port b open-drain co ntrol register (pbodr) pbodr is an 8-bit read/write register that specifies the output type of port b. bit bit name initial value r/w description 7 pb7odr 0 r/w 6 pb6odr 0 r/w 5 pb5odr 0 r/w 4 pb4odr 0 r/w 3 pb3odr 0 r/w 2 pb2odr 0 r/w 1 pb1odr 0 r/w when a pin function is specified as an output port, setting the corresponding bit to 1 specifies pin output as open-drain and the pmos input pull-up to the off state. clearing this bit to 0 specifies push- pull output. 0 pb0odr 0 r/w section 9 i/o ports rev. 7.00 sep. 11, 2009 page 144 of 566 rej09b0211-0700 9.5.6 pin functions port b pins also function as tpu and mmt i/o pins. the correspondence between the register specification and the pin functions is shown below. note: the h8s/2614 and h8s/2616 have no mmt input and output pins. table 9.14 pb7 pin function pwobe 0 1 tpu channel 5 setting * output input or initial value ? pb7ddr ? 0 1 ? pb7 input pb7 output pin function tiocb5 output tiocb5 input pwob output note: * for details on the tpu channel specification, refer to section 10, 16-bit timer pulse unit (tpu). table 9.15 pb6 pin function pwoae 0 1 tpu channel 5 setting * output input or initial value ? pb6ddr ? 0 1 ? pb6 input pb6 output pin function tioca5 output tioca5 input pwoa output note: * for details on the tpu channel specification, refer to section 10, 16-bit timer pulse unit (tpu). section 9 i/o ports rev. 7.00 sep. 11, 2009 page 145 of 566 rej09b0211-0700 table 9.16 pb5 pin function pvobe 0 1 tpu channel 4 setting * output input or initial value ? pb5ddr ? 0 1 ? pb5 input pb5 output pin function tiocb4 output tiocb4 input pvob output note: * for details on the tpu channel specification, refer to section 10, 16-bit timer pulse unit (tpu). table 9.17 pb4 pin function pvoae 0 1 tpu channel 4 setting * output input or initial value ? pb4ddr ? 0 1 ? pb4 input pb4 output pin function tioca4 output tioca4 input pvoa output note: * for details on the tpu channel specification, refer to section 10, 16-bit timer pulse unit (tpu). table 9.18 pb3 pin function puobe 0 1 tpu channel 3 setting * output input or initial value ? pb3ddr ? 0 1 ? pb3 input pb3 output pin function tiocd3 output tiocd3 input puob output note: * for details on the tpu channel specification, refer to section 10, 16-bit timer pulse unit (tpu). section 9 i/o ports rev. 7.00 sep. 11, 2009 page 146 of 566 rej09b0211-0700 table 9.19 pb2 pin function puoae 0 1 tpu channel 3 setting * output input or initial value ? pb2ddr ? 0 1 ? pb2 input pb2 output pin function tiocc3 output tiocc3 input puoa output note: * for details on the tpu channel specification, refer to section 10, 16-bit timer pulse unit (tpu). table 9.20 pb1 pin function pcoe 0 1 tpu channel 3 setting * output input or initial value ? pb1ddr ? 0 1 ? pb1 input pb1 output pin function tiocb3 output tiocb3 input pco output note: * for details on the tpu channel specification, refer to section 10, 16-bit timer pulse unit (tpu). table 9.21 pb0 pin function pcie 0 1 tpu channel 3 setting * output input or initial value pb0ddr ? 0 1 0 pb0 input pb0 output pin function tioca3 output tioca3 input pci input note: * for details on the tpu channel specification, refer to section 10, 16-bit timer pulse unit (tpu). section 9 i/o ports rev. 7.00 sep. 11, 2009 page 147 of 566 rej09b0211-0700 9.6 port c port c is an 8-bit i/o port that also has other functions. port c has the following registers. for details on register addresses and register states during each processing, refer to appendix a, on- chip i/o register. ? port c data direction register (pcddr) ? port c data register (pcdr) ? port c register (portc) ? port c mos pull-up control register (pcpcr) ? port c open-drain control register (pcodr) 9.6.1 port c data di rection register (pcddr) pcddr is an 8-bit write-only register, the individual bits of which specify whether the pins of port c are used for input or output. pcddr cannot be read; if it is, an undefined value will be read. bit bit name initial value r/w description 7 pc7ddr 0 w 6 pc6ddr 0 w 5 pc5ddr 0 w 4 pc4ddr 0 w 3 pc3ddr 0 w 2 pc2ddr 0 w 1 pc1ddr 0 w when a pin is specified as a general purpose i/o port, setting this bit to 1 makes the corresponding port 1 pin an output pin. clearing this bit to 0 makes the pin an input pin. 0 pc0ddr 0 w section 9 i/o ports rev. 7.00 sep. 11, 2009 page 148 of 566 rej09b0211-0700 9.6.2 port c data register (pcdr) pcdr is an 8-bit readable/writable register that stores output data for the port c pins. bit bit name initial value r/w description 7 pc7dr 0 r/w 6 pc6dr 0 r/w 5 pc5dr 0 r/w 4 pc4dr 0 r/w 3 pc3dr 0 r/w 2 pc2dr 0 r/w 1 pc1dr 0 r/w output data for a pin is stored when the pin is specified as a general purpose i/o port. 0 pc0dr 0 r/w 9.6.3 port c register (portc) portc is an 8-bit read-only register that shows port c pin states. portc cannot be modified. bit bit name initial value r/w description 7 pc7 undefined * r 6 pc6 undefined * r 5 pc5 undefined * r 4 pc4 undefined * r 3 pc3 undefined * r 2 pc2 undefined * r 1 pc1 undefined * r if a port c read is performed while pcddr bits are set to 1, the pcdr values are read. if a port c read is performed while pcddr bits are cleared to 0, the pin states are read. 0 pc0 undefined * r note: * determined by the states of pins pc7 to pc0. section 9 i/o ports rev. 7.00 sep. 11, 2009 page 149 of 566 rej09b0211-0700 9.6.4 port c pull-up mos control register (pcpcr) pcpcr is an 8-bit read/write register that controls the on/off state of mos input pull-up of port c. bit bit name initial value r/w description 7 pc7pcr 0 r/w 6 pc6pcr 0 r/w 5 pc5pcr 0 r/w 4 pc4pcr 0 r/w 3 pc3pcr 0 r/w 2 pc2pcr 0 r/w 1 pc1pcr 0 r/w when a pin is specified as an input port, setting the corresponding bit to 1 turns on the mos input pull- up for that pin. 0 pc0pcr 0 r/w 9.6.5 port c open-drain control register (pcodr) pcodr is an 8-bit read/write register th at specifies an output type of port c. bit bit name initial value r/w description 7 pc7odr 0 r/w 6 pc6odr 0 r/w 5 pc5odr 0 r/w 4 pc4odr 0 r/w 3 pc3odr 0 r/w 2 pc2odr 0 r/w 1 pc1odr 0 r/w when a pin is specified as an output port, setting the corresponding bit to 1 specifies pin output as open-drain and the mos input pull-up to the off state. clearing this bit to 0 specifies push-pull output. 0 pc0odr 0 r/w section 9 i/o ports rev. 7.00 sep. 11, 2009 page 150 of 566 rej09b0211-0700 9.6.6 pin functions port c pins also function as sci_1 and sci_0 i/o and interrupt input. the correspondence between the register specification and the pin functions is shown below. pc7: this pin function is switched as shown below. pc7ddr 0 1 pin function pc7 input pc7 output pc6: this pin function is switched as shown below. pc6ddr 0 1 pin function pc6 input pc6 output pc5/sck1/ irq5 : the pin function is switched as show n below according to the operating mode, bit c/ a in the sci1?s smr, bits cke0 and cke1 in scr, and bit pc5ddr. cke1 0 1 c/ a 0 1 ? cke0 0 1 ? ? pc5ddr 0 1 ? ? ? pc5 input pin function irq5 input pc5 output sck1 output sck1 output sck1 input pc4/rxd1: the pin function is switched as show n below according to the operating mode, bit re in the sci1?s scr, and bit pc4ddr. re 0 1 pc4ddr 0 1 ? pin function pc4 input pc4 output rxd1 input section 9 i/o ports rev. 7.00 sep. 11, 2009 page 151 of 566 rej09b0211-0700 pc3/txd1: the pin function is switched as show n below according to th e operating mode, bit te in the sci1?s scr, and bit pc3ddr. te 0 1 pc3ddr 0 1 ? pin function pc3 input pc3 output txd1 output pc2/sck0/ irq4 : the pin function is switched as show n below according to the operating mode, bit c/ a in the sci0?s smr, bits cke0 and cke1 in scr, and bit pc2ddr. cke1 0 1 c/ a 0 1 ? cke0 0 1 ? ? pc2ddr 0 1 ? ? ? pin function pc2 input pc2 output sck0 output sck0 output sck0 input irq4 input pc1/rxd0: the pin function is switched as show n below according to the operating mode, bit re in the sci0?s scr, and bit pc1ddr. re 0 1 pc1ddr 0 1 ? pin function pc1 input pc1 output rxd0 input pc0/txd0: the pin function is switched as show n below according to th e operating mode, bit te in the sci0?s scr, and bit pc0ddr. te 0 1 pc0ddr 0 1 ? pin function pc0 input pc0 output txd0 output section 9 i/o ports rev. 7.00 sep. 11, 2009 page 152 of 566 rej09b0211-0700 9.7 port d port d is an 8-bit i/o port that also has other functions. port d has the following registers. for details on register addresses and register states during each processing, refer to appendix a, on- chip i/o register. ? port d data direction register (pdddr) ? port d data register (pddr) ? port d register (portd) ? port d pull-up mos control register (pdpcr) 9.7.1 port d data di rection register (pdddr) pdddr is an 8-bit write-only register, the individual bits of which specify whether the pins of port d are used for input or output. pdddr cannot be read; if it is, an undefined value will be read. bit bit name initial value r/w description 7 pd7ddr 0 w 6 pd6ddr 0 w 5 pd5ddr 0 w 4 pd4ddr 0 w 3 pd3ddr 0 w 2 pd2ddr 0 w 1 pd1ddr 0 w when a pin is specified as a general purpose i/o port, setting this bit to 1 makes the corresponding port 1 pin an output pin. clearing this bit to 0 makes the pin an input pin. 0 pd0ddr 0 w section 9 i/o ports rev. 7.00 sep. 11, 2009 page 153 of 566 rej09b0211-0700 9.7.2 port d data register (pddr) pddr is an 8-bit readable/writable register that stores output data for the port d pins. bit bit name initial value r/w description 7 pd7dr 0 r/w 6 pd6dr 0 r/w 5 pd5dr 0 r/w 4 pd4dr 0 r/w 3 pd3dr 0 r/w 2 pd2dr 0 r/w 1 pd1dr 0 r/w output data for a pin is stored when the pin is specified as a general purpose i/o port. 0 pd0dr 0 r/w 9.7.3 port d register (portd) portd is an 8-bit read-only register that shows port d pin states. portd cannot be modified. bit bit name initial value r/w description 7 pd7 undefined * r 6 pd6 undefined * r 5 pd5 undefined * r 4 pd4 undefined * r 3 pd3 undefined * r 2 pd2 undefined * r 1 pd1 undefined * r if a port d read is performed while pdddr bits are set to 1, the pddr values are read. if a port d read is performed while pdddr bits are cleared to 0, the pin states are read. 0 pd0 undefined * r note: * determined by the states of pins pd7 to pd0. section 9 i/o ports rev. 7.00 sep. 11, 2009 page 154 of 566 rej09b0211-0700 9.7.4 port d pull-up mos control register (pdpcr) pdpcr is an 8-bit readable/writable register that controls on/off states of the input pull-up mos of port d. bit bit name initial value r/w description 7 pd7pcr 0 r/w 6 pd6pcr 0 r/w 5 pd5pcr 0 r/w 4 pd4pcr 0 r/w 3 pd3pcr 0 r/w 2 pd2pcr 0 r/w 1 pd1pcr 0 r/w when the pin is in its input state, the input pull-up mos of the input pin is on when the corresponding bit is set to 1. 0 pd0pcr 0 r/w section 9 i/o ports rev. 7.00 sep. 11, 2009 page 155 of 566 rej09b0211-0700 9.8 port f port f is an 8-bit i/o port that also has other functions. port f has the following registers. for details on register addresses and register states during each processing, refer to appendix a, on- chip i/o register. ? port f data direction register (pfddr) ? port f data register (pfdr) ? port f register (portf) 9.8.1 port f data di rection register (pfddr) pfddr is an 8-bit write-only register, the individual bits of which specify whether the pins of port f are used for input or output. pfddr cannot be read; if it is, an undefined value will be read. bit bit name initial value r/w description 7 pf7ddr 0 w when a pin is specified as a general purpose i/o port, setting this bit to 1 makes the pf7 pin a output pin. clearing this bit to 0 makes the pin an input pin. 6 pf6ddr 0 w 5 pf5ddr 0 w 4 pf4ddr 0 w 3 pf3ddr 0 w 2 pf2ddr 0 w 1 pf1ddr 0 w when a pin is specified as a general purpose i/o port, setting this bit to 1 makes the corresponding port f pin an output pin. clearing this bit to 0 makes the pin an input pin. 0 pf0ddr 0 w section 9 i/o ports rev. 7.00 sep. 11, 2009 page 156 of 566 rej09b0211-0700 9.8.2 port f data register (pfdr) pfdr is an 8-bit readable/writable register that stores output data for the port f pins. bit bit name initial value r/w description 7 ? 0 r/w reserved only 0 should be written to this bit. 6 pf6dr 0 r/w 5 pf5dr 0 r/w 4 pf4dr 0 r/w 3 pf3dr 0 r/w 2 pf2dr 0 r/w 1 pf1dr 0 r/w output data for a pin is stored when the pin is specified as a general purpose i/o port. 0 pf0dr 0 r/w 9.8.3 port f register (portf) portf is an 8-bit read-only register that shows port f pin states. portf cannot be modified. bit bit name initial value r/w description 7 pf7 undefined * r 6 pf6 undefined * r 5 pf5 undefined * r 4 pf4 undefined * r 3 pf3 undefined * r 2 pf2 undefined * r 1 pf1 undefined * r if a port f read is performed while pfddr bits are set to 1, the pfdr values are read. if a port f read is performed while pfddr bits are cleared to 0, the pin states are read. 0 pf0 undefined * r note: * determined by the states of pins pf7 to pf0. section 9 i/o ports rev. 7.00 sep. 11, 2009 page 157 of 566 rej09b0211-0700 9.8.4 pin functions port f is an 8-bit i/o port. port f pins also function as external interrupt input, irq2 and irq3 , a/d trigger input ( adtrg ), and system clock output ( ). pf7/ : the pin function is switched as shown below according to bit pf7ddr. pf7ddr 0 1 pin function pf7 input output pf6: the pin function is switched as shown below according to bit pf6ddr. pf6ddr 0 1 pin function pf6 input pf6 output pf5: the pin function is switched as shown below according to bit pf5ddr. pf5ddr 0 1 pin function pf5 input pf5 output pf4: the pin function is switched as shown below according to bit pf4ddr. pf4ddr 0 1 pin function pf4 input pf4 output pf3/ adtrg / irq3 : the pin function is switched as s hown below according to the operating mode, the bus mode, a/d converter bits trgs1 and trgs0, and bit pf3ddr. pf3ddr 0 1 pf3 input adtrg input * 1 pin function irq3 input * 2 pf3 output notes: 1. adtrg input when trgs0 = trgs1 = 1. 2. when used as an external interrupt input pin, do not use as an i/o pin for another function. section 9 i/o ports rev. 7.00 sep. 11, 2009 page 158 of 566 rej09b0211-0700 pf2: the pin function is switched as shown below according to bit pf2ddr. pf2ddr 0 1 pin function pf2 input pf2 output pf1: the pin function is switched as shown below according to bit pf1ddr. pf1ddr 0 1 pin function pf1 input pf1 output pf0/ irq2 : the pin function is switched as shown below according to bit pf0ddr. pfddr 0 1 pf0 input pin function irq2 input pf0 output section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 159 of 566 rej09b0211-0700 section 10 16-bit timer pulse unit (tpu) this lsi has an on-chip 16-bit timer pulse unit (tpu) comprised of six 16-bit timer channels. the function list of the 16-bit timer unit and its block diagram are shown in table 10.1 and figure 10.1, respectively. note: dtc or ppg are not implemented in the h8s/2614 and h8s/2616. 10.1 features ? maximum 16-pulse input/output ? selection of 8 counter input clocks for each channel ? the following operations can be set for each channel ? waveform output at compare match ? input capture function ? counter clear operation ? synchronous operation ? multiple timer counters (tcnt) can be written to simultaneously ? simultaneous clearing by compare match and input capture is possible ? register simultaneous input/output is possible by synchronous counter operation ? a maximum 15-phase pwm output is possible in combination with synchronous operation ? buffer operation settable for channels 0 and 3 ? phase counting mode settable independently for each of channels 1, 2, 4, and 5 ? cascaded operation ? fast access via internal 16-bit bus ? 26 interrupt sources ? automatic transfer of register data ? programmable pulse generator (ppg) output trigger can be generated ? a/d converter conversion start trigger can be generated ? module stop mode can be set section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 160 of 566 rej09b0211-0700 table 10.1 tpu functions item channel 0 channel 1 channel 2 channel 3 channel 4 channel 5 count clock /1 /4 /16 /64 tclka tclkb tclkc tclkd /1 /4 /16 /64 /256 tclka tclkb /1 /4 /16 /64 /1024 tclka tclkb tclkc /1 /4 /16 /64 /256 /1024 /4096 tclka /1 /4 /16 /64 /1024 tclka tclkc /1 /4 /16 /64 /256 tclka tclkc tclkd general registers tgra_0 tgrb_0 tgra_1 tgrb_1 tgra_2 tgrb_2 tgra_3 tgrb_3 tgra_4 tgrb_4 tgra_5 tgrb_5 general registers/ buffer registers tgrc_0 tgrd_0 ? ? tgrc_3 tgrd_3 ? ? i/o pins tioca0 tiocb0 tiocc0 tiocd0 tioca1 tiocb1 tioca2 tiocb2 tioca3 tiocb3 tiocc3 tiocd3 tioca4 tiocb4 tioca5 tiocb5 counter clear function tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture 0 output o o o o o o 1 output o o o o o o compare match output toggle output o o o o o o input capture function o o o o o o synchronous operation o o o o o o pwm mode o o o o o o phase counting mode ? o o ? o o buffer operation o ? ? o ? ? section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 161 of 566 rej09b0211-0700 item channel 0 channel 1 channel 2 channel 3 channel 4 channel 5 dtc activation tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture a/d converter trigger tgra_0 compare match or input capture tgra_1 compare match or input capture tgra_2 compare match or input capture tgra_3 compare match or input capture tgra_4 compare match or input capture tgra_5 compare match or input capture ppg trigger tgra_0/ tgrb_0 compare match or input capture tgra_1/ tgrb_1 compare match or input capture tgra_2/ tgrb_2 compare match or input capture tgra_3/ tgrb_3 compare match or input capture ? ? interrupt sources 5 sources ? compare match or input capture 0a ? compare match or input capture 0b ? compare match or input capture 0c ? compare match or input capture 0d ? overflow 4 sources ? compare match or input capture 1a ? compare match or input capture 1b ? overflow ? underflow 4 sources ? compare match or input capture 2a ? compare match or input capture 2b ? overflow ? underflow 5 sources ? compare match or input capture 3a ? compare match or input capture 3b ? compare match or input capture 3c ? compare match or input capture 3d ? overflow 4 sources ? compare match or input capture 4a ? compare match or input capture 4b ? overflow ? underflow 4 sources ? compare match or input capture 5a ? compare match or input capture 5b ? overflow ? underflow legend: o : possible ?: not possible section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 162 of 566 rej09b0211-0700 channel 3 tmdr tiorl tsr tcr tiorh tier tgra tcnt tgrb tgrc tgrd channel 4 tmdr tsr tcr tior tier tgra tcnt tgrb channel 5 tmdr tsr tcr tior tier tgra tcnt tgrb control lo g ic for channels 3 to 5 channel 2 tmdr tsr tcr tior tier tgra tcnt tgrb tgrc channel 1 tmdr tsr tcr tior tier tgra tcnt tgrb channel 0 control lo g ic for channels 0 to 2 tgra tcnt tgrb tgrd bus interface common tsyr control lo g ic tstr tioca3 tiocb3 tiocc3 tiocd3 tioca4 tiocb4 tioca5 tiocb5 /1 /4 /16 /64 /256 /1024 /4096 tclka tclkb tclkc tclkd le g end: tstr: tsyr: tcr: tmdr: timer start re g ister timer synchro re g ister timer control re g ister timer mode re g ister timer i/o control re g isters (h, l) timer interrupt enable re g ister timer status re g ister timer g eneral re g isters (a to d) tioca0 tiocb0 tiocc0 tiocd0 tioca1 tiocb1 tioca2 tiocb2 interrupt request si g nals channel 3: channel 4: channel 5: interrupt request si g nals channel 3: channel 4: channel 5: internal data bus ppg output tri gg er si g nal a/d converter convertion start si g nal module data bus tgia_3 tgib_3 tgic_3 tgid_3 tciv_3 tgia_4 tgib_4 tciv_4 tciu_4 tgia_5 tgib_5 tciv_5 tciu_5 tgia_0 tgib_0 tgic_0 tgid_0 tciv_0 tgia_1 tgib_1 tciv_1 tciu_1 tgia_2 tgib_2 tciv_2 tciu_2 tmdr tsr tcr tiorh tier tiorl input/output pins channel 3: channel 4: channel 5: input/output pins channel 0: channel 1: channel 2: clock input internal clock: external clock: tior (h, l): tier: tsr: tgr (a to d): figure 10.1 block diagram of tpu section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 163 of 566 rej09b0211-0700 10.2 input/output pins table 10.2 tpu pins channel symbol i/o function all tclka input external clock a input pin (channels 1 and 5 phase counting mode a phase input) tclkb input external clock b input pin (channels 1 and 5 phase counting mode b phase input) tclkc input external clock c input pin (channels 2 and 4 phase counting mode a phase input) tclkd input external clock d input pin (channels 2 and 4 phase counting mode b phase input) 0 tioca0 i/o tgra_0 input capture input/output compare output/pwm output pin tiocb0 i/o tgrb_0 input capture input/output compare output/pwm output pin tiocc0 i/o tgrc_0 input capture input/output compare output/pwm output pin tiocd0 i/o tgrd_0 input capture input/output compare output/pwm output pin 1 tioca1 i/o tgra_1 input capture input/output compare output/pwm output pin tiocb1 i/o tgrb_1 input capture input/output compare output/pwm output pin 2 tioca2 i/o tgra_2 input capture input/output compare output/pwm output pin tiocb2 i/o tgrb_2 input capture input/output compare output/pwm output pin 3 tioca3 i/o tgra_3 input capture input/output compare output/pwm output pin tiocb3 i/o tgrb_3 input capture input/output compare output/pwm output pin tiocc3 i/o tgrc_3 input capture input/output compare output/pwm output pin tiocd3 i/o tgrd_3 input capture input/output compare output/pwm output pin 4 tioca4 i/o tgra_4 input capture input/output compare output/pwm output pin tiocb4 i/o tgrb_4 input capture input/output compare output/pwm output pin 5 tioca5 i/o tgra_5 input capture input/output compare output/pwm output pin tiocb5 i/o tgrb_5 input capture input/output compare output/pwm output pin section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 164 of 566 rej09b0211-0700 10.3 register descriptions the tpu has the following registers. for details on register addresses and register states during each process, refer to appendix a, on-chip i/o regi ster. to distinguish registers in each channel, an underscore and the channel number are added as a suffix to the register name; tcr for channel 0 is expressed as tcr_0. ? timer control register_0 (tcr_0) ? timer mode register_0 (tmdr_0) ? timer i/o control register h_0 (tiorh_0) ? timer i/o control register l_0 (tiorl_0) ? timer interrupt enable register_0 (tier_0) ? timer status register_0 (tsr_0) ? timer counter_0 (tcnt_0) ? timer general register a_0 (tgra_0) ? timer general register b_0 (tgrb_0) ? timer general register c_0 (tgrc_0) ? timer general register d_0 (tgrd_0) ? timer control register_1 (tcr_1) ? timer mode register_1 (tmdr_1) ? timer i/o control register _1 (tior_1) ? timer interrupt enable register_1 (tier_1) ? timer status register_1 (tsr_1) ? timer counter_1 (tcnt_1) ? timer general register a_1 (tgra_1) ? timer general register b_1 (tgrb_1) ? timer control register_2 (tcr_2) ? timer mode register_2 (tmdr_2) ? timer i/o control register_2 (tior_2) ? timer interrupt enable register_2 (tier_2) ? timer status register_2 (tsr_2) ? timer counter_2 (tcnt_2) ? timer general register a_2 (tgra_2) ? timer general register b_2 (tgrb_2) ? timer control register_3 (tcr_3) ? timer mode register_3 (tmdr_3) section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 165 of 566 rej09b0211-0700 ? timer i/o control register h_3 (tiorh_3) ? timer i/o control register l_3 (tiorl_3) ? timer interrupt enable register_3 (tier_3) ? timer status register_3 (tsr_3) ? timer counter_3 (tcnt_3) ? timer general register a_3 (tgra_3) ? timer general register b_3 (tgrb_3) ? timer general register c_3 (tgrc_3) ? timer general register d_3 (tgrd_3) ? timer control register_4 (tcr_4) ? timer mode register_4 (tmdr_4) ? timer i/o control register _4 (tior_4) ? timer interrupt enable register_4 (tier_4) ? timer status register_4 (tsr_4) ? timer counter_4 (tcnt_4) ? timer general register a_4 (tgra_4) ? timer general register b_4 (tgrb_4) ? timer control register_5 (tcr_5) ? timer mode register_5 (tmdr_5) ? timer i/o control register_5 (tior_5) ? timer interrupt enable register_5 (tier_5) ? timer status register_5 (tsr_5) ? timer counter_5 (tcnt_5) ? timer general register a_5 (tgra_5) ? timer general register b_5 (tgrb_5) common registers ? timer start register (tstr) ? timer synchro register (tsyr) section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 166 of 566 rej09b0211-0700 10.3.1 timer control register (tcr) the tcr registers are 8-bit readable/writable regi sters that control the tcnt operation for each channel. the tpu has a total of six tcr registers, one for each channel (channels 0 to 5). tcr register settings should be conducted only when tcnt operation is stopped. bit bit name initial value r/w description 7 6 5 cclr2 cclr1 cclr0 0 0 0 r/w r/w r/w counter clear 0 to 2 these bits select the tcnt counter clearing source. see tables 10.3 and 10.4 for details. 4 3 ckeg1 ckeg0 0 0 r/w r/w clock edge 0 and 1 these bits select the input clock edge. when the input clock is counted using both edges, the input clock period is halved (e.g. /4 both edges = /2 rising edge). if phase counting mode is used on channels 1, 2, 4, and 5, this setting is ignored and the phase counting mode setting has priority. internal clock edge selection is valid when the input clock is /4 or slower. this setting is ignored if the input clock is / 1, or when overflow/underflow of another channel is selected. 00: count at rising edge 01: count at falling edge 1x: count at both edges legend: x: don?t care 2 1 0 tpsc2 tpsc1 tpsc0 0 0 0 r/w r/w r/w time prescaler 0 to 2 these bits select the tcnt counter clock. the clock source can be selected independently for each channel. see tables10.5 to10.10 for details. section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 167 of 566 rej09b0211-0700 table 10.3 cclr0 to cclr2 (channels 0 and 3) channel bit 7 cclr2 bit 6 cclr1 bit 5 cclr0 description 0, 3 0 0 0 tcnt clearing disabled 1 tcnt cleared by tgra compare match/input capture 1 0 tcnt cleared by tgrb compare match/input capture 1 tcnt cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation * 1 1 0 0 tcnt clearing disabled 1 tcnt cleared by tgrc compare match/input capture * 2 1 0 tcnt cleared by tgrd compare match/input capture * 2 1 tcnt cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation * 1 notes: 1. synchronous operation is set by setting the sync bit in tsyr to 1. 2. when tgrc or tgrd is used as a buffer register, tcnt is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. table 10.4 cclr0 to cclr2 (channels 1, 2, 4, and 5) channel bit 7 reserved * 2 bit 6 cclr1 bit 5 cclr0 description 1, 2, 4, 5 0 0 0 tcnt clearing disabled 1 tcnt cleared by tgra compare match/input capture 1 0 tcnt cleared by tgrb compare match/input capture 1 tcnt cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation * 1 notes: 1. synchronous operation is selected by setting the sync bit in tsyr to 1. 2. bit 7 is reserved in channels 1, 2, 4, and 5. it is always read as 0 and cannot be modified. section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 168 of 566 rej09b0211-0700 table 10.5 tpsc0 to tpsc2 (channel 0) channel bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 description 0 0 0 0 internal clock: counts on /1 1 internal clock: counts on /4 1 0 internal clock: counts on /16 1 internal clock: counts on /64 1 0 0 external clock: counts on tclka pin input 1 external clock: counts on tclkb pin input 1 0 external clock: counts on tclkc pin input 1 external clock: counts on tclkd pin input table 10.6 tpsc0 to tpsc2 (channel 1) channel bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 description 1 0 0 0 internal clock: counts on /1 1 internal clock: counts on /4 1 0 internal clock: counts on /16 1 internal clock: counts on /64 1 0 0 external clock: counts on tclka pin input 1 external clock: counts on tclkb pin input 1 0 internal clock: counts on /256 1 counts on tcnt2 overflow/underflow note: this setting is ignored when channel 1 is in phase counting mode. section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 169 of 566 rej09b0211-0700 table 10.7 tpsc0 to tpsc2 (channel 2) channel bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 description 2 0 0 0 internal clock: counts on /1 1 internal clock: counts on /4 1 0 internal clock: counts on /16 1 internal clock: counts on /64 1 0 0 external clock: counts on tclka pin input 1 external clock: counts on tclkb pin input 1 0 external clock: counts on tclkc pin input 1 internal clock: counts on /1024 note: this setting is ignored when channel 2 is in phase counting mode. table 10.8 tpsc0 to tpsc2 (channel 3) channel bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 description 3 0 0 0 internal clock: counts on /1 1 internal clock: counts on /4 1 0 internal clock: counts on /16 1 internal clock: counts on /64 1 0 0 external clock: counts on tclka pin input 1 internal clock: counts on /1024 1 0 internal clock: counts on /256 1 internal clock: counts on /4096 section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 170 of 566 rej09b0211-0700 table 10.9 tpsc0 to tpsc2 (channel 4) channel bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 description 4 0 0 0 internal clock: counts on /1 1 internal clock: counts on /4 1 0 internal clock: counts on /16 1 internal clock: counts on /64 1 0 0 external clock: counts on tclka pin input 1 external clock: counts on tclkc pin input 1 0 internal clock: counts on /1024 1 counts on tcnt5 overflow/underflow note: this setting is ignored when channel 4 is in phase counting mode. table 10.10 tpsc0 to tpsc2 (channel 5) channel bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 description 5 0 0 0 internal clock: counts on /1 1 internal clock: counts on /4 1 0 internal clock: counts on /16 1 internal clock: counts on /64 1 0 0 external clock: counts on tclka pin input 1 external clock: counts on tclkc pin input 1 0 internal clock: counts on /256 1 external clock: counts on tclkd pin input note: this setting is ignored when channel 5 is in phase counting mode. section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 171 of 566 rej09b0211-0700 10.3.2 timer mode register (tmdr) the tmdr registers are 8-bit readab le/writable registers that are used to set the operating mode of each channel. the tpu has six tmdr registers, one for each channel. tmdr register settings should be changed only when tcnt operation is stopped. bit bit name initial value r/w description 7, 6 ? all 1 ? reserved these bits are always read as 1 and cannot be modified. 5 bfb 0 r/w buffer operation b specifies whether tgrb is to operate in the normal way, or tgrb and tgrd are to be used together for buffer operation. when tgrd is used as a buffer register, tgrd input capture/output compare is not generated. in channels 1, 2, 4, and 5, which have no tgrd, bit 5 is reserved. it is always read as 0 and cannot be modified. 0: tgrb operates normally 1: tgrb and tgrd used together for buffer operation 4 bfa 0 r/w buffer operation a specifies whether tgra is to operate in the normal way, or tgra and tgrc are to be used together for buffer operation. when tgrc is used as a buffer register, tgrc input capture/output compare is not generated. in channels 1, 2, 4, and 5, which have no tgrc, bit 4 is reserved. it is always read as 0 and cannot be modified. 0: tgra operates normally 1: tgra and tgrc used together for buffer operation 3 2 1 0 md3 md2 md1 md0 0 0 0 0 r/w r/w r/w r/w modes 0 to 3 these bits are used to set the timer operating mode. md3 is a reserved bit. in a write, it should always be written with 0. see table 10.11 for details. section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 172 of 566 rej09b0211-0700 table 10.11 md0 to md3 bit 3 md3 * 1 bit 2 md2 * 2 bit 1 md1 bit 0 md0 description 0 0 0 0 normal operation 1 reserved 1 0 pwm mode 1 1 pwm mode 2 1 0 0 phase counting mode 1 1 phase counting mode 2 1 0 phase counting mode 3 1 phase counting mode 4 1 x x x ? legend: x: don?t care notes: 1. md3 is a reserved bit. in a write, it should always be written with 0. 2. phase counting mode cannot be set for channels 0 and 3. in this case, 0 should always be written to md2. section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 173 of 566 rej09b0211-0700 10.3.3 timer i/o control register (tior) the tior registers are 8-bit read able/writable registers that control the tgr registers. the tpu has eight tior registers, two each for channels 0 a nd 3, and one each for channels 1, 2, 4, and 5. care is required as tior is a ffected by the tmdr setting. the initial output specified by tior is valid when the counter is stopped (the cst bit in tstr is cleared to 0). note also that, in pwm mode 2, the output at the point at which the counter is cleared to 0 is specified. when tgrc or tgrd is designated for buffer opera tion, this setting is invalid and the register operates as a buffer register. tiorh_0, tior_1, tior_2, tiorh_3, tior_4, tior_5 bit bit name initial value r/w description 7 6 5 4 iob3 iob2 iob1 iob0 0 0 0 0 r/w r/w r/w r/w i/o control b0 to b3 specify the function of tgrb. 3 2 1 0 ioa3 ioa2 ioa1 ioa0 0 0 0 0 r/w r/w r/w r/w i/o control a0 to a3 specify the function of tgra. tiorl_0, tiorl_3 bit bit name initial value r/w description 7 6 5 4 iod3 iod2 iod1 iod0 0 0 0 0 r/w r/w r/w r/w i/o control d0 to d3 specify the function of tgrd. 3 2 1 0 ioc3 ioc2 ioc1 ioc0 0 0 0 0 r/w r/w r/w r/w i/o control c0 to c3 specify the function of tgrc. section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 174 of 566 rej09b0211-0700 table 10.12 tiorh_0 (channel 0) description bit 7 iob3 bit 6 iob2 bit 5 iob1 bit 4 iob0 tgrb_0 function tiocb_0 pin function 0 0 0 0 output disabled 1 output compare register initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 initial output is 1 toggle output at compare match 1 0 0 0 input capture at rising edge 1 input capture at falling edge 1 x input capture register input capture at both edges 1 x x capture input source is channel 1/count clock input capture at tcnt_1 count-up/count-down * legend: x: don?t care note: * when bits tpsc0 to tpsc2 in tcr_1 are set to b'000 and /1 is used as the tcnt_1 count clock, this setting is invalid and input capture is not generated. section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 175 of 566 rej09b0211-0700 table 10.13 tiorl_0 (channel 0) description bit 7 iod3 bit 6 iod2 bit 5 iod1 bit 4 iod0 tgrd_0 function tiocd_0 pin function 0 0 0 0 output disabled 1 output compare register * 2 initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 initial output is 1 toggle output at compare match 1 0 0 0 input capture at rising edge 1 input capture at falling edge 1 x input capture register * 2 input capture at both edges 1 x x capture input source is channel 1/count clock input capture at tcnt_1 count-up/count-down * 1 legend: x: don?t care notes: 1. when bits tpsc0 to tpsc2 in tcr_1 are set to b'000 and /1 is used as the tcnt_1 count clock, this setting is invalid and input capture is not generated. 2. when the bfb bit in tmdr_0 is set to 1 and tgrd_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 176 of 566 rej09b0211-0700 table 10.14 tior_1 (channel 1) description bit 7 iob3 bit 6 iob2 bit 5 iob1 bit 4 iob0 tgrb_1 function tiocb_1 pin function 0 0 0 0 output disabled 1 output compare register initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 initial output is 1 toggle output at compare match 1 0 0 0 input capture at rising edge 1 input capture at falling edge 1 x input capture register input capture at both edges 1 x x tgrc_0 compare match/input capture input capture at generation of tgrc_0 compare match/input capture legend: x: don?t care section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 177 of 566 rej09b0211-0700 table 10.15 tior_2 (channel 2) description bit 7 iob3 bit 6 iob2 bit 5 iob1 bit 4 iob0 tgrb_2 function tiocb_2 pin function 0 0 0 0 output disabled 1 output compare register initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 initial output is 1 toggle output at compare match 1 x 0 0 input capture at rising edge 1 input capture at falling edge 1 x input capture register input capture at both edges legend: x: don?t care section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 178 of 566 rej09b0211-0700 table 10.16 tiorh_3 (channel 3) description bit 7 iob3 bit 6 iob2 bit 5 iob1 bit 4 iob0 tgrb_3 function tiocb_3 pin function 0 0 0 0 output disabled 1 output compare register initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 initial output is 1 toggle output at compare match 1 0 0 0 input capture at rising edge 1 input capture at falling edge 1 x input capture register input capture at both edges 1 x x capture input source is channel 4/count clock input capture at tcnt_4 count-up/count-down * legend: x: don?t care note: * when bits tpsc0 to tpsc2 in tcr_4 are set to b'000 and /1 is used as the tcnt_4 count clock, this setting is invalid and input capture is not generated. section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 179 of 566 rej09b0211-0700 table 10.17 tiorl_3 (channel 3) description bit 7 iod3 bit 6 iod2 bit 5 iod1 bit 4 iod0 tgrd_3 function tiocd_3 pin function 0 0 0 0 output disabled 1 output compare register * 2 initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 initial output is 1 toggle output at compare match 1 0 0 0 input capture at rising edge 1 input capture at falling edge 1 x input capture register * 2 input capture at both edges 1 x x capture input source is channel 4/count clock input capture at tcnt_4 count-up/count-down * 1 legend: x: don?t care notes: 1. when bits tpsc0 to tpsc2 in tcr_4 are set to b'000 and /1 is used as the tcnt_4 count clock, this setting is invalid and input capture is not generated. 2. when the bfb bit in tmdr_3 is set to 1 and tgrd_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 180 of 566 rej09b0211-0700 table 10.18 tior_4 (channel 4) description bit 7 iob3 bit 6 iob2 bit 5 iob1 bit 4 iob0 tgrb_4 function tiocb_4 pin function 0 0 0 0 output disabled 1 output compare register initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 initial output is 1 toggle output at compare match 1 0 0 0 input capture at rising edge 1 input capture at falling edge 1 x input capture register input capture at both edges 1 x x capture input source is tgrc_3 compare match/input capture input capture at generation of tgrc_3 compare match/input capture legend: x: don?t care section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 181 of 566 rej09b0211-0700 table 10.19 tior_5 (channel 5) description bit 7 iob3 bit 6 iob2 bit 5 iob1 bit 4 iob0 tgrb_5 function tiocb_5 pin function 0 0 0 0 output disabled 1 output compare register initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 initial output is 1 toggle output at compare match 1 x 0 0 input capture at rising edge 1 input capture at falling edge 1 x input capture register input capture at both edges legend: x: don?t care section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 182 of 566 rej09b0211-0700 table 10.20 tiorh_0 (channel 0) description bit 3 ioa3 bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 tgra_0 function tioca_0 pin function 0 0 0 0 output disabled 1 output compare register initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 initial output is 1 toggle output at compare match 1 0 0 0 capture input source is tioca0 pin input capture at rising edge 1 input capture at falling edge 1 x input capture register input capture at both edges 1 x x capture input source is channel 1/count clock input capture at tcnt_1 count-up/count-down legend: x: don?t care section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 183 of 566 rej09b0211-0700 table 10.21 tiorl_0 (channel 0) description bit 3 ioc3 bit 2 ioc2 bit 1 ioc1 bit 0 ioc0 tgrc_0 function tiocc_0 pin function 0 0 0 0 output disabled 1 output compare register * initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 initial output is 1 toggle output at compare match 1 0 0 0 input capture at rising edge 1 input capture at falling edge 1 x input capture register * input capture at both edges 1 x x capture input source is channel 1/count clock input capture at tcnt_1 count-up/count-down legend: x: don?t care note: * when the bfa bit in tmdr_0 is set to 1 and tgrc_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 184 of 566 rej09b0211-0700 table 10.22 tior_1 (channel 1) description bit 3 ioa3 bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 tgra_1 function tioca_1 pin function 0 0 0 0 output disabled 1 output compare register initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 initial output is 1 toggle output at compare match 1 0 0 0 input capture at rising edge 1 input capture at falling edge 1 x input capture register input capture at both edges 1 x x capture input source is tgra_0 compare match/input capture input capture at generation of channel 0/tgra_0 compare match/input capture legend: x: don?t care section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 185 of 566 rej09b0211-0700 table 10.23 tior_2 (channel 2) description bit 3 ioa3 bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 tgra_2 function tioca_2 pin function 0 0 0 0 output disabled 1 output compare register initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 initial output is 1 toggle output at compare match 1 x 0 0 input capture at rising edge 1 input capture at falling edge 1 x input capture register input capture at both edges legend: x: don?t care section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 186 of 566 rej09b0211-0700 table 10.24 tiorh_3 (channel 3) description bit 3 ioa3 bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 tgra_3 function tioca_3 pin function 0 0 0 0 output disabled 1 output compare register initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 initial output is 1 toggle output at compare match 1 0 0 0 input capture at rising edge 1 input capture at falling edge 1 x input capture register input capture at both edges 1 x x capture input source is channel 4/count clock input capture at tcnt_4 count-up/count-down legend: x: don?t care section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 187 of 566 rej09b0211-0700 table 10.25 tiorl_3 (channel 3) description bit 3 ioc3 bit 2 ioc2 bit 1 ioc1 bit 0 ioc0 tgrc_3 function tiocc_3 pin function 0 0 0 0 output disabled 1 output compare register * initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 initial output is 1 toggle output at compare match 1 0 0 0 input capture at rising edge 1 input capture at falling edge 1 x input capture register * input capture at both edges 1 x x capture input source is channel 4/count clock input capture at tcnt_4 count-up/count-down legend: x: don?t care note: * when the bfa bit in tmdr_3 is set to 1 and tgrc_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 188 of 566 rej09b0211-0700 table 10.26 tior_4 (channel 4) description bit 3 ioa3 bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 tgra_4 function tioca_4 pin function 0 0 0 0 output disabled 1 output compare register initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 initial output is 1 toggle output at compare match 1 0 0 0 input capture at rising edge 1 input capture at falling edge 1 x input capture register input capture at both edges 1 x x capture input source is tgra_3 compare match/input capture input capture at generation of tgra_3 compare match/input capture legend: x: don?t care section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 189 of 566 rej09b0211-0700 table 10.27 tior_5 (channel 5) description bit 3 ioa3 bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 tgra_5 function tioca_5 pin function 0 0 0 0 output disabled 1 output compare register initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 initial output is 1 toggle output at compare match 1 x 0 0 input capture at rising edge 1 input capture at falling edge 1 x input capture register input capture at both edges legend: x: don?t care section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 190 of 566 rej09b0211-0700 10.3.4 timer interrupt enable register (tier) the tier registers are 8-bit read able/writable registers that control enabling or disabling of interrupt requests for each channel. the tpu ha s six tier registers, one for each channel. bit bit name initial value r/w description 7 ttge 0 r/w a/d conversion start request enable enables or disables generation of a/d conversion start requests by tgra input capture/compare match. 0: a/d conversion start request generation disabled 1: a/d conversion start request generation enabled 6 ? 1 ? reserved this bit is always read as 1 and cannot be modified. 5 tcieu 0 r/w underflow interrupt enable enables or disables interrupt requests (tciu) by the tcfu flag when the tcfu flag in tsr is set to 1 in channels 1, 2, 4, and 5. in channels 0 and 3, bit 5 is reserved. it is always read as 0 and cannot be modified. 0: interrupt requests (tciu) by tcfu disabled 1: interrupt requests (tciu) by tcfu enabled 4 tciev 0 r/w overflow interrupt enable enables or disables interrupt requests (tciv) by the tcfv flag when the tcfv flag in tsr is set to 1. 0: interrupt requests (tciv) by tcfv disabled 1: interrupt requests (tciv) by tcfv enabled 3 tgied 0 r/w tgr interrupt enable d enables or disables interrupt requests (tgid) by the tgfd bit when the tgfd bit in tsr is set to 1 in channels 0 and 3. in channels 1, 2, 4, and 5, bit 3 is reserved. it is always read as 0 and cannot be modified. 0: interrupt requests (tgid) by tgfd bit disabled 1: interrupt requests (tgid) by tgfd bit enabled section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 191 of 566 rej09b0211-0700 bit bit name initial value r/w description 2 tgiec 0 r/w tgr interrupt enable c enables or disables interrupt requests (tgic) by the tgfc bit when the tgfc bit in tsr is set to 1 in channels 0 and 3. in channels 1, 2, 4, and 5, bit 2 is reserved. it is always read as 0 and cannot be modified. 0: interrupt requests (tgic) by tgfc bit disabled 1: interrupt requests (tgic) by tgfc bit enabled 1 tgieb 0 r/w tgr interrupt enable b enables or disables interrupt requests (tgib) by the tgfb bit when the tgfb bit in tsr is set to 1. 0: interrupt requests (tgib) by tgfb bit disabled 1: interrupt requests (tgib) by tgfb bit enabled 0 tgiea 0 r/w tgr interrupt enable a enables or disables interrupt requests (tgia) by the tgfa bit when the tgfa bit in tsr is set to 1. 0: interrupt requests (tgia) by tgfa bit disabled 1: interrupt requests (tgia) by tgfa bit enabled section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 192 of 566 rej09b0211-0700 10.3.5 timer status register (tsr) the tsr registers are 8-bit readable /writable registers that indicate the status of each channel. the tpu has six tsr registers, one for each channel. bit bit name initial value r/w description 7 tcfd 1 r count direction flag status flag that shows the direction in which tcnt counts in channels 1, 2, 4, and 5. in channels 0 and 3, bit 7 is reserved. it is always read as 1 and cannot be modified. 0: tcnt counts down 1: tcnt counts up 6 ? 1 ? reserved this bit is always read as 1 and cannot be modified. 5 tcfu 0 r/(w) underflow flag status flag that indicates that tcnt underflow has occurred when channels 1, 2, 4, and 5 are set to phase counting mode. only 0 can be written, for flag clearing. in channels 0 and 3, bit 5 is reserved. it is always read as 0 and cannot be modified. [setting condition] ? when the tcnt value underflows (changes from h'0000 to h'ffff) [clearing condition] ? when 0 is written to tcfu after reading tcfu = 1 4 tcfv 0 r/(w) overflow flag status flag that indicates that tcnt overflow has occurred. only 0 can be written, for flag clearing. [setting condition] ? when the tcnt value overflows (changes from h'ffff to h'0000 ) [clearing condition] ? when 0 is written to tcfv after reading tcfv = 1 section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 193 of 566 rej09b0211-0700 bit bit name initial value r/w description 3 tgfd 0 r/(w) input capture/output compare flag d status flag that indicates the occurrence of tgrd input capture or compare match in channels 0 and 3. only 0 can be written, for flag clearing. in channels 1, 2, 4, and 5, bit 3 is reserved. it is always read as 0 and cannot be modified. [setting conditions] ? when tcnt = tgrd and tgrd is functioning as output compare register ? when tcnt value is transferred to tgrd by input capture signal and tgrd is functioning as input capture register [clearing conditions] ? when dtc is activated by tgid interrupt and the disel bit of mrb in dtc is 0 ? when 0 is written to tgfd after reading tgfd = 1 2 tgfc 0 r/(w) input capture/output compare flag c status flag that indicates the occurrence of tgrc input capture or compare match in channels 0 and 3. only 0 can be written, for flag clearing. in channels 1, 2, 4, and 5, bit 2 is reserved. it is always read as 0 and cannot be modified. [setting conditions] ? when tcnt = tgrc and tgrc is functioning as output compare register ? when tcnt value is transferred to tgrc by input capture signal and tgrc is functioning as input capture register [clearing conditions] ? when dtc is activated by tgic interrupt and the disel bit of mrb in dtc is 0 ? when 0 is written to tgfc after reading tgfc = 1 section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 194 of 566 rej09b0211-0700 bit bit name initial value r/w description 1 tgfb 0 r/(w) input capture/output compare flag b status flag that indicates the occurrence of tgrb input capture or compare match. only 0 can be written, for flag clearing. [setting conditions] ? when tcnt = tgrb and tgrb is functioning as output compare register ? when tcnt value is transferred to tgrb by input capture signal and tgrb is functioning as input capture register [clearing conditions] ? when dtc is activated by tgib interrupt and the disel bit of mrb in dtc is 0 ? when 0 is written to tgfb after reading tgfb = 1 0 tgfa 0 r/(w) input capture/output compare flag a status flag that indicates the occurrence of tgra input capture or compare match. only 0 can be written, for flag clearing. [setting conditions] ? when tcnt = tgra and tgra is functioning as output compare register ? when tcnt value is transferred to tgra by input capture signal and tgra is functioning as input capture register [clearing conditions] ? when dtc is activated by tgia interrupt and the disel bit of mrb in dtc is 0 ? when 0 is written to tgfa after reading tgfa = 1 section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 195 of 566 rej09b0211-0700 10.3.6 timer counter (tcnt) the tcnt registers are 16-bit readable/writable counters. the tpu has six tcnt counters, one for each channel. the tcnt counters are initialized to h'0000 by a reset, and in hardware standby mode. the tcnt counters cannot be accessed in 8-bit un its; they must always be accessed as a 16-bit unit. 10.3.7 timer general register (tgr) the tgr registers are dual function 16-bit readable/writable registers, functioning as either output compare or input capture register s. the tpu has 16 tgr registers, four each for channels 0 and 3 and two each for channels 1, 2, 4, and 5. tg rc and tgrd for channels 0 and 3 can also be designated for operation as buffer registers. the tgr registers cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. tgr buffer register combinations are tgra? tgrc and tgrb?tgrd. 10.3.8 timer start register (tstr) tstr is an 8-bit readable/writable register that selects operation/stoppage for channels 0 to 5. when setting the operating mode in tmdr or setting the count clock in tcr, first stop the tcnt counter. bit bit name initial value r/w description 7, 6 ? all 0 ? reserved only 0 should be written to these bits. 5 4 3 2 1 0 cst5 cst4 cst3 cst2 cst1 cst0 0 r/w counter start 0 to 5 these bits select operation or stoppage for tcnt. if 0 is written to the cst bit during operation with the tioc pin designated for output, the counter stops but the tioc pin output compare output level is retained. if tior is written to when the cst bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: tcnt_0 to tcnt_5 count operation is stopped 1: tcnt_0 to tcnt_5 performs count operation section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 196 of 566 rej09b0211-0700 10.3.9 timer synchro register (tsyr) tsyr is an 8-bit readable/writable register that selects independent operation or synchronous operation for the channel 0 to 5 tcnt counters. a channel performs synchronous operation when the corresponding bit in tsyr is set to 1. bit bit name initial value r/w description 7, 6 ? all 0 r/w reserved only 0 should be written to these bits. 5 4 3 2 1 0 sync5 sync4 sync3 sync2 sync1 sync0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w timer synchro 0 to 5 these bits are used to select whether operation is independent of or synchronized with other channels. when synchronous operation is selected, the tcnt synchronous presetting of multiple channels, and synchronous clearing by counter clearing on another channel, are possible. to set synchronous operation, the sync bits for at least two channels must be set to 1. to set synchronous clearing, in addition to the sync bit, the tcnt clearing source must also be set by means of bits cclr0 to cclr2 in tcr. 0: tcnt_0 to tcnt_5 operates independently (tcnt presetting /clearing is unrelated to other channels) 1: tcnt_0 to tcnt_5 performs synchronous operation tcnt synchronous presetting/synchronous clearing is possible section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 197 of 566 rej09b0211-0700 10.4 operation 10.4.1 basic functions each channel has a tcnt and tgr register. tcnt performs up-counting, and is also capable of free-running operation, synchronous counting, and external event counting. each tgr can be used as an input capture register or output compare register. counter operation: when one of bits cst0 to cst5 is set to 1 in tstr, the tcnt counter for the corresponding channel begins counting. tcnt can operate as a free-running counter, periodic counter, for example. 1. example of count operation setting procedure figure 10.2 shows an example of th e count operation setting procedure. operation selection select counter clock periodic counter select counter clearin g source select output compare re g ister set period free-runnin g counter start count operation section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 198 of 566 rej09b0211-0700 2. free-running count operation and periodic count operation immediately after a reset, the tpu?s tcnt counters are all designated as free-running counters. when the relevant bit in tstr is set to 1 the corresponding tcnt counter starts up- count operation as a free-running counter. when tcnt overflows (from h'ffff to h'0000), the tcfv bit in tsr is set to 1. if the value of the corresponding tciev bit in tier is 1 at this point, the tpu requests an interrupt. af ter overflow, tcnt starts counting up again from h'0000. figure 10.3 illustrates free-running counter operation. tcnt value h'ffff h'0000 cst bit tcfv time figure 10.3 free-running counter operation when compare match is selected as the tcnt clearing source, the tcnt counter for the relevant channel performs periodic count operation. the tgr register for setting the period is designated as an output compare register, and counter clearing by compare match is selected by means of bits cclr0 to cclr2 in tcr. afte r the settings have been made, tcnt starts up-count operation as a periodic counter when the corresponding bit in tstr is set to 1. when the count value matches the value in tgr, the tgf bit in tsr is set to 1 and tcnt is cleared to h'0000. if the value of the corresponding tgie bit in tier is 1 at this point, the tpu requests an interrupt. after a compare match, tcnt starts counting up again from h'0000. figure 10.4 illustrates peri odic counter operation. section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 199 of 566 rej09b0211-0700 tcnt value tgr h'0000 cst bit tgf time counter cleared by tgr compare match fla g cleared by software or dtc activation figure 10.4 period ic counter operation waveform output by compare match: the tpu can perform 0, 1, or toggle output from the corresponding output pin using compare match. 1. example of setting procedure for waveform output by compare match figure 10.5 shows an example of the setting procedure for waveform output by compare match. output selection select waveform output mode set output timin g start count operation section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 200 of 566 rej09b0211-0700 2. examples of waveform output operation figure 10.6 shows an example of 0 output/1 output. in this example tcnt has been designated as a free-running counter, a nd settings have been made such that 1 is output by compare match a, and 0 is output by compare match b. when the set level and the pin level coincide, the pin level does not change. tcnt value h'ffff h'0000 tioca tiocb time tgra tgrb no chan g e no chan g e no chan g e no chan g e 1 output 0 output figure 10.6 example of 0 output/1 output operation figure 10.7 shows an example of toggle output. in this example, tcnt has been designated as a periodic counter (with counter clearing on compare match b), and settings have been made such that the output is toggled by both compare match a and compare match b. tcnt value h'ffff h'0000 tiocb tioca time tgrb tgra to gg le output to gg le output counter cleared by tgrb compare match figure 10.7 example of toggle output operation section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 201 of 566 rej09b0211-0700 input capture function: the tcnt value can be transferred to tgr on detection of the tioc pin input edge. rising edge, falling edge, or both edges can be select ed as the detected edge. for channels 0, 1, 3, and 4, it is also possible to specify another channel's counter input clock or compare match signal as the input capture source. note: when another channel's counter input clock is used as the input capture input for channels 0 and 3, /1 should not be selected as the counter input clock used for input capture input. input capture will not be generated if /1 is selected. 1. example of input captur e operation setting procedure figure 10.8 shows an example of the input capture operation setting procedure. input selection select input capture input start count desi g nate tgr as an input capture re g ister by means of tior, and select risin g ed g e, fallin g ed g e, or both ed g es as the input capture source and input si g nal ed g e. set the cst bit in tstr to 1 to start the count operation. [1] [2] [1] [2] figure 10.8 example of input capture operation setting procedure section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 202 of 566 rej09b0211-0700 2. example of input capture operation figure 10.9 shows an example of input capture operation. in this example both rising and falling edges have been selected as the tioca pin input capture input edge, the falling edge has been se lected as the tiocb pi n input capture input edge, and counter clearing by tgrb input capture has been designated for tcnt. tcnt value h'0180 h'0000 tioca tgra h'0010 h'0005 counter cleared by tiocb input (fallin g ed g e) h'0160 h'0005 h'0160 h'0010 tgrb h'0180 tiocb time figure 10.9 example of input capture operation section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 203 of 566 rej09b0211-0700 10.4.2 synchronous operation in synchronous operation, the values in a number of tcnt counters can be rewritten simultaneously (synchronous presetting). also, a number of tcnt counters can be cleared simultaneously by making the appropriate setting in tcr (synchronous clearing). synchronous operation enables tgr to be incremented with respect to a single time base. channels 0 to 5 can all be designated for synchronous operation. example of synchronous operation setting procedure: figure 10.10 shows an example of the synchronous operation setting procedure. no yes synchronous operation selection set synchronous operation synchronous presettin g set tcnt section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 204 of 566 rej09b0211-0700 example of synchronous operation: figure 10.11 shows an example of synchronous operation. in this example, synchronous operation and pwm m ode 1 have been designated for channels 0 to 2, tgrb_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source. three-phase pwm waveforms are output from pins tioc0a, tioc1a, and tioc2a. at this time, synchronous presetting, and synchron ous clearing by tgrb_0 compare match, are performed for channel 0 to 2 tcnt counters, and the data set in tgrb_0 is used as the pwm cycle. for details of pwm modes, see section 10.4.5, pwm modes. tcnt_0 to tcnt_2 values h'0000 tioca_0 tioca_1 tgrb_0 synchronous clearin g by tgrb_0 compare match tgra_2 tgra_1 tgrb_2 tgra_0 tgrb_1 tioca_2 time figure 10.11 example of synchronous operation section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 205 of 566 rej09b0211-0700 10.4.3 buffer operation buffer operation, provided for channels 0 and 3, enables tgrc and tgrd to be used as buffer registers. buffer operation differs depending on whether tgr has been designated as an input capture register or as a compare match register. table 10.28 shows the register combinations used in buffer operation. table 10.28 register combinat ions in buffer operation channel timer general re gister buffer register 0 tgra_0 tgrc_0 tgrb_0 tgrd_0 3 tgra_3 tgrc_3 tgrb_3 tgrd_3 ? when tgr is an output compare register when a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. this operation is illustrated in figure 10.12. buffer re g ister timer g eneral re g ister tcnt comparator compare match si g nal figure 10.12 compare match buffer operation section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 206 of 566 rej09b0211-0700 ? when tgr is an input capture register when input capture occurs, the value in tcnt is transferred to tgr and the value previously held in the timer general register is transferred to the buffer register. this operation is illustrated in figure 10.13. buffer re g ister timer g eneral re g ister tcnt input capture si g nal figure 10.13 input capture buffer operation example of buffer operati on setting procedure: figure 10.14 shows an example of the buffer operation setting procedure. buffer operation select tgr function set buffer operation start count section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 207 of 566 rej09b0211-0700 examples of buffer operation 1. when tgr is an output compare register figure 10.15 shows an operation example in which pwm mode 1 has been designated for channel 0, and buffer operation has been desi gnated for tgra and tgrc. the settings used in this example are tcnt clearing by compare match b, 1 output at compare match a, and 0 output at compare match b. as buffer operation has been se t, when compare match a occurs the output changes and the value in buffer register tgrc is simultaneously transferred to timer general register tgra. this operation is repeated each tim e that compare match a occurs. for details of pwm modes, see section 10.4.5, pwm modes. tcnt value tgrb_0 h'0000 tgrc_0 tgra_0 h'0200 h'0520 tioca h'0200 h'0450 h'0520 h'0450 tgra_0 h'0450 h'0200 transfer time figure 10.15 example of buffer operation (1) section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 208 of 566 rej09b0211-0700 2. when tgr is an input capture register figure 10.16 shows an operation example in which tgra has been designated as an input capture register, and buffer operation has been designated for tgra and tgrc. counter clearing by tgra input capture has been set for tcnt, and both rising and falling edges have been selected as the tioca pin input capture input edge. as buffer operation has been set, when the tcnt value is stored in tgra upon the occurrence of input capture a, the value previously stored in tgra is simultaneously transferred to tgrc. tcnt value h'09fb h'0000 tgrc time h'0532 tioca tgra h'0f07 h'0532 h'0f07 h'0532 h'0f07 h'09fb figure 10.16 example of buffer operation (2) section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 209 of 566 rej09b0211-0700 10.4.4 cascaded operation in cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. this function works by counting the channel 1 (channel 4) counter clock upon overflow/underflow of tcnt_2 (tcnt_5) as set in bits tpsc0 to tpsc2 in tcr. underflow occurs only when the lower 16-bit tcnt is in phase-counting mode. table 10.29 shows the register combinations used in cascaded operation. note: when phase counting mode is set for channel 1 or 4, the counter clock setting is invalid and the counters operates independently in phase counting mode. table 10.29 cascaded combinations combination upper 16 bits lower 16 bits channels 1 and 2 tcnt_1 tcnt_2 channels 4 and 5 tcnt_4 tcnt_5 example of cascaded opera tion setting procedure: figure 10.17 shows an example of the setting procedure for cascaded operation. cascaded operation set cascadin g start count section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 210 of 566 rej09b0211-0700 examples of cascaded operation: figure 10.18 illustrates the operation when tcnt_2 overflow/underflow counting has been set for tcnt_1, when tgra_1 and tgra_2 have been designated as input capture registers, and when tioc pin rising edge has been selected. when a rising edge is input to the tioca1 and tioca2 pins simultaneously, the upper 16 bits of the 32-bit data are transferred to tgra_1, and the lower 16 bits to tgra_2. tcnt_2 clock tcnt_2 h'ffff h'0000 h'0001 tioca1, tioca2 tgra_1 h'03a2 tgra_2 h'0000 tcnt_1 clock tcnt_1 h'03a1 h'03a2 figure 10.18 example of cascaded operation (1) figure 10.19 illustrates the operation when tcnt_2 overflow/underflow counting has been set for tcnt_1 and phase counting mode has been designated for channel 2. tcnt_1 is incremented by tcnt_2 overflow and decremented by tcnt_2 underflow. tclka tcnt_2 fffd tcnt_1 0001 tclkb fffe ffff 0000 0001 0002 0001 0000 ffff 0000 0000 figure 10.19 example of cascaded operation (2) section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 211 of 566 rej09b0211-0700 10.4.5 pwm modes in pwm mode, pwm waveforms are output from the output pins. the output level can be selected as 0, 1, or toggle output in response to a compare match of each tgr. tgr registers settings can be used to output a pwm waveform in the range of 0% to 100% duty. designating tgr compare match as the counter clearing source enables the period to be set in that register. all channels can be designated for pw m mode independently. synchronous operation is also possible. there are two pwm modes, as described below. ? pwm mode 1 pwm output is generated from the tioca and tiocc pins by pairing tgra with tgrb and tgrc with tgrd. the output specified by bits ioa0 to ioa3 and ioc0 to ioc3 in tior is output from the tioca and tiocc pins at compare matches a and c, and the output specified by bits iob0 to iob3 and iod0 to iod3 in tior is output at compare matches b and d. the initial output value is the value set in tgra or tgrc. if the set values of paired tgrs are identical, the output value does not change when a compare match occurs. in pwm mode 1, a maximum 8-phase pwm output is possible. ? pwm mode 2 pwm output is generated using one tgr as the cycle register and the others as duty registers. the output specified in tior is performed by means of compare matches. upon counter clearing by a synchronization register compare match, the output value of each pin is the initial value set in tior. if the set values of the cy cle and duty registers are identical, the output value does not change when a compare match occurs. in pwm mode 2, a maximum 15-phase pwm output is possible in combination use with synchronous operation. the correspondence between pwm output pins and registers is shown in table 10.30. section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 212 of 566 rej09b0211-0700 table 10.30 pwm output registers and output pins output pins channel registers pwm mode 1 pwm mode 2 0 tgra_0 tioca0 tioca0 tgrb_0 tiocb0 tgrc_0 tiocc0 tiocc0 tgrd_0 tiocd0 1 tgra_1 tioca1 tioca1 tgrb_1 tiocb1 2 tgra_2 tioca2 tioca2 tgrb_2 tiocb2 3 tgra_3 tioca3 tioca3 tgrb_3 tiocb3 tgrc_3 tiocc3 tiocc3 tgrd_3 tiocd3 4 tgr4a_4 tioca4 tioca4 tgr4b_4 tiocb4 5 tgra_5 tioca5 tioca5 tgrb_5 tiocb5 note: in pwm mode 2, pwm output is not possible for the tgr register in which the period is set. section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 213 of 566 rej09b0211-0700 example of pwm mode setting procedure: figure 10.20 shows an example of the pwm mode setting procedure. pwm mode select counter clock select counter clearin g source select waveform output level set tgr set pwm mode start count section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 214 of 566 rej09b0211-0700 tcnt value tgra h'0000 tioca time tgrb counter cleared by tgra compare match figure 10.21 example of pwm mode operation (1) figure 10.22 shows an example of pwm mode 2 operation. in this example, synchronous operation is designated for channels 0 and 1, tgrb_1 compare match is set as the tcnt clearing source, and 0 is set for the initial output value and 1 for the output value of the other tgr registers (tgra_0 to tgrd_0, tgra_1), outputting a 5-phase pwm waveform. in this case, the value set in tgrb_1 is used as th e cycle, and the values set in the other tgrs are used as the duty levels. tcnt value tgrb_1 h'0000 tioca0 counter cleared by tgrb_1 compare match time tgra_1 tgrd_0 tgrc_0 tgrb_0 tgra_0 tiocb0 tiocc0 tiocd0 tioca1 figure 10.22 example of pwm mode operation (2) section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 215 of 566 rej09b0211-0700 figure 10.23 shows examples of pwm waveform output with 0% duty and 100% duty in pwm mode. tcnt value tgra h'0000 tioca time tgrb 0% duty tgrb rewritten tgrb rewritten tgrb rewritten tcnt value tgra h'0000 tioca time tgrb 100% duty tgrb rewritten tgrb rewritten tgrb rewritten output does not chan g e when cycle re g ister and duty re g ister compare matches occur simultaneously tcnt value tgra h'0000 tioca time tgrb 100% duty tgrb rewritten tgrb rewritten tgrb rewritten output does not chan g e when cycle re g ister and duty re g ister compare matches occur simultaneously 0% duty figure 10.23 example of pwm mode operation (3) section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 216 of 566 rej09b0211-0700 10.4.6 phase counting mode in phase counting mode, the phase difference between two external clock inputs is detected and tcnt is incremented/decr emented accordingly. this mode can be set for channels 1, 2, 4, and 5. when phase counting mode is set, an external cl ock is selected as the counter input clock and tcnt operates as an up/down-counter regardless of the setting of bits tpsc0 to tpsc2 and bits ckeg0 and ckeg1 in tcr. however, the functions of bits cclr0 and cclr1 in tcr, and of tior, tier, and tgr, are valid, and input capture/compare match and interrupt functions can be used. this can be used for two-phase encoder pulse input. if overflow occurs when tcnt is counting up, the tcfv flag in tsr is set; if underflow occurs when tcnt is counting down, the tcfu flag is set. the tcfd bit in tsr is the count direction flag. reading the tcfd flag reveals whether tcnt is counting up or down. table 10.31 shows the correspondence between external clock pins and channels. table 10.31 phase counting mode clock input pins external clock pins channels a-phase b-phase when channel 1 or 5 is set to phase counting mode tclka tclkb when channel 2 or 4 is set to phase counting mode tclkc tclkd section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 217 of 566 rej09b0211-0700 example of phase counting mode setting procedure: figure 10.24 shows an example of the phase counting mode setting procedure. phase countin g mode select phase countin g mode start count section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 218 of 566 rej09b0211-0700 table 10.32 up/down-count conditions in phase counting mode 1 tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) operation high level up-count low level low level high level high level down-count low level high level low level legend: : rising edge : falling edge 2. phase counting mode 2 figure 10.26 shows an example of phase counting mode 2 operation, and table 10.33 summarizes the tcnt up/down-count conditions. time down-count up-count tcnt value tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) figure 10.26 example of phase counting mode 2 operation section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 219 of 566 rej09b0211-0700 table 10.33 up/down-count conditions in phase counting mode 2 tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) operation high level don?t care low level low level high level up-count high level don?t care low level high level low level down-count legend: : rising edge : falling edge 3. phase counting mode 3 figure 10.27 shows an example of phase counting mode 3 operation, and table 10.34 summarizes the tcnt up/down-count conditions. time up-count down-count tcnt value tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) figure 10.27 example of phase counting mode 3 operation section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 220 of 566 rej09b0211-0700 table 10.34 up/down-count conditions in phase counting mode 3 tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) operation high level don?t care low level low level high level up-count high level down-count low level don?t care high level low level legend: : rising edge : falling edge 4. phase counting mode 4 figure 10.28 shows an example of phase counting mode 4 operation, and table 10.35 summarizes the tcnt up/down-count conditions. time up-count down-count tcnt value tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) figure 10.28 example of phase counting mode 4 operation section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 221 of 566 rej09b0211-0700 table 10.35 up/down-count conditions in phase counting mode 4 tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) operation high level up-count low level low level don?t care high level high level down-count low level high level don?t care low level legend: : rising edge : falling edge phase counting mode application example: figure 10.29 shows an example in which channel 1 is in phase counting mode, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect position or speed. channel 1 is set to phase counting mode 1, and the encoder pulse a-phase and b-phase are input to tclka and tclkb. channel 0 operates with tcnt counter clearing by tgrc_0 compare match; tgra_0 and tgrc_0 are used for the compare match function a nd are set with the speed control period and position control period. tgrb_0 is used for input capture, with tgrb_0 and tgrd_0 operating in buffer mode. the channel 1 counter input clock is designated as the tgrb_0 input capture source, and the pulse widths of 2-phase encoder 4-multiplication pulses are detected. tgra_1 and tgrb_1 for channel 1 are designated for input capture, and channel 0 tgra_0 and tgrc_0 compare matches are selected as the input capture source and store the up/down-counter values for the control periods. this procedure enables the accurate detection of position and speed. section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 222 of 566 rej09b0211-0700 tcnt_1 tcnt_0 channel 1 tgra_1 (speed period capture) tgra_0 (speed control period) tgrb_1 (speed period capture) tgrc_0 (position control period) tgrb_0 (pulse width capture) tgrd_0 (buffer operation) channel 0 tclka tclkb ed g e detection circuit + ? + ? figure 10.29 phase counting mode application example section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 223 of 566 rej09b0211-0700 10.5 interrupts there are three kinds of tpu interrupt source; tgr input capture/compare match, tcnt overflow, and tcnt underflow. each interrupt source has its own status flag and enable/disabled bit, allowing the generation of interrupt request signals to be enabled or disabled individually. when an interrupt request is generated, the corresponding status flag in tsr is set to 1. if the corresponding enable/disable bit in tier is set to 1 at this time, an interrupt is requested. the interrupt request is cleared by cl earing the status flag to 0. relative channel priorities can be changed by the interrupt controller, however the priority order within a channel is fixed. for details, see section 5, interrupt controller. table 10.36 lists the tpu interrupt sources. section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 224 of 566 rej09b0211-0700 table 10.36 tpu interrupts channel name interrupt source interrupt flag dtc activation 0 tgia_0 tgra_0 input capture/compare match tgfa_0 possible tgib_0 tgrb_0 input capture/compare match tgfb_0 possible tgic_0 tgrc_0 input capture/compare match tgfc_0 possible tgid_0 tgrd_0 input capture/compare match tgfd_0 possible tciv_0 tcnt_0 overflow tcfv_0 not possible 1 tgia_1 tgra_1 input capture/compare match tgfa_1 possible tgib_1 tgrb_1 input capture/compare match tgfb_1 possible tciv_1 tcnt_1 overflow tcfv_1 not possible tciu_1 tcnt_1 underflow tcfu_1 not possible 2 tgia_2 tgra_2 input capture/compare match tgfa_2 possible tgib_2 tgrb_2 input capture/compare match tgfb_2 possible tciv_2 tcnt_2 overflow tcfv_2 not possible tciu_2 tcnt_2 underflow tcfu_2 not possible 3 tgia_3 tgra_3 input capture/compare match tgfa_3 possible tgib_3 tgrb_3 input capture/compare match tgfb_3 possible tgic_3 tgrc_3 input capture/compare match tgfc_3 possible tgid_3 tgrd_3 input capture/compare match tgfd_3 possible tciv_3 tcnt_3 overflow tcfv_3 not possible 4 tgia_4 tgra_4 input capture/compare match tgfa_4 possible tgib_4 tgrb_4 input capture/compare match tgfb_4 possible tciv_4 tcnt_4 overflow tcfv_4 not possible tciu_4 tcnt_4 underflow tcfu_4 not possible 5 tgia_5 tgra_5 input capture/compare match tgfa_5 possible tgib_5 tgrb_5 input capture/compare match tgfb_5 possible tciv_5 tcnt_5 overflow tcfv_5 not possible tciu_5 tcnt_5 underflow tcfu_5 not possible note: this table shows the initial state immediately after a reset. the relative channel priorities can be changed by the interrupt controller. section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 225 of 566 rej09b0211-0700 input capture/compare match interrupt: an interrupt is requested if the tgie bit in tier is set to 1 when the tgf flag in tsr is set to 1 by the occurrence of a tgr input capture/compare match on a particular channel. the interrupt reques t is cleared by clearing the tgf flag to 0. the tpu has 16 input capture/compare match interrupts, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5. overflow interrupt: an interrupt is requested if the tciev bit in tier is set to 1 when the tcfv flag in tsr is set to 1 by the occurren ce of tcnt overflow on a channel. the interrupt request is cleared by clearing the tcfv flag to 0. the tpu has six overflow interrupts, one for each channel. underflow interrupt: an interrupt is requested if the tcie u bit in tier is set to 1 when the tcfu flag in tsr is set to 1 by the occurrence of tcnt underflow on a channel. the interrupt request is cleared by clearing the tcfu flag to 0. the tpu has four underflow interrupts, one each for channels 1, 2, 4, and 5. 10.6 dtc activation the dtc can be activated by the tgr input capture/compare match interrupt for a channel. for details, see section 8, data transfer controller (dtc). a total of 16 tpu input capture/compare match interrupts can be used as dtc activation sources, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5. 10.7 a/d converter activation the a/d converter can be activated by the tgra input capture/compare match for a channel. if the ttge bit in tier is set to 1 when the tgfa flag in tsr is set to 1 by the occurrence of a tgra input capture/compare match on a particular channel, a request to begin a/d conversion is sent to the a/d converter. if the tpu conversion start trigger has been selected on the a/d converter side at this time, a/d conversion is begun. in the tpu, a total of six tgra input capture/compare match interrupts can be used as a/d converter conversion start sources, one for each channel. section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 226 of 566 rej09b0211-0700 10.8 operation timing 10.8.1 input/output timing tcnt count timing: figure 10.30 shows tcnt count timing in internal clock operation, and figure 10.31 shows tcnt count timing in external clock operation. tcnt tcnt input clock internal clock n ? 1n n + 1n + 2 fallin g ed g e risin g ed g e figure 10.30 count timing in internal clock operation tcnt tcnt input clock external clock n ? 1n n + 1n + 2 fallin g ed g e risin g ed g e fallin g ed g e figure 10.31 count timing in external clock operation output compare output timing: a compare match signal is generated in the final state in which tcnt and tgr match (the point at which the count value matched by tcnt is updated). when a compare match signal is generated, the output value set in tior is output at the output compare output pin. after a match between tcnt and tgr, the compare match signal is not generated until the tcnt input clock is generated. figure 10.32 shows output compare output timing. section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 227 of 566 rej09b0211-0700 tgr tcnt tcnt input clock n nn + 1 compare match si g nal tioc pin figure 10.32 output compare output timing input capture signal timing: figure 10.33 shows input capture signal timing. tcnt input capture input nn + 1 n + 2 n n + 2 tgr input capture si g nal figure 10.33 input capture input signal timing section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 228 of 566 rej09b0211-0700 timing for counter clearing by compare match/input capture: figure 10.34 shows the timing when counter clearing on compare match is specified, and figure 10.35 shows the timing when counter clearing on i nput capture is specified. tcnt counter clear si g nal compare match si g nal tgr n n h'0000 figure 10.34 counter clea r timing (compare match) tcnt counter clear si g nal input capture si g nal tgr n h'0000 n figure 10.35 counter clear timing (input capture) section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 229 of 566 rej09b0211-0700 buffer operation timing: figures 10.36 and 10.37 show the timing in buffer operation. tgra, tgrb compare match si g nal tcnt tgrc, tgrd nn n nn + 1 figure 10.36 buffer operati on timing (compare match) tgra, tgrb tcnt input capture si g nal tgrc, tgrd n n nn + 1 n n n + 1 figure 10.37 buffer operation timing (input capture) section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 230 of 566 rej09b0211-0700 10.8.2 interrupt signal timing tgf flag setting timing in case of compare match: figure 10.38 shows the timing for setting of the tgf flag in tsr on compare match, and tgi interrupt request signal timing. tgr tcnt tcnt input clock n nn + 1 compare match si g nal tgf fla g tgi interrupt figure 10.38 tgi interrupt timing (compare match) tgf flag setting timing in case of input capture: figure 10.39 shows the timing for setting of the tgf flag in tsr on input capture, and tgi interrupt request signal timing. tgr tcnt input capture si g nal n n tgf fla g tgi interrupt figure 10.39 tgi interrupt timing (input capture) section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 231 of 566 rej09b0211-0700 tcfv flag/tcfu flag setting timing: figure 10.40 shows the timing for setting of the tcfv flag in tsr on overflow, and tciv interrupt request signal timing. figure 10.41 shows the timing for setting of the tcfu flag in tsr on underflow, and tciu interrupt request signal timing. overflow si g nal tcnt (overflow) tcnt input clock h'ffff h'0000 tcfv fla g tciv interrupt figure 10.40 tciv interrupt setting timing section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 232 of 566 rej09b0211-0700 underflow si g nal tcnt (underflow) tcnt input clock h'0000 h'ffff tcfu fla g tciu interrupt figure 10.41 tciu interrupt setting timing status flag clearing timing: after a status flag is read as 1 by the cpu, it is cleared by writing 0 to it. when the dtc is activated, the flag is cleared automatically. figure 10.42 shows the timing for status flag clearing by the cpu, and figure 10.43 shows the timing for status flag clearing by the dtc. status fla g write si g nal address tsr address interrupt request si g nal tsr write cycle t 1 t 2 figure 10.42 timing for status flag clearing by cpu section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 233 of 566 rej09b0211-0700 interrupt request si g nal status fla g address source address dtc read cycle t 1 t 2 destination address t 1 t 2 dtc write cycle figure 10.43 timing for status flag clearing by dtc activation section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 234 of 566 rej09b0211-0700 10.9 usage notes 10.9.1 module stop mode setting tpu operation can be disabled or enabled using the module st op control register. the initial setting is for tpu operation to be halted. regi ster access is enabled by clearing module stop mode. for details, refer to section 20, power-down modes. 10.9.2 input clock restrictions the input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detec tion. the tpu will not operate properly at narrower pulse widths. in phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. figure 10.44 shows the input clock conditions in phase counting mode. overlap phase differ- ence phase differ- ence overlap tclka (tclkc) tclkb (tclkd) pulse width pulse width pulse width pulse width notes: phase difference and overlap pulse width : 1.5 states or more : 2.5 states or more figure 10.44 phase differe nce, overlap, and pulse width in phase counting mode 10.9.3 caution on period setting when counter clearing on compare match is set, tcnt is cleared in the final state in which it matches the tgr value (the point at which the count value matched by tcnt is updated). consequently, the actual counter frequency is given by the following formula: f = (n + 1) section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 235 of 566 rej09b0211-0700 where f : counter frequency : operating frequency n : tgr set value 10.9.4 contention between tcnt write and clear operations if the counter clear signal is generated in the t 2 state of a tcnt write cycle, tcnt clearing takes precedence and the tcnt write is not performed. figure 10.45 shows the timing in this case. counter clear si g nal write si g nal address tcnt address tcnt tcnt write cycle t 1 t 2 n h'0000 figure 10.45 contention between tcnt write and clear operations section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 236 of 566 rej09b0211-0700 10.9.5 contention between tcnt write and increment operations if incrementing occurs in the t 2 state of a tcnt write cycle, the tcnt write takes precedence and tcnt is not incremented. figure 10.46 shows the timing in this case. tcnt input clock write si g nal address tcnt address tcnt tcnt write cycle t 1 t 2 n m tcnt write data figure 10.46 contenti on between tcnt write and increment operations section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 237 of 566 rej09b0211-0700 10.9.6 contention between tg r write and compare match if a compare match occurs in the t 2 state of a tgr write cycle, the tgr write takes precedence and the compare match signal is inhibited. a compare match does not occur even if the previous value is written. figure 10.47 shows the timing in this case. compare match si g nal write si g nal address tgr address tcnt tgr write cycle t 1 t 2 n m tgr write data tgr n n + 1 prohibited figure 10.47 contention betw een tgr write and compare match section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 238 of 566 rej09b0211-0700 10.9.7 contention between buffer register write and compare match if a compare match occurs in the t 2 state of a tgr write cycle, the data that is transferred to tgr by the buffer operation will be that in the buffer prior to the write. figure 10.48 shows the timing in this case. compare match si g nal write si g nal address buffer re g ister address buffer re g ister tgr write cycle t 1 t 2 n tgr n m buffer re g ister write data figure 10.48 contention between buffer register write and compare match section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 239 of 566 rej09b0211-0700 10.9.8 contention between tgr read and input capture if an input capture signal is generated in the t 1 state of a tgr read cycle, the data that is read will be that in the buffer after input capture transfer. figure 10.49 shows the timing in this case. input capture si g nal read si g nal address tgr address tgr tgr read cycle t 1 t 2 m internal data bus x m figure 10.49 contention between tgr read and input capture section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 240 of 566 rej09b0211-0700 10.9.9 contention between tgr write and input capture if an input capture signal is generated in the t 2 state of a tgr write cycle, the input capture operation takes precedence and the write to tgr is not performed. figure 10.50 shows the timing in this case. input capture si g nal write si g nal address tcnt tgr write cycle t 1 t 2 m tgr m tgr address figure 10.50 contention between tgr write and input capture section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 241 of 566 rej09b0211-0700 10.9.10 contention between buffer register write and input capture if an input capture signal is generated in the t 2 state of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. figure 10.51 shows the timing in this case. input capture si g nal write si g nal address tcnt buffer re g ister write cycle t 1 t 2 n tgr n m m buffer re g ister buffer re g ister address figure 10.51 contention between buffer register write and input capture section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 242 of 566 rej09b0211-0700 10.9.11 contention between overflo w/underflow and counter clearing if overflow/underflow and counter clearing occur simultaneously, the tcfv/tcfu flag in tsr is not set and tcnt clearing takes precedence. figure 10.52 shows the operation timing when a tgr compare match is specified as the clearing source, and when h'ffff is set in tgr. counter clear si g nal tcnt input clock tcnt tgf prohibited tcfv h'ffff h'0000 figure 10.52 contention betw een overflow and counter clearing section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 243 of 566 rej09b0211-0700 10.9.12 contention between tcnt write and overf low/underflow if there is an up-count or down-count in the t 2 state of a tcnt write cycle, and overflow/underflow occurs, the tcnt write takes precedence and the tcfv/t cfu flag in tsr is not set. figure 10.53 shows the operation timing when there is contention between tcnt write and overflow. write si g nal address tcnt address tcnt tcnt write cycle t 1 t 2 h'ffff m tcnt write data tcfv fla g prohibited figure 10.53 contention be tween tcnt write and overflow 10.9.13 multiplexing of i/o pins in this lsi, the tclka input pin is multiplexed with the tiocc0 i/o pi n, the tclkb input pin with the tiocd0 i/o pin, the tclkc input pin with the tiocb1 i/o pin, and the tclkd input pin with the tiocb2 i/o pin. when an external clock is input, compare match output should not be performed from a multiplexed pin. 10.9.14 interrupts in module stop mode if module stop mode is entered when an interrupt has been requested, it will not be possible to clear the cpu interrupt source or the dtc activation source. interrupts should therefore be disabled before entering module stop mode. section 10 16-bit timer pulse unit (tpu) rev. 7.00 sep. 11, 2009 page 244 of 566 rej09b0211-0700 section 11 motor management timer (mmt) rev. 7.00 sep. 11, 2009 page 245 of 566 rej09b0211-0700 section 11 motor management timer (mmt) motor management timer (mmt) can output 6-phase pwm waveforms with non-overlap times. figure 11.1 shows a block diagram of the mmt. note: no mmt is implemented in the h8s/2614 and h8s/2616. 11.1 features ? triangular wave comparison type 6-phase pwm waveform output with non-overlap times ? non-overlap times generated by timer dead time counters ? toggle output synchronized with pwm period ? counter clearing on an external signal ? data transfer by dtc activation ? output-off functions ? pwm output halted by external signal ? pwm output halted when oscillation stops ? module stop mode can be set section 11 motor management timer (mmt) rev. 7.00 sep. 11, 2009 page 246 of 566 rej09b0211-0700 tgruu + 2td + td + 2td + td + 2td + td tgru tgrud tgrvu tgrv tgrvd tgrwu tgrw tgrwd tmdr pco pci puoa puob pvoa pvob pwoa pwob tcnt tsr tbru tbrv tbrw tpbr tpdr 2 + 2td tpdr compare match interrupt 2td compare match interrupt tddr tdcnt0 comparators control circuit ma g nitude comparators tcnt comparators le g end: tgr: tbr: tddr: tpdr: tpbr: td: timer g eneral re g ister timer buffer re g ister timer dead time data re g ister timer period data re g ister timer period buffer re g ister dead time tmdr: tcnr: tsr: tcnt: tdcnt: timer mode re g ister timer control re g ister timer status re g ister timer counter timer dead time counter figure 11.1 block diagram of mmt section 11 motor management timer (mmt) rev. 7.00 sep. 11, 2009 page 247 of 566 rej09b0211-0700 11.2 input/output pins table 11.1 shows the pin configuration of the mmt. table 11.1 pin configuration name i/o function pci input counter clear signal input pco output toggle output synchronized with pwm period puoa output pwmu phase output (positive phase) puob output pwmu phase output (negative phase) pvoa output pwmv phase output (positive phase) pvob output pwmv phase output (negative phase) pwoa output pwmw phase output (positive phase) pwob output pwmw phase output (negative phase) 11.3 register descriptions the mmt has the following registers. these registers are initialized on power-on reset or in hardware standby mode. they are not initialized in module stop mode or software standby mode. for details on register addresses, refer to appendix a, on-chip i/o register. ? timer mode register (tmdr) ? timer control register (tcnr) ? timer status register (tsr) ? timer counter (tcnt) ? timer buffer register u (tbru) ? timer buffer register v (tbrv) ? timer buffer register w (tbrw) ? timer general register uu (tgruu) ? timer general register vu (tgrvu) ? timer general register wu (tgrwu) ? timer general register u (tgru) ? timer general register v (tgrv) ? timer general register w (tgrw) ? timer general register ud (tgrud) ? timer general register vd (tgrvd) section 11 motor management timer (mmt) rev. 7.00 sep. 11, 2009 page 248 of 566 rej09b0211-0700 ? timer general register wd (tgrwd) ? timer dead time counter 0 (tdcnt0) ? timer dead time counter 1 (tdcnt1) ? timer dead time counter 2 (tdcnt2) ? timer dead time counter 3 (tdcnt3) ? timer dead time counter 4 (tdcnt4) ? timer dead time counter 5 (tdcnt5) ? timer dead time data register (tddr) ? timer period buffer register (tpbr) ? timer period data register (tpdr) ? mmt pin control register (mmtpc) 11.3.1 timer mode register (tmdr) the timer mode register (tmdr) sets the operating mode and selects the pwm output level. bit bit name initial value r/w description 7 to 4 ? all 0 ? reserved these bits are always read as 0 and should only be written with 0. 3 olsn 0 r/w output level select n selects the negative phase output level in the operating modes. 0: active level is low 1: active level is high 2 olsp 0 r/w output level select p selects the positive phase output level in the operating modes. 0: active level is low 1: active level is high 1 0 md1 md0 0 0 r/w r/w modes 0 to 3 these bits set the timer operating mode. 00: operation halted 01: operating mode 1 (transfer at crest) 10: operating mode 2 (transfer at trough) 11: operating mode 3 (transfer at crest and trough) section 11 motor management timer (mmt) rev. 7.00 sep. 11, 2009 page 249 of 566 rej09b0211-0700 11.3.2 timer control register (tcnr) the timer control register (tcnr) controls the enabling or disabling of interrupt requests, selects the enabling or disabling of regi ster access, selects counter opera tion or halting, and controls the enabling or disabling of toggle output synchronized with the pwm period. bit bit name initial value r/w description 7 ? 0 r/w reserved this bit is always read as 0. only 0 should be written to this bit. 6 cst 0 r/w timer counter start selects operation or halting of the timer counter (tcnt) and timer dead time counter (tdcnt). 0: tcnt and tdcnt operation is halted 1: tcnt and tdcnt perform count operations 5 rpro 0 r/w register protect enables or disables the reading of registers other than tsr, and enables or disables writes to registers other than tbru to tbrw, tpbr, and tsr. writes to tcnr itself are also disabled. note that reset input is necessary in order to write to these registers again. 0: register access enabled 1: register access disabled 4 to 2 ? all 0 ? reserved these bits are always read as 0. only 0 should be written to these bits. 1 tgien 0 r/w tgr interrupt enable n enables or disables interrupt requests by the tgfn bit when tgfn is set to 1 in the tsr register. 0: interrupt requests by tgfn bit disabled 1: interrupt requests by tgfn bit enabled 0 tgiem 0 r/w tgr interrupt enable m enables or disables interrupt requests by the tgfm bit when tgfm is set to 1 in the tsr register. 0: interrupt requests by tgfm bit disabled 1: interrupt requests by tgfm bit enabled section 11 motor management timer (mmt) rev. 7.00 sep. 11, 2009 page 250 of 566 rej09b0211-0700 11.3.3 timer status register (tsr) the timer status register holds status flags. bit bit name initial value r/w description 7 tcfg 1 r count direction flag status flag that indicates the count direction of the tcnt counter. 0: tcnt counts down 1: tcnt counts up 6 to 2 ? all 0 ? reserved these bits are always read as 0 and should only be written with 0. 1 tgfn 0 r/(w) * output compare flag n status flag that indicates a compare match between tcnt and 2td (td: tddr value). [setting condition] ? when tcnt = 2td [clearing condition] ? when 0 is written to tgfn after reading tgfn = 1 0 tgfm 0 r/(w) * output compare flag m status flag that indicates a compare match between tcnt and the tpdr register. [setting condition] ? when tcnt = tpdr [clearing condition] ? when 0 is written to tgfm after reading tgfm = 1 note: * can only be written with 0 for flag clearing. 11.3.4 timer counter (tcnt) the timer counter (tcnt) is a 16-bit counter. on ly 16-bit access can be used on tcnt; 8-bit access is not possible. section 11 motor management timer (mmt) rev. 7.00 sep. 11, 2009 page 251 of 566 rej09b0211-0700 11.3.5 timer buffer registers (tbr) the timer buffer registers (tbr) function as 16 -bit buffer registers. the mmt has three tbr registers; tbru, tbrv, and tbrw, each of wh ich have two addresses; a buffer operation address (shown first) and a free operation addre ss (shown second). a value written to the buffer operation address is transferred to the corresponding tgr at the timing set in bits md1 and md0 in the timer mode register (tmdr). a value set in the free operation address is transferred to the corresponding tgr immedi ately. only 16-bit access can be us ed on the tbr registers; 8-bit access is not possible. 11.3.6 timer general registers (tgr) the timer general registers (tgr) function as 16-bit compare registers. the mmt has nine tgr registers, that are compared w ith the tcnt counter in the op erating modes. only 16-bit access can be used on the tgr registers; 8-bit access is not possible. 11.3.7 timer dead time counters (tdcnt) the timer dead time counters (tdcnt) are 16-b it read-only counters. only 16-bit access can be used on the tdcnt counters; 8-bit access is not possible. 11.3.8 timer dead time data register (tddr) the timer dead time data register (tddr) is a 16-bit register that sets the positive phase and negative phase non-overlap time (dead time). only 16-bit access can be used on tddr; 8-bit access is not possible. 11.3.9 timer period buffer register (tpbr) the timer period buffer register (tpbr) is a 16-bit register that functions as a buffer register for the tpdr register. a value of 1/2 the pwm carrier period should be set as the tpbr value. the tpbr value is transferred to the tpdr register at the transfer timing set in the tmdr register. only 16-bit access can be used on tp br; 8-bit access is not possible. 11.3.10 timer period data register (tpdr) the timer period data register (tpdr) functions as a 16-bit compare register. in the operating modes, the tpdr register value is constantly compared with the tcnt counter value, and when they match the tcnt counter changes its count direction from up to down. only 16-bit access can be used on tpdr; 8-bit access is not possible. section 11 motor management timer (mmt) rev. 7.00 sep. 11, 2009 page 252 of 566 rej09b0211-0700 11.3.11 mmt pin control register (mmtpc) the mmtpc is an 8-bit readable/writable register that enables or disables usage of the mmt pins. bit bit name initial value r/w description 7 pwobe 0 r/w pwob enabled 0: pb7 pin is port i/o pin/tpu i/o pin 1: pb7 pin is pwob output pin of mmt 6 pwoae 0 r/w pwoa enabled 0: pb6 pin is port i/o pin/tpu i/o pin 1: pb6 pin is pwoa output pin of mmt 5 pvobe 0 r/w pvob enabled 0: pb5 pin is port i/o pin/tpu i/o pin 1: pb5 pin is pvob output pin of mmt 4 pvoae 0 r/w pvoa enabled 0: pb4 pin is port i/o pin/tpu i/o pin 1: pb4 pin is pvoa output pin of mmt 3 puobe 0 r/w puob enabled 0: pb3 pin is port i/o pin/tpu i/o pin 1: pb3 pin is puob output pin of mmt 2 puoae 0 r/w puoa enabled 0: pb2 pin is port i/o pin/tpu i/o pin 1: pb2 pin is puoa output pin of mmt 1 pcoe 0 r/w pco enabled 0: pb1 pin is port i/o pin/tpu i/o pin 1: pb1 pin is pco output pin of mmt 0 pcie 0 r/w pci enabled 0: pb0 pin is port i/o pin/tpu i/o pin 1: pb0 pin is pci output pin of mmt section 11 motor management timer (mmt) rev. 7.00 sep. 11, 2009 page 253 of 566 rej09b0211-0700 11.4 operation when the operating mode is selected, a 3-phase pwm waveform is output with a non-overlap relationship between the positive and negative phases. the puoa, puob, pvoa, pvob, pwoa, and pwob pins are pwm output pins, the pco pin functions as a toggle output synchronized with the pwm waveform, and the pci pin functions as the counter clear signal input. the tcnt counter performs up- and down-count operations, whereas the tdcnt counters perform up-count operations. section 11 motor management timer (mmt) rev. 7.00 sep. 11, 2009 page 254 of 566 rej09b0211-0700 11.4.1 sample setting procedure an example of the operating mode setting procedure is shown in figure 11.2. halt count operation set tcnt set tbr set pwm output level set operatin g mode set external pin functions start count operation section 11 motor management timer (mmt) rev. 7.00 sep. 11, 2009 page 255 of 566 rej09b0211-0700 figure 11.3 shows the sample mmt canceling procedure. mmt count operation set port set the pwm output port to g o hi g h. clear the enable bit in mmtpc to 0 to switch the mmt output pin to the port pin. clear the cst bit in tcnr to 0 to halt count operation. set external pin function halt count operation figure 11.3 mmt canceling procedure count operation: set 2td (td: value set in tddr) as the initial value of the tcnt counter when cst bit in tcnr is set to 0. when the cst bit is set to 1, tcnt counts up to {value set in tpbr + 2td}, and then starts counting down. when tcnt reaches 2td, it starts counting up again, and continues in this way. tcnt is constantly compared with tgru, tgrv, and tgrw. in addition, it is compared with tgruu, tgrvu, tgrwu, and tpdr when counting up, and with tgrud, tgrvd, tgrwd, and 2td when counting down. tdcnt0 to tdcnt5 are read-only counters. it is not necessary to set their initial values. tdcnt0, tdcnt2, and tdcnt4 start counting up at the falling edge of a positive phase compare match output when tcnt is counting down. when they become e qual to tddr they are cleared to 0 and halt. tdcnt1, tdcnt3, and tdcnt5 start counting up at the falling edge of a negative phase compare match output when tcnt is counting up. when they match tddr they are cleared to 0 and halt. tdcnt0 to tdcnt5 are compared with tddr only while a count operation is in progress. no count operation is performed when the tddr value is 0. figure 11.4 shows an example of the tcnt count operation. section 11 motor management timer (mmt) rev. 7.00 sep. 11, 2009 page 256 of 566 rej09b0211-0700 tcnt td h'ffff h'0000 tpdr tgruu tgru tgrud 2td td td 2td 2td 1/2 period (tpbr) figure 11.4 example of tcnt count operation register operation: in the operating modes, four buffer registers and ten compare registers are used. the registers that are consta ntly compared with the tcnt counter are tgru, tgrv, and tgrw. in addition, tgruu, tgrvu, tgrwu, and tpdr are compared with tcnt when tcnt is counting up, and tgrud, tgrvd, tgrwd are compared with tcnt when tcnt is counting down. the buffer register for tpdr is tpbr; the buffer register for tgruu, tgru, and tgrud is tbru; the buffer register for tgrvu, tgrv, and tgrvd is tbrv; and the buffer register for tgrwu, tgrw, and tgrwd is tbrw. to change compare register data, the new data should be written to the corresponding buffer register. the buffer registers can be read and written to at all times. data written to tpbr and the buffer operation addresses for tbru to tbrw is transferred at the timing specified by bits md1 and md0 in the timer mode register (tmdr). data written to the free operation addresses for tbru to tbrw is transferred immediately. after data transfer is completed, the relationship between the compare registers and buffer registers is as follows: tgru (tgrv, tgrw) value = tbru (tbrv, tbrw) value + td (td: value set in tddr) tgruu (tgrvu, tgrwu) value = tbru (tbrv, tbrw) value + 2td tgrud (tgrvd, tgrwd) value = tbru (tbrv, tbrw) value tpdr value = tpbr value + 2td the values of tbru to tbrw should always be set in the range h'0000 to h'ffff ? 2t d, and the value of tpbr should always be set in the range h'0000 to h'ffff ? 4td. section 11 motor management timer (mmt) rev. 7.00 sep. 11, 2009 page 257 of 566 rej09b0211-0700 figure 11.5 shows examples of counter and register operations. + + + compared durin g up-count compared durin g down-count compared durin g up-count compared durin g down-count up-count compare match down-count down-count compare match up-count constantly compared (tbr + 2td) (tbr + td) (tbr) tgruu tgrvu tgrwu tgru tgrv tgrw tgrud tgrvd tgrwd tpdr tcnt (1/2 period + 2td) tddr (td) tpbr (1/2 period) tddr tddr tdcnt (td) (td) tbru tbrv tbrw (tbr) (2td) 2 2 up-count compare match halt tcnt figure 11.5 examples of counter and register operations initial settings: in the operating modes, there are five registers that require initialization. make the following register settings before setting the operating mode with bits md1 and md0 in the timer mode register (tmdr). set the timer period buffer register (tpbr) to 1/2 the pwm carrier period, set dead time td in the timer dead time data register (tddr) (when outputting an ideal waveform, td = h'0000), and set {tpbr value + 2td} in the timer period data register (tpdr). section 11 motor management timer (mmt) rev. 7.00 sep. 11, 2009 page 258 of 566 rej09b0211-0700 set {pwm duty initial value ? td} in the free write operation addresses for tbru to tbrw. the values of tbru to tbrw should always be set in the range h'0000 to h'ffff ? 2t d, and the value of tpbr should always be set in the range h'0000 to h'ffff ? 4td. pwm output active level setting: in the operating modes, the active level of pwm pulses is set with bits olsn and olsp in the timer mode register (tmdr). the output level can be set for the three positive phases and the three negative phases of 6-phase output. the operating mode must be exited before setting or changing the output level. dead time setting: in the operating modes, pwm pulses are output with a non-overlap relationship between the positive and negative phases . this non-overlap time is known as the dead time. the non-overlap time is set in the timer dead time data register (tddr). the dead time generation waveform is generated by comparing the value set in tddr with the timer dead time counters (tdcnt) for each phase. the operating mode must be exited before changing the contents of tddr. pwm period setting: in the operating modes, 1/2 the pwm pulse period is set in the tpbr register. the tpbr value should always be se t in the range h'0000 to h'ffff ? 4td. the value set in tpbr is transferred to tpdr at the timi ng selected with bits md1 and md0 in the timer mode register (tmdr). after the transfer, the value in tpdr is {tpbr value + 2td}. the new pwm period is effective from the next period when data is updated at the tcnt counter crest, and from the same period when data is updated at the trough. register updating: in the operating modes, buffer registers are used to update compare register data. update data can be written to a buffer regi ster at all times. the buffer register value is transferred to the compare register at the timing set by bits md1 and md0 in the timer mode register (tmdr) (except in the case of a write to the free operation address for tbru to tbrw, in which case the value is transferred to the corresponding compare register immediately). initial output in operating modes: the initial output in the operating modes is determined by the initial values of tbru to tbrw. table 11.2 shows the relationship between the initial value of tbru to tbrw and the initial output. section 11 motor management timer (mmt) rev. 7.00 sep. 11, 2009 page 259 of 566 rej09b0211-0700 table 11.2 initial values of tbru to tbrw and initial output initial output initial value of tbru to tbrw olsp = 1, olsn = 1 olsp = 0, olsn = 0 tbr = h'0000 positive phase: 1 negative phase: 0 positive phase: 0 negative phase: 1 h'0000 < tbr td positive phase: 0 negative phase: 0 positive phase: 1 negative phase: 1 td < tbr h'ffff ? 2td positive phase: 0 negative phase: 1 positive phase: 1 negative phase: 0 pwm output generation in operating modes: in the operating modes, a 3-phase pwm waveform is output with a non-overlap relationship between the positive and negative phases. this non-overlap time is called the dead time. the pwm waveform is generated from an output generation waveform generated by anding the compare output waveform with the dead time generation waveform. waveform generation for one phase (the u-phase) is shown here. the v-phase and w-phase waveforms are generated in the same way. 1. compare output waveform the compare output waveform is generated by comparing the values in the tcnt counter and the tgr registers. for compare output waveform u phase a (cmoua), 0 is output if tgruu > tcnt in the t1 interval (when tcnt is counting up), and 1 is output if tgruu tcnt. in the t2 interval (when tcnt is counting down), 0 is output if tgru > tcnt, and 1 is output if tgru tcnt. for compare output waveform u phase b (cmoub), 1 is output if tgru > tcnt in the t1 interval, and 0 is output if tgru tcnt. in the t2 interval, 1 is output if tgrud > tcnt, and 0 is output if tgrud tcnt. 2. dead time generation waveform for dead time generation waveform u phases a (dtgua) and b (dtgub), 1 is output as the initial value. tdcnt0 starts counting at the falling edge of cmoua. dtgua outputs 0 if tdcnt0 is counting, and 1 otherwise. tdcnt1 starts counting at the falling edge of cmoub. dtgub outputs 0 if tdcnt1 is counting, and 1 otherwise. section 11 motor management timer (mmt) rev. 7.00 sep. 11, 2009 page 260 of 566 rej09b0211-0700 3. output generation waveform output generation waveform u phase a (ogua) is generated by anding cmoua and dtgub, and output generation waveform u phase b (ogub) is generated by anding cmoub and dtgua. 4. pwm waveform the pwm waveform is generated by converting th e output generation waveform to the output level set in bits olsn and olsp in the timer mode register (tmdr). figure 11.6 shows an example of pwm waveform generation (operating mode 3, olsn = 1, olsp = 1). when writin g to free operation address tpdr 2td compare output waveform dead time g eneration waveform output g eneration waveform pwm waveform figure 11.6 example of pwm waveform generation 0% to 100% duty output: in the operating modes, pwm waveforms with any duty from 0% to 100% can be output. the output pwm duty is set using the buffer registers (tbru to tbrw). 100% duty output is performed when the buffer register (tbru to tbrw) value is set to h'0000. the waveform in this case has positive phase in the 100% on state. 0% duty output is performed when a value greater than the tp dr value is set as the buffer register (tbru to tbrw) value. the waveform in this case has pos itive phase in the 100% off state. external counter clear function: in the operating modes, the tcnt counter can be cleared from an external source. when using the counter clear function, the pci pin function should be set to input using the mmt pin control register. section 11 motor management timer (mmt) rev. 7.00 sep. 11, 2009 page 261 of 566 rej09b0211-0700 at the falling edge of pci , the tcnt counter is cleared to 2t d (initial set value), counts up until it reaches the tpdr value, and then starts counting down. when the count reaches 2td, tcnt starts counting up again, and this sequence is repeated. an example of counter clearing is shown in figure 11.7. tcnt tpdr 2td h'0000 pci pin (counter clear input) figure 11.7 example of tcnt counter clearing toggle output synchronized with pwm period: in the operating modes, output can be toggled synchronously with the pwm carrier period. when outputting the pwm period, the pco pin function should be set to output using the mmt pin control register. an example of the toggle output waveform is shown in figure 11.8. pwm output is toggled according to the tcnt co unt direction. the toggl e output pin is pco. pco outputs 1 when tcnt is counting up, and 0 when counting down. output state when counter is halted: when tcnt is halted, the state of the pwm outputpin is retained. the tcnt value is also retained. section 11 motor management timer (mmt) rev. 7.00 sep. 11, 2009 page 262 of 566 rej09b0211-0700 tcnt tpdr 2td h'0000 pco pin (to gg le output) figure 11.8 example of toggle output waveform synchronized with pwm period 11.4.2 output protection functions operating mode output has the following protection functions: ? halting pwm output by external signal the 6-phase pwm output pins can be placed in the high-impedance state automatically by inputting a specified external signal. there are four external signal input pins. for details, see section 11.8, port output enable (poe). ? halting mmt output when oscillation stops the 6-phase pwm output pins are placed in th e high-impedance state automatically when stoppage of the clock input is detected. however, pin states are not guaranteed when the clock is restarted. section 11 motor management timer (mmt) rev. 7.00 sep. 11, 2009 page 263 of 566 rej09b0211-0700 11.5 interrupts when the tgfm (tgfn) flag is set to 1 in th e timer status register (tsr) by a compare match between tcnt and the tpdr register (2td), and if the tgiem (tgien) bit setting in the timer control register (tcnr) is 1, an interrupt is requested. the interrupt request is cleared by clearing the tgf flag to 0. table 11.3 mmt interrupt sources name interrupt source interrupt flag dtc activation tgimn compare match between tcnt and tpdr tgfm yes tginn compare match between tcnt and 2td tgfn yes the on-chip dtc can be activated by a compar e match between tcnt and tpdr or between tcnt and 2td. section 11 motor management timer (mmt) rev. 7.00 sep. 11, 2009 page 264 of 566 rej09b0211-0700 11.6 operation timing 11.6.1 input/output timing tcnt and tdcnt count timing: figure 11.9 shows the tcnt and tdcnt count timing. n ? 3n ? 2n ? 1 n n + 1n + 2n + 3n + 4 tcnt, tdcnt figure 11.9 count timing tcnt counter clea ring timing: figure 11.10 shows the timing of tcnt counter clearing by an external signal. n ? 3n ? 2n ? 1 n n + 1 2td 2td + 1 2td + 2 td tcnt counter clear si g nal tddr figure 11.10 tcnt counter clearing timing section 11 motor management timer (mmt) rev. 7.00 sep. 11, 2009 page 265 of 566 rej09b0211-0700 tdcnt operation timing: figure 11.11 shows the tdcnt operation timing. h'0001 . . . . td ? 1 td h'0000 h'0000 td cmo tdcnt tddr compare match si g nal tdcnt clear si g nal dtg figure 11.11 tdcnt operation timing dead time generation timing: figure 11.12 shows the timing for dead time generation. section 11 motor management timer (mmt) rev. 7.00 sep. 11, 2009 page 266 of 566 rej09b0211-0700 n + td n - td n td tdcnt tcnt tddr tgruu, tgrvu, tgrwu n - 1 n n + 1 n + td n + 1 + td 01 td 0 tgru, tgrv, tgrw tgrud, tgrvd, tgrwd puoa, pvoa, pwoa puob, pvob, pwob n + td n ? td n td tdcnt tcnt section 11 motor management timer (mmt) rev. 7.00 sep. 11, 2009 page 267 of 566 rej09b0211-0700 buffer operation timing: figure 11.13 shows the compare match buffer operation timing. m1 m2 m0 td tpbr tddr l0 + 2td l2 + 2td l1 + 2td tgruu, tgrvu, tgrwu l0 + td l2 + td l1 + td tgru, tgrv, tgrw l0 l2 l1 tgrud, tgrvd, tgrwd l1 l2 l0 tbru, tbrv, tbrw m1 + 2td m2 + 2td m0 + 2td tpdr n ? 1 . . . . n ? 1n 2td + 1 2td 2td + 1 2td + 2 tcnt compare match si g nal figure 11.13 buffer operation timing section 11 motor management timer (mmt) rev. 7.00 sep. 11, 2009 page 268 of 566 rej09b0211-0700 11.6.2 interrupt signal timing timing of tgf flag setting by compare match: figure 11.14 shows the timing of setting of the tgf flag in the timer status register (t sr) on a compare match between tcnt and tpdr, and the timing of the tgi interrupt request signal. the timing is the same for a compare match between tcnt and 2td. n tpdr n ? 3n ? 2n ? 1 n n + 1n + 2n + 3n + 4 tcnt compare match si g nal tgf fla g tgi interrupt figure 11.14 tgi interrupt timing section 11 motor management timer (mmt) rev. 7.00 sep. 11, 2009 page 269 of 566 rej09b0211-0700 status flag clearing timing: a status flag is cleared when th e cpu reads 1 from the flag, then 0 is written to it. when the dtc controller is activated, the flag is cleared automatically. figure 11.15 shows the timing of status flag clearing by the cpu, and figure 11.16 shows the timing of status flag clearing by the dtc. tsr address address tgi interrupt status fla g write si g nal t 1 t 2 t 3 tsr write cycle figure 11.15 timing of status flag clearing by cpu source address address tgi interrupt status fla g destination address t 1 t 2 dtc read cycle dtc write cycle t 3 t 1 t 2 t 3 figure 11.16 timing of status flag clearing by dtc controller section 11 motor management timer (mmt) rev. 7.00 sep. 11, 2009 page 270 of 566 rej09b0211-0700 11.7 usage notes 11.7.1 module stop mode setting mmt operation can be disabled or enabled usi ng the module stop control register. the initial setting is for mmt operation to be halted. regi ster access is enabled by clearing module stop mode. for details, refer to section 20, power-down modes. 11.7.2 notes for mmt operation note that the kinds of operation and contention described below occur during mmt operation. contention between buffer regi ster write and compare match: if a compare match occurs in the t 2 state of a buffer register (tbru to tbrw, or tpbr) write cycle, data is transferred from the buffer register to the compare register (t gr or tpdr) by a buffer operation. the data transferred is the buffer register write data. figure 11.17 shows the timing in this case. buffer re g ister write data nm m address compare match si g nal tgi interrupt buffer re g ister compare re g ister write si g nal buffer re g ister address t 1 t 2 t 3 buffer re g ister write cycle figure 11.17 contention between buffer register write and compare match section 11 motor management timer (mmt) rev. 7.00 sep. 11, 2009 page 271 of 566 rej09b0211-0700 contention between compare re gister write and compare match: if a compare match occurs in the t 3 state of a compare register (tgr or tpdr ) write cycle, the compare register write is not performed, and data is transferred from the buffer register (tbru, tbrv, tbrw, or tpbr) to the compare register by a buffer operation. figure 11.18 shows the timing in this case. n n address compare match si g nal tgi interrupt buffer re g ister compare re g ister write si g nal compare re g ister address compare re g ister write data compare re g ister write cycle t 1 t 2 t 3 figure 11.18 contention between compare register write and compare match section 11 motor management timer (mmt) rev. 7.00 sep. 11, 2009 page 272 of 566 rej09b0211-0700 writing to timer general register u (tgru) , timer general register v (tgrv), timer general register w (tgrw): pay attention to the notices below, when a value is written into the timer general register u (tgru), timer general register v (tgrv), timer general register w (tgrw), and in case of written into free operation address * . ? in case of count up: do not write a value ?previous value of tgru + td? into tgru. ? in case of count down: do not write a value ?previous value of tgru + td? into tgru. in the same manner to tgrv, and tgrw. when a value ?previous value of tgru + td? is written (in case of count down ?previous value of tgru ? td?), the output of puoa/puob, pvoa/pvob, pwoa/pwob (corresponding to u, v, w phase may not be output for 1 cycle. figure 11.19 shows the error case. this note is not applied when a value is written into buffer operation address. note: when address, h'ffff049c, h'ffff04ac, h' ffff04bc are used as register address for tbru, tbrv, tbrw, respectively. tgru previous value of tgru 2td td case of count up previous value of tgru tgru 2td td case of count down figure 11.19 error case in writing operation writing to timer period da ta register (tpdr), and timer dead time data register (tddr): ? do not revise tpdr register when mmt is operating. always use a buffer-write operation through tpbr register. ? do not revise tddr register once an operation of mmt is invoked. when tddr is revised, a wave may not be output for as much as 1 cycle (full count period of 16 bits in tdcnt), because a value cannot be written into tdcnt, which is compared to a value set in tddr. section 11 motor management timer (mmt) rev. 7.00 sep. 11, 2009 page 273 of 566 rej09b0211-0700 note on mmt dead time: the dead time (non-overlap time) may be shorter than the value set in the time dead time register (mmt_tddr), or a silent (consisting of 0s) pwm waveform may be output. dead time matches set value exactly normal output waveform puoa * puob * note: * also applies to the combination of pvoa and pvbo or pwoa and pwbo. dead time is shorter than set value output waveform caused by dead time limitation figure 11.20 output waveform caused by dead time limitation to prevent the problem from occurring , implement either a or b below. 1. set the cst bit to 1 and do not clear it after mmt counting begins. if there is a need to clear the cst bit, do not set it to 1 again. 2. in order to set, clear, and then reset the cst bit, use the following procedure for clearing and resetting. (1) set the pwm output pin as a general input port in the mmt pin control register. (2) set a value of h'0000 in the free operation addresses of all the buffer registers (tbru, tbrv and tbrw). (3) after the set dead time interval has elapsed set tcnr to h'00 and clear the cst bit to 0. (4) reset the cst bit to 1. section 11 motor management timer (mmt) rev. 7.00 sep. 11, 2009 page 274 of 566 rej09b0211-0700 11.8 port output enable (poe) the port output enable (poe) circuit enables the mmt?s output pins (poua, poub, pova, povb, powa, powb, and pco) to be placed in the high-impedance state by varying the input at pins poe0 to poe3 . an interrupt can also be requested at the same time. 11.8.1 features the poe circuit has the following features: ? falling edge, /8 16 times, /16 16 times, or /128 16 times low-level sampling can be set for each of input pins poe0 to poe3 . ? the mmt?s output pins can be placed in the high-impedance state on sampling of a falling edge or low level at pins poe0 to poe3 . ? an interrupt request can be initiated by input level sampling. /8 poe3 poe2 poe1 poe0 /16 frequency divider fallin g ed g e detection circuit low level detection circuit icsr input level detection circuit /128 hi g h impedance request control si g nal interrupt request figure 11.21 block diagram of poe section 11 motor management timer (mmt) rev. 7.00 sep. 11, 2009 page 275 of 566 rej09b0211-0700 11.8.2 input/output pins table 11.4 shows the pin configuration of the poe circuit. table 11.4 pin configuration name abbreviation i/o function port output enable input pins poe0 to poe3 input input request signals for placing mmt?s output pins in high-impedance state 11.8.3 register descriptions the poe circuit has the following registers. the icsr registers are initialized by a reset or in hardware standby mode. however, they are not in itialized in software standby mode or sleep mode and retain their previous values. for details on re gister addresses, refer to appendix a, on-chip i/o register. ? input level control/status register (icsr) ? poe pin control register (poepc) input level control/status register (icsr): the input level control/status register (icsr) is a 16-bit readable/writable register that selects the input mode for pins poe0 to poe3 , controls enabling or disabling of interrupts, and holds status information. bit bit name initial value r/w description 15 poe3f 0 r/(w) * poe3 flag indicates that a high impedance request has been input to the poe3 pin. [clearing condition] ? when 0 is written to poe3f after reading poe3f = 1 [setting condition] ? when the input set by bits 6 and 7 of icsr occurs at the poe3 pin section 11 motor management timer (mmt) rev. 7.00 sep. 11, 2009 page 276 of 566 rej09b0211-0700 bit bit name initial value r/w description 14 poe2f 0 r/(w) * poe2 flag indicates that a high impedance request has been input to the poe2 pin. [setting condition] ? when the input set by bits 4 and 5 of icsr occurs at the poe2 pin [clearing condition] ? when 0 is written to poe2f after reading poe2f = 1 13 poe1f 0 r/(w) * poe1 flag indicates that a high impedance request has been input to the poe1 pin. [setting condition] ? when the input set by bits 2 and 3 of icsr occurs at the poe1 pin [clearing condition] ? when 0 is written to poe1f after reading poe1f = 1 12 poe0f 0 r/(w) * poe0 flag indicates that a high impedance request has been input to the poe0 pin. [setting condition] ? when the input set by bits 0 and 1 of icsr occurs at the poe0 pin [clearing condition] ? when 0 is written to poe0f after reading poe0f = 1 11 to 9 ? all 0 ? reserved these bits are always read as 0. only 0 should be written to these bits. 8 pie 0 r/w port interrupt enable enables or disables an interrupt request when 1 is set in any of bits poe0f to poe3f in icsr. 0: interrupt request disabled 1: interrupt request enabled section 11 motor management timer (mmt) rev. 7.00 sep. 11, 2009 page 277 of 566 rej09b0211-0700 bit bit name initial value r/w description 7 6 poe3m1 poe3m0 0 0 r/w r/w poe3 modes 1 and 0 these bits select the input mode of the poe3 pin. 00: request accepted at falling edge of poe3 input 01: poe3 input is sampled for low level 16 times every /8 clock, and request is accepted when all samples are low level 10: poe3 input is sampled for low level 16 times every /16 clock, and request is accepted when all samples are low level 11: poe3 input is sampled for low level 16 times every /128 clock, and request is accepted when all samples are low level 5 4 poe2m1 poe2m0 0 0 r/w r/w poe2 modes 1 and 0 these bits select the input mode of the poe2 pin. 00: request accepted at falling edge of poe2 input 01: poe2 input is sampled for low level 16 times every /8 clock, and request is accepted when all samples are low level 10: poe2 input is sampled for low level 16 times every /16 clock, and request is accepted when all samples are low level 11: poe2 input is sampled for low level 16 times every /128 clock, and request is accepted when all samples are low level 3 2 poe1m1 poe1m0 0 0 r/w r/w poe1 modes 1 and 0 these bits select the input mode of the poe1 pin. 00: request accepted at falling edge of poe1 input 01: poe1 input is sampled for low level 16 times every /8 clock, and request is accepted when all samples are low level 10: poe1 input is sampled for low level 16 times every /16 clock, and request is accepted when all samples are low level 11: poe1 input is sampled for low level 16 times every /128 clock, and request is accepted when all samples are low level section 11 motor management timer (mmt) rev. 7.00 sep. 11, 2009 page 278 of 566 rej09b0211-0700 bit bit name initial value r/w description 1 0 poe0m1 poe0m0 0 0 r/w r/w poe0 modes 1 and 0 these bits select the input mode of the poe0 pin. 00: request accepted at falling edge of poe0 input 01: poe0 input is sampled for low level 16 times every /8 clock, and request is accepted when all samples are low level 10: poe0 input is sampled for low level 16 times every /16 clock, and request is accepted when all samples are low level 11: poe0 input is sampled for low level 16 times every /128 clock, and request is accepted when all samples are low level note: * only 0 can be written, for flag clearing. poe pin control register (poepc): poepc is an 8-bit readable/wr itable register that controls enabling or disabling of the poe pin. bit bit name initial value r/w description 7 poe3e 0 r/w poe3 enabled 0: pa3 pin is port i/o pin/sck2 i/o pin 1: pa3 pin is poe3 input pin of poe 6 poe2e 0 r/w poe2 enabled 0: pa2 pin is port i/o pin/rxd2 input pin 1: pa2 pin is poe2 input pin of poe 5 poe1e 0 r/w poe1 enabled 0: pa1 pin is port i/o pin/txd output pin 1: pa1 pin is poe1 input pin of poe 4 poe0e 0 r/w poe0 enabled 0: pa0 pin is port i/o pin 1: pa0 pin is poe0 input pin of poe 3 to 0 ? undefined ? reserved section 11 motor management timer (mmt) rev. 7.00 sep. 11, 2009 page 279 of 566 rej09b0211-0700 11.8.4 operation input level detection: when the input condition set in icsr occurs on any one of the poe pins, the mmt output pins go to the high-impedance state. ? pins placed in the high-impedan ce state (the mmt?s output pins) the 7 pins pwob, pwoa, pvob, pvoa, p uob, puoa, pco are placed in the high- impedance state. note: when used as an output port or tpu output pin, a pin will not enter the high-impedance state. 1. falling edge detection when a transition from high- to low-level input occurs on a poe pin. 2. low level detection figure 11.22 shows the low level detection oper ation. low level sampling is performed 16 times in succession using the sampling clock set in icsr. the input is not accepted if a high level is detected even once among these samples. the timing of entry of the mmt's output pins into the high-impedance state from the sampling clock is the same for falling edge detection and low level detection. 8, 16, or 128 clocks samplin g clock poe input puoa all samples low-level at least one hi g h-level sample [1] [1] [2] [2] [3] [16] fla g set (poe accepted) hi g h-impedance state fla g not set [13] note: the other mmt output pins also g o to the hi g h-impedance state at the same timin g . figure 11.22 low level detection operation exiting high-impedance state: the mmt output pins that have entered the high-impedance state are released from this state by restoring them to their initial states by means of a power-on reset, or by clearing all the poe flags in icsr (poe0f to poe3f: bits 12 to 15). section 11 motor management timer (mmt) rev. 7.00 sep. 11, 2009 page 280 of 566 rej09b0211-0700 section 12 programmable pulse generator (ppg) rev. 7.00 sep. 11, 2009 page 281 of 566 rej09b0211-0700 section 12 programmable pulse generator (ppg) the programmable pulse generator provides pulse outputs using the 16-bit timer pulse unit (tpu) as a time base. the ppg pulse outputs are divided into 4-bit groups (group 2 and group 3) that can operate both simultaneously and independently. the block diagram of the ppg is shown in figure 12.1. note: no ppg is implemented in the h8s/2614 and h8s/2616. 12.1 features ? 8-bit output data ? two output groups ? selectable output trigger signals ? non-overlap mode ? can operate in tandem with the data transfer controller (dtc) ? settable inverted output ? module stop mode can be set section 12 programmable pulse generator (ppg) rev. 7.00 sep. 11, 2009 page 282 of 566 rej09b0211-0700 compare match si g nals po15 po14 po13 po12 po11 po10 po9 po8 le g end: ppg output mode re g ister ppg output control re g ister next data enable re g ister h next data enable re g ister l next data re g ister h next data re g ister l output data re g ister h output data re g ister l pmr: pcr: nderh: nderl: ndrh: ndrl: podrh: podrl: pulse output pins, g roup 3 pulse output pins, g roup 2 pulse output pins, g roup 1 pulse output pins, g roup 0 podrh podrl ndrh ndrl control lo g ic nderh pmr nderl pcr internal data bus figure 12.1 block diagram of ppg section 12 programmable pulse generator (ppg) rev. 7.00 sep. 11, 2009 page 283 of 566 rej09b0211-0700 12.2 input/output pins table 12.1 summarizes the i/o pins of the ppg. table 12.1 ppg i/o pins pin name i/o function po15 output po14 output po13 output po12 output group 3 pulse output po11 output po10 output po9 output group 2 pulse output po8 output 12.3 register descriptions the ppg has the following registers. for details on register addresses and register states during each processing, refer to appe ndix a, on-chip i/o register. ? ppg output control register (pcr) ? ppg output mode register (pmr) ? next data enable register h (nderh) ? next data enable register l (nderl) ? output data register h (podrh) ? output data register l (podrl) ? next data register h (ndrh) ? next data register l (ndrl) section 12 programmable pulse generator (ppg) rev. 7.00 sep. 11, 2009 page 284 of 566 rej09b0211-0700 12.3.1 next data enable registers h, l (nderh, nderl) nderh and nderl are an 8-bit read able/writable register that enables or disables pulse output on a bit-by-bit basis. the corresponding ddr also needs to be set to 1 in order to enable pulse output by the ppg. nderh bit bit name initial value r/w description 7 6 5 4 3 2 1 0 nder15 nder14 nder13 nder12 nder11 nder10 nder9 nder8 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w next data enable 8 to 15 when a bit is set to 1 for pulse output by ndrh, the value in the corresponding ndrh bit is transferred to the podrh bit by the selected outpu t trigger. values are not transferred from ndrh to podrh for cleared bits. nderl bit bit name initial value r/w description 7 6 5 4 3 2 1 0 nder7 nder6 nder5 nder4 nder3 nder2 nder1 nder0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w next data enable 0 to 7 when a bit is set to 1 for pulse output by ndrl, the value in the corresponding ndrl bit is transferred to the podrl bit by the selected output trigger. values are not transferred from ndrl to podrl for cleared bits. section 12 programmable pulse generator (ppg) rev. 7.00 sep. 11, 2009 page 285 of 566 rej09b0211-0700 12.3.2 output data registers h, l (podrh, podrl) podrh and podrl are 8-bit readable/writable registers that store output data for use in pulse output. a bit that has been set for pulse output by nder is read-only and cannot be modified. podrh bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pod15 pod14 pod13 pod12 pod11 pod10 pod9 pod8 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w output data register 8 to 15 for bits that have been set to pulse output by nderh, the output trigger transfers ndrh values to this register during ppg operation. while nderh is set to 1, the cpu cannot write to this register. while nderh is cleared, the initial output value of the pulse can be set. podrl bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pod15 pod14 pod13 pod12 pod11 pod10 pod9 pod8 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w output data register 0 to 7 for bits which have been set to pulse output by nderl, the output trigger transfers ndrl values to this register during ppg operation. while nderl is set to 1, the cpu cannot write to this register. while nderl is cleared, the initial output value of the pulse can be set. section 12 programmable pulse generator (ppg) rev. 7.00 sep. 11, 2009 page 286 of 566 rej09b0211-0700 12.3.3 next data registers h, l (ndrh, ndrl) ndrh and ndrl are an 8-bit readable/writable regist er that stores the data for the next pulse output. the ndr addresses differ depending on whether pulse output groups have the same output trigger or different output triggers. ndrh if pulse output groups 2 and 3 have the same output trigger, all eight bits are mapped to the same address and can be accessed at one time, as shown below. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 ndr15 ndr14 ndr13 ndr12 ndr11 ndr10 ndr9 ndr8 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w next data register 8 to 15 the register contents are transferred to the corresponding podrh bits by the output trigger specified with pcr. if pulse output groups 2 and output pulse groups 3 have different output triggers, the upper 4 bits and the lower 4 bits are mapped to different addresses, as shown below. bit bit name initial value r/w description 7 6 5 4 ndr15 ndr14 ndr13 ndr12 0 0 0 0 r/w r/w r/w r/w next data register 12 to 15 the register contents are transferred to the corresponding podrh bits by the output trigger specified with pcr. 3 to 0 ? all 1 ? reserved these bits are always read as 1 and cannot be modified. section 12 programmable pulse generator (ppg) rev. 7.00 sep. 11, 2009 page 287 of 566 rej09b0211-0700 bit bit name initial value r/w description 7 to 4 ? all 1 ? reserved these bits are always read as 1 and cannot be modified. 3 2 1 0 ndr11 ndr10 ndr9 ndr8 0 0 0 0 r/w r/w r/w r/w next data register 8 to11 the register contents are transferred to the corresponding podrh bits by the output trigger specified with pcr. ndrl if pulse output groups 0 and 1 have the same output trigger, all eight bits are mapped to the same address and can be accessed at one time, as shown below. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 ndr7 ndr6 ndr5 ndr4 ndr3 ndr2 ndr1 ndr0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w next data register 0 to 7 the register contents are transferred to the corresponding podrl bits by the output trigger specified with pcr. section 12 programmable pulse generator (ppg) rev. 7.00 sep. 11, 2009 page 288 of 566 rej09b0211-0700 if pulse output groups 0 and output pulse groups 1 have different output triggers, upper 4 bits and lower 4 bits are mapped to the different addresses as shown below. bit bit name initial value r/w description 7 6 5 4 ndr7 ndr6 ndr5 ndr4 0 0 0 0 r/w r/w r/w r/w next data register 4 to 7 the register contents are transferred to the corresponding podrl bits by the output trigger specified with pcr. 3 to 0 ? all 1 ? reserved these bits are always read as 1 and cannot be modified. bit bit name initial value r/w description 7 to 4 ? all 1 ? reserved 1 is always read and write is disabled. 3 2 1 0 ndr3 ndr2 ndr1 ndr0 0 0 0 0 r/w r/w r/w r/w next data register 3 to 0 the register contents are transferred to the corresponding podrl bits by the output trigger specified with pcr. section 12 programmable pulse generator (ppg) rev. 7.00 sep. 11, 2009 page 289 of 566 rej09b0211-0700 12.3.4 ppg output control register (pcr) pcr is an 8-bit readable/writable register that selects output trigger signals on a group-by-group basis. for details on output trigger selection, refe r to section 12.3.5, ppg output mode register (pmr). bit bit name initial value r/w description 7 6 g3cms1 g3cms0 1 1 r/w r/w group 3 compare match select 0 and 1 select output trigger of pulse output group 3. 00: compare match in tpu channel 0 01: compare match in tpu channel 1 10: compare match in tpu channel 2 11: compare match in tpu channel 3 5 4 g2cms1 g2cms0 1 1 r/w r/w group 2 compare match select 0 and 1 select output trigger of pulse output group 2. 00: compare match in tpc channel 0 01: compare match in tpc channel 1 10: compare match in tpc channel 2 11: compare match in tpc channel 3 3 2 g1cms1 g1cms0 1 1 r/w r/w reserved 1 0 g0cms1 g0cms0 1 1 r/w r/w reserved section 12 programmable pulse generator (ppg) rev. 7.00 sep. 11, 2009 page 290 of 566 rej09b0211-0700 12.3.5 ppg output mode register (pmr) the pmr is an 8-bit read able/writable register that selects the pulse output mode of the ppg for each group. if inverted output is selected, a lo w-level pulse is output when podrh is 1 and a high-level pulse is output when podrh is 0. if non-overlapping operation is selected, ppg updates its output values on compare match a or b of the tpu that becomes the output trigger. for details, refer to section 12.4.5, non-overlapping pulse output. bit bit name initial value r/w description 7 g3inv 1 r/w group 3 inversion selects direct output or inverted output for pulse output group 3. 0: inverted output 1: direct output 6 g2inv 1 r/w group 2 inversion selects direct output or inverted output for pulse output group 2. 0: inverted output 1: direct output 5, 4 ? all 1 r/w reserved 3 g3nov 0 r/w group 3 non-overlap selects normal or non-overlapping operation for pulse output group 3. 0: normal operation (output values updated at compare match a in the selected tpu channel) 1: non-overlapping operation (output values at compare match a or b in the selected tpu channel) 2 g2nov 0 r/w group 2 non-overlap selects normal or non-overlapping operation for pulse output group 2. 0: normal operation (output values updated at compare match a in the selected tpu channel) 1: non-overlapping operation (output values at compare match a or b in the selected tpu channel) 1, 0 ? all 0 r/w reserved section 12 programmable pulse generator (ppg) rev. 7.00 sep. 11, 2009 page 291 of 566 rej09b0211-0700 12.4 operation 12.4.1 overview figure 12.2 shows a block diagram of the ppg. ppg pulse output is enabled when the corresponding bits in p1ddr and nder are set to 1. an initial output value is determined by its corresponding podr initial setting. when the compare match event specified by pcr occurs, the corresponding ndr bit contents are transferred to podr to update the output values. the sequential output of up to 8 bits of data is possible by writing new output data to ndr before the next compare match. output tri gg er si g nal pulse output pin internal data bus normal output/inverted output c podr qd nder q ndr qd ddr figure 12.2 ppg output operation section 12 programmable pulse generator (ppg) rev. 7.00 sep. 11, 2009 page 292 of 566 rej09b0211-0700 12.4.2 output timing if pulse output is enabled, the contents of ndr contents are transferred to podr and output when the specified compare match even t occurs. figure 12.3 shows the timing of these operations for the case of normal output in groups 2 and 3, triggered by compare match a. tcnt nn + 1 tgra n compare match a si g nal ndrh mn podrh po8 to po15 n mn figure 12.3 timing of transfer and output of ndr contents (example) section 12 programmable pulse generator (ppg) rev. 7.00 sep. 11, 2009 page 293 of 566 rej09b0211-0700 12.4.3 sample setup procedu re for normal pulse output figure 12.4 shows a sample procedure for setting up normal pulse output. select tgr functions [1] set tgra value set countin g operation select interrupt request set initial output data enable pulse output select output tri gg er set next pulse output data start counter set next pulse output data normal ppg output no yes tpu setup port and ppg setup tpu setup [2] [3] [4] [5] [6] [7] [8] [9] [10] compare match? [1] set tior to make tgra an output compare re g ister (with output disabled). [2] set the ppg output tri gg er period. [3] select the counter clock source with bits tpsc2 to tpsc0 in tcr. select the counter clear source with bits cclr1 and cclr0. [4] enable the tgia interrupt in tier. the dtc can also be set up to transfer data to ndr. [5] set the initial output values in podr. [6] set the ddr and nder bits for the pins to be used for pulse output to 1. [7] select the tpu compare match event to be used as the output tri gg er in pcr. [8] set the next pulse output values in ndr. [9] set the cst bit in tstr to 1 to start the tcnt counter. [10] at each tgia interrupt, set the next output values in ndr. figure 12.4 setup procedure for normal pulse output (example) section 12 programmable pulse generator (ppg) rev. 7.00 sep. 11, 2009 page 294 of 566 rej09b0211-0700 12.4.4 example of normal pulse output (example of five-phase pulse output) figure 12.5 shows an example in which pulse output is used for cyclic five-phase pulse output. tcnt value tcnt tgra h'0000 ndrh 00 80 c0 40 60 20 30 10 18 08 88 podrh po15 po14 po13 po12 po11 time compare match c0 80 c0 80 40 60 20 30 10 18 08 88 80 c0 40 figure 12.5 normal pulse output example (five-phas e pulse output) 1. set up tgra of the tpu that is used as the output trigger to be an output compare register. set a frequency in tgra so the counter will be cl eared on compare match a. set the tgiea bit of tier to 1 to enable the compare match/input capture a (tgia) interrupt. 2. write h'f8 in p1ddr and nderh, and set the g3cms0, g3cms1, g2cms0, and g2cms1 bits in pcr to select compare match in the tpu channel set up in the previous step to be the output trigger. write output data h'80 in ndrh. 3. when compare match a occurs, the ndrh c ontents are transferred to podrh and output. the tgia interrupt handling routine writes the next output data (h'c0) in ndrh. 4. five-phase overlapping pulse output (one or two phases active at a time) can be obtained subsequently by writing h'40, h'60, h'20, h'30. h'10, h'18, h'08, h'88, ... at successive tgia interrupts. if the dtc is set for activation by this interrupt, pulse output can be obtained without imposing a load on the cpu. section 12 programmable pulse generator (ppg) rev. 7.00 sep. 11, 2009 page 295 of 566 rej09b0211-0700 12.4.5 non-overlapping pulse output during non-overlapping operation, transfer from ndr to podr is performed as follows: ? ndr bits are always transferred on podr bits on compare match a. ? on compare match b, ndr bits are transferred only if their value is 0. bits are not transferred if their value is 1. figure 12.6 illustrates the non-overlapping pulse output operation. compare match a compare match b pulse output pin internal data bus normal output/inverted output c podr qd nder q ndr qd ddr figure 12.6 non-overlapping pulse output therefore, 0 data can be transferred ahead of 1 data by making compare match b occur before compare match a. the ndr contents should not be altered during the interval between compare match b and compare match a (the non-overlap margin). this can be accomplished by having the tgia inte rrupt handling routine write the next data in ndr, or by having the tgia interrupt activate the dtc. note, however, that the next data must be written before the next compare match b occurs. figure 12.7 shows the timing of this operation. section 12 programmable pulse generator (ppg) rev. 7.00 sep. 11, 2009 page 296 of 566 rej09b0211-0700 0/1 output 0 output 0/1 output 0 output do not write to ndr here write to ndr here compare match a compare match b ndr podr do not write to ndr here write to ndr here write to ndr write to ndr figure 12.7 non-overlapping operation and ndr write timing section 12 programmable pulse generator (ppg) rev. 7.00 sep. 11, 2009 page 297 of 566 rej09b0211-0700 12.4.6 sample setup procedure for non-overlapping pulse output figure 12.8 shows a sample procedure for setting up non-overlapping pulse output. select tgr functions [1] set tgr values set countin g operation select interrupt request set initial output data enable pulse output select output tri gg er set next pulse output data start counter set next pulse output data compare match a? no yes tpu setup ppg setup tpu setup non-overlappin g ppg output set non-overlappin g g roups [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [1] set tior to make tgra and tgrb an output compare re g isters (with output disabled). [2] set the pulse output tri gg er period in tgrb and the non-overlap mar g in in tgra. [3] select the counter clock source with bits tpsc2 to tpsc0 in tcr. select the counter clear source with bits cclr1 and cclr0. [4] enable the tgia interrupt in tier. the dtc can also be set up to transfer data to ndr. [5] set the initial output values in podr. [6] set the ddr and nder bits for the pins to be used for pulse output to 1. [7] select the tpu compare match event to be used as the pulse output tri gg er in pcr. [8] in pmr, select the g roups that will operate in non-overlap mode. [9] set the next pulse output values in ndr. [10] set the cst bit in tstr to 1 to start the tcnt counter. [11] at each tgia interrupt, set the next output values in ndr. figure 12.8 setup procedure for non-overlapping pulse output (example) section 12 programmable pulse generator (ppg) rev. 7.00 sep. 11, 2009 page 298 of 566 rej09b0211-0700 12.4.7 example of non-overlapping pulse output (example of four-phase complementary non-overlapping output) figure 12.9 shows an example in which pulse output is used for four-phase complementary non- overlapping pulse output. tcnt value tcnt tgrb tgra h'0000 ndrh 95 65 59 56 95 65 00 95 05 65 41 59 50 56 14 95 05 65 podrh po15 po14 po13 po12 po11 po10 po9 po8 time non-overlap mar g in figure 12.9 non-overlapping pulse output example (four-phase complementary) section 12 programmable pulse generator (ppg) rev. 7.00 sep. 11, 2009 page 299 of 566 rej09b0211-0700 1. set up the tpu channel to be used as the output trigger channel such that tgra and tgrb are output compare registers. set the trigger period in tgrb and the non-overlap margin in tgra, and set the counter to be cleared on compare match b. set the tgiea bit in tier to 1 to enable the tgia interrupt. 2. write h'ff in p1ddr and nderh, and set the g3cms1, g3cms0, g2cms1, and g2cms0 bits in pcr to select compare match in the tpu channel set up in the previous step to be the output trigger. set the g3nov and g2nov bits in pmr to 1 to select non-overlapping output. write output data h'95 in ndrh. 3. the timer counter in the tpu channel star ts. when a compare match with tgrb occurs, outputs change from 1 to 0. when a compare match with tgra occurs, outputs change from 0 to 1 (the change from 0 to 1 is delayed by the value set in tgra). the tgia interrupt handling routine writes the next output data (h'65) in ndrh. 4. four-phase complementary non-overlapping pulse output can be obtained subsequently by writing h'59, h'56, h'95, ... at successive tgia interrupts. if the dtc is set for activation by this interrupt, pulse output can be obtained without imposing a load on the cpu. section 12 programmable pulse generator (ppg) rev. 7.00 sep. 11, 2009 page 300 of 566 rej09b0211-0700 12.4.8 inverted pulse output if the g3inv, g2inv, g1inv, and g0inv bits in pmr are cleared to 0, values that are the inverse of the podr contents can be output. figure 12.10 shows the outputs when g3inv and g2inv are cleared to 0, in addition to the settings of figure 12.9. tcnt value tcnt tgrb tgra h'0000 ndrh 95 65 59 56 95 65 00 95 05 65 41 59 50 56 14 95 05 65 podrl po15 po14 po13 po12 po11 po10 po9 po8 time figure 12.10 inverted pulse output (example) section 12 programmable pulse generator (ppg) rev. 7.00 sep. 11, 2009 page 301 of 566 rej09b0211-0700 12.4.9 pulse output triggered by input capture pulse output can be triggered by tpu input capture as well as by compare match. if tgra functions as an input capture register in the tpu channel selected by pcr, pulse output will be triggered by the input capture signal. figure 12.11 shows the timing of this output. n mn tioc pin input capture si g nal ndr podr mn po figure 12.11 pulse output tri ggered by input capture (example) 12.5 usage notes 12.5.1 module stop mode setting ppg operation can be disabled or enabled using the module stop control register. the initial setting is for ppg operation to be halted. register access is enabled by clearing module stop mode. for details, refer to section 20, power-down modes. 12.5.2 operation of pulse output pins pins po8 to po15 are also used for other peripheral functions such as the tpu. when output by another peripheral function is enabled, the corresponding pins cannot be used for pulse output. note, however, that data transfer from ndr bits to podr bits takes place, regardless of the usage of the pins. pin functions should be changed only under conditi ons in which the output trigger event will not occur. section 12 programmable pulse generator (ppg) rev. 7.00 sep. 11, 2009 page 302 of 566 rej09b0211-0700 section 13 watchdog timer rev. 7.00 sep. 11, 2009 page 303 of 566 rej09b0211-0700 section 13 watchdog timer the watchdog timer (wdt) is an 8-bit timer that can generate an internal reset signal for this lsi if a system crash prevents the cpu from writing to the timer counter, thus allowing it to overflow. when this watchdog function is not needed, the wdt can be used as an interval timer. in interval timer operation, an interval timer interrupt is generated each time the counter overflows. the block diagram of the wdt is shown in figure 13.1. 13.1 features ? selectable from eight counter input clocks. ? switchable between watchdog timer mode and interval timer mode. in watchdog timer mode ? if the counter overflows, it is possible to select whether this lsi is internally reset or not. in interval timer mode ? if the counter overflows, the wdt generates an interval timer interrupt (wovi). section 13 watchdog timer rev. 7.00 sep. 11, 2009 page 304 of 566 rej09b0211-0700 overflow interrupt control wovi (interrupt request si g nal) internal reset si g nal * reset control rstcsr tcnt tscr /2 /64 /128 /512 /2048 /8192 /32768 /131072 clock clock select internal clock sources bus interface module bus tcsr: tcnt: rstcsr: note: * the type of internal reset si g nal depends on a re g ister settin g . timer control/status re g ister timer counter reset control/status re g ister wdt le g end: internal bus figure 13.1 block diagram of wdt 13.2 register descriptions the wdt has the following three registers. for details, refer to appendix a, on-chip i/o register. to prevent accidental overwriting, tcsr , tcnt, and rstcsr have to be written to by a different method to normal registers. for details, refer to section 13.5.1, notes on register access. ? timer control/status register (tcsr) ? timer counter (tcnt) ? reset control/status register (rstcsr) 13.2.1 timer counter (tcnt) tcnt is an 8-bit readable/writa ble up-counter. tcnt is initialized to h'00 by a reset, when the tme bit in tcsr is cleared to 0. section 13 watchdog timer rev. 7.00 sep. 11, 2009 page 305 of 566 rej09b0211-0700 13.2.2 timer control/sta tus register (tcsr) tcsr is an 8-bit readable/writable register. its functions include selecting the clock source to be input to tcnt, and selecting the timer mode. bit bit name initial value r/w description 7 ovf 0 r/(w) * overflow flag indicates that tcnt has overflowed. only a write of 0 is permitted, to clear the flag. [setting condition] ? when tcnt overflows (changes from h'ff to h'00) when internal reset request generation is selected in watchdog timer mode, ovf is cleared automatically by the internal reset. [clearing condition] ? cleared by reading tcsr when ovf = 1, then writing 0 to ovf 6 wt/it 0 r/w timer mode select selects whether the wdt is used as a watchdog timer or interval timer. 0: interval timer mode 1: watchdog timer mode 5 tme 0 r/w timer enable when this bit is set to 1, tcnt starts counting. when this bit is cleared, tcnt stops counting and is initialized to h'00. 4, 3 ? all 1 ? reserved these bits are always read as 1 and cannot be modified. section 13 watchdog timer rev. 7.00 sep. 11, 2009 page 306 of 566 rej09b0211-0700 bit bit name initial value r/w description 2 1 0 cks2 cks1 cks0 0 0 0 r/w r/w r/w clock select 0 to 2 selects the clock source to be input to tcnt. the overflow frequency for = 20 mhz is enclosed in parentheses. 000: clock /2 (frequency: 25.6 s) 001: clock /64 (frequency: 819.2 s) 010: clock /128 (frequency: 1.6 ms) 011: clock /512 (frequency: 6.6 ms) 100: clock /2048 (frequency: 26.2 ms) 101: clock /8192 (frequency: 104.9 ms) 110: clock /32768 (frequency: 419.4 ms) 111: clock /131072 (frequency: 1.68 s) note: * only 0 can be written, for flag clearing. section 13 watchdog timer rev. 7.00 sep. 11, 2009 page 307 of 566 rej09b0211-0700 13.2.3 reset control/status register (rstcsr) rstcsr is an 8-bit readable/writable register that controls the generation of the internal reset signal when tcnt overflows, and selects the type of internal reset signal. rstcsr is initialized to h'1f by a reset signal from the res pin, and not by the wdt internal reset signal caused by overflows. bit bit name initial value r/w description 7 wovf 0 r/(w) * watchdog overflow flag this bit is set when tcnt overflows in watchdog timer mode. this bit cannot be set in interval timer mode, and only 0 can be written. [setting condition] ? set when tcnt overflows (changed from h'ff to h'00) in watchdog timer mode [clearing condition] ? cleared by reading rstcsr when wovf = 1, and then writing 0 to wovf 6 rste 0 r/w reset enable specifies whether or not a reset signal is generated in the chip if tcnt overflows during watchdog timer operation. 0: reset signal is not generated even if tcnt overflows (though this lsi is not reset, tcnt and tcsr in wdt are reset) 1: reset signal is generated if tcnt overflows 5 rsts 0 r/w reset select selects the type of internal reset generated if tcnt overflows during watchdog timer operation. 0: power-on reset 1: setting prohibited 4 to 0 ? all 1 ? reserved these bits are always read as 1 and cannot be modified. note: * only 0 can be written, for flag clearing. section 13 watchdog timer rev. 7.00 sep. 11, 2009 page 308 of 566 rej09b0211-0700 13.3 operation 13.3.1 watchdog timer mode to use the wdt as a watchdog timer, set the wt/ it bit in tcsr and the tme bit to 1. when the wdt is used as a watchdog timer, and if tcnt overflows without being rewritten because of a system malfunction or other error, an in ternal reset occurs and th e internal chip states can be reset. tcnt does not overflow while the system is operating normally. software must prevent tcnt overflows by rewriting the tcnt value (normally be writing h'00) before overflows occurs. in this case, select power-on reset by se tting the rsts bit of the rstcsr to 0. the internal reset signal is output for 518 states. if a reset caused by a signal input to the res pin occurs at the same time as a reset caused by a wdt overflow, the res pin reset has priority and the wovf bit in rstcsr is cleared to 0. the wdtovf signal is output for 132 states when the rste bit = 1 of rstcsr, and for 130 states when the rste bit = 0. when the tcnt overflows in watchdog timer mode, the wovf bit of the rstcsr is set to 1. if the rste bit of the rstcsr has been set to 1, an internal reset signal for the entire lsi is generated at tcnt overflow. 13.3.2 interval timer mode when the wdt is used as an in terval timer, an interval timer interrupt (wovi) is generated each time the tcnt overflows. therefore, an interrupt can be generated at intervals. when the tcnt overflows in interval timer mode, an interval timer interrupt (wovi) is requested at the time the ovf bit of the tcsr is set to 1. section 13 watchdog timer rev. 7.00 sep. 11, 2009 page 309 of 566 rej09b0211-0700 13.4 interrupts during interval timer mode operation, an overflow generates an interval timer interrupt (wovi). the interval timer interrupt is requested whenever the ovf flag is set to 1 in tcsr. ovf must be cleared to 0 in the interrupt handling routine. table 13.1 wdt interrupt source name interrupt source interrupt flag dtc activation wovi tcnt overflow wovf impossible 13.5 usage notes 13.5.1 notes on register access the watchdog timer?s tcnt, tcsr, and rstcsr registers differ from other registers in being more difficult to write to. the procedures for writing to and reading these registers are given below. writing to tcnt, tcsr, and rstcsr these registers must be written to by a word transfer instruction. they cannot be written to by a byte transfer instruction. tcnt and tcsr both have the same write address. therefore, the relative condition shown in figure 13.2 needs to be satisfied in order to wr ite to tcnt or tcsr. the transfer instruction writes the lower byte data to tcnt or tc sr according to the satisfied condition. to write to rstcsr, execute a word transfer instruction for address h'ff76. a byte transfer instruction cannot write to rstcsr. the method of writing 0 to the wovf bit differs from that of writing to the rste and rsts bits. to write 0 to the wovf bit, satisfy the condition shown in figure 13.2. if satisfied, the transfer instruction clears the wovf bit to 0, but has no effect on the rste and rsts bits. to write to the rste and rsts bits, satisfy the condition shown in figure 13.2. if satisfied, the transfer instruction writes the values in bits 5 and 6 of the lower byte into the rste and rsts bits, respectively, but has no effect on the wovf bit. section 13 watchdog timer rev. 7.00 sep. 11, 2009 page 310 of 566 rej09b0211-0700 tcnt write writin g to rste and rsts bits tcsr write writin g 0 to wovf bit address: address: 15 8 7 0 h'5a h'ff74 h'ff76 write data 15 8 7 0 h'a5 h'ff74 h'ff76 write data or h'00 figure 13.2 writing to tcnt, tcsr, and rstcsr (example for wdt0) reading tcnt, tcsr, and rstcsr (wdt0) these registers are read in the same way as ot her registers. the read addresses are h'ff74 for tcsr, h'ff75 for tcnt, and h'ff77 for rstcsr. 13.5.2 contention betw een timer counter (tcnt) write and increment if a timer counter clock pulse is generated during the t 2 state of a tcnt write cycle, the write takes priority and the timer counter is not incremented. figure 13.3 shows this operation. address internal write si g nal tcnt input clock tcnt nm t 1 t 2 tcnt write cycle counter write data figure 13.3 contention betw een tcnt write and increment section 13 watchdog timer rev. 7.00 sep. 11, 2009 page 311 of 566 rej09b0211-0700 13.5.3 changing value of cks2 to cks0 if bits cks0 to cks2 in tcsr are written to while the wdt is operating, errors could occur in the incrementation. software must be used to stop the watchdog timer (by clearing the tme bit to 0) before changing the value of bits cks0 to cks2. 13.5.4 switching between watchdog timer mode and interval timer mode if the mode is switched from watchdog timer to interval timer while the wdt is operating, errors could occur in the incrementation. software must be used to stop the watchdog timer (by clearing the tme bit to 0) before switching the mode. 13.5.5 internal reset in watchdog timer mode this lsi is not reset internally if tcnt ove rflows while the rste bit is cleared to 0 during watchdog timer operation, however tcnt and tcsr of the wdt are reset. tcnt, tcsr, or rstcr cannot be written to for 132 states following an overflow. during this period, any attempt to read the wovf flag is not acknowledged. accordingly, wait 132 states after overflow to write 0 to the wovf flag for clearing. 13.5.6 ovf flag clearing in intervel timer mode when the ovf flag setting conflicts with the ovf flag reading in interval timer mode, writing 0 to the ovf bit may not clear the flag even though the ovf bit has been read while it is 1. if there is a possibility that the ovf flag setting and readi ng will conflict, such as when the ovf flag is polled with the intervel timer interrupt disabled, read the ovf bit while it is 1 at least twice before writing 0 to the ovf bit to clear the flag. section 13 watchdog timer rev. 7.00 sep. 11, 2009 page 312 of 566 rej09b0211-0700 section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 313 of 566 rej09b0211-0700 section 14 serial communication interface (sci) this lsi has three independent serial communication interface (sci) channels. the sci can handle both asynchronous and clocked synchronous serial communication. serial data communication can be carried out using standard asynchronous communication chips such as a universal asynchronous receiver/transmitter (uart) or an asynchronous communication interface adapter (acia). a function is also provided for serial communication between processors (multiprocessor communication function) . the sci also supports an ic card (smart card) interface conforming to iso/iec 7816-3 (ide ntification card) as a serial communication interface extension function. figure 14.1 shows a block diagram of the sci. note: no dtc is implemented in the h8s/2614 and h8s/2616. 14.1 features ? choice of asynchronous or clocked synchronous serial communication mode ? full-duplex communication capability the transmitter and receiver are mutually indepe ndent, enabling transmission and reception to be executed simultaneously. double-buffering is used in both the tran smitter and the receiver, enabling continuous transmission and continuous reception of serial data. ? on-chip baud rate generator allows any bit rate to be selected external clock can be selected as a transfer clock source (except for in smart card interface mode). ? choice of lsb-first or msb-first transfer (except in the case of asynchronous mode 7-bit data) ? four interrupt sources transmit-end, transmit-data-empty, receive-dat a-full, and receive error ? that can issue requests. the transmit-data-empty interrupt and receive da ta full interrupts can be used to activate the data transfer controller (dtc). ? module stop mode can be set asynchronous mode ? data length: 7 or 8 bits ? stop bit length: 1 or 2 bits ? parity: even, odd, or none section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 314 of 566 rej09b0211-0700 ? receive error detection: parity , overrun, and framing errors ? break detection: break can be de tected by reading the rxd pin le vel directly in the case of a framing error clocked synchronous mode ? data length: 8 bits ? receive error detection: overrun errors detected smart card interface ? automatic transmission of error signa l (parity error) in receive mode ? error signal detection and automatic data retransmission in transmit mode ? direct convention and inverse convention both supported rxd txd sck clock external clock /4 /16 /64 tei txi rxi eri rsr: rdr: tsr: tdr: smr: scr: ssr: scmr: brr: receive shift re g ister receive data re g ister transmit shift re g ister transmit data re g ister serial mode re g ister serial control re g ister serial status re g ister smart card mode re g ister bit rate re g ister scmr ssr scr smr transmission/ reception control baud rate g enerator brr module data bus bus interface rdr tsr rsr parity g eneration parity check le g end: tdr internal data bus figure 14.1 block diagram of sci section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 315 of 566 rej09b0211-0700 14.2 input/output pins table 14.1 shows the serial pins for each sci channel. table 14.1 pin configuration channel pin name * i/o function sck0 i/o sci0 clock input/output rxd0 input sci0 receive data input 0 txd0 output sci0 transmit data output sck1 i/o sci1 clock input/output rxd1 input sci1 receive data input 1 txd1 output sci1 transmit data output 2 sck2 i/o sci2 clock input/output rxd2 input sci2 receive data input txd2 output sci2 transmit data output note: * pin names sck, rxd, and txd are used in the text for all channels, omitting the channel designation. 14.3 register descriptions the sci has the following register s for each channel. for details on register addresses and register states during each process, refer to appendix a, on-chip i/o register. the serial mode register (smr), serial status register (ssr), and serial control register (scr) are described separately for normal serial communication inte rface mode and smart card inte rface mode because their bit functions differ in part. ? receive shift register (rsr) ? receive data register (rdr) ? transmit data register (tdr) ? transmit shift register (tsr) ? serial mode register (smr) ? serial control register (scr) ? serial status register (ssr) ? smart card mode register (scmr) ? bit rate register (brr) section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 316 of 566 rej09b0211-0700 14.3.1 receive shift register (rsr) rsr is a shift register that is used to receive se rial data input to the rxd pin and convert it into parallel data. when one byte of data has been r eceived, it is transferred to rdr automatically. rsr cannot be directly accessed by the cpu. 14.3.2 receive data register (rdr) rdr is an 8-bit register that stores received da ta. when the sci has received one byte of serial data, it transfers the received serial data from rs r to rdr, where it is st ored. after this, rsr is receive-enabled. as rsr and rdr function as a double buffer in this way, continuous receive operations are possible. after confirming that the rdrf bit in ssr is set to 1, read rdr only once. rdr cannot be written to by the cpu. 14.3.3 transmit data register (tdr) tdr is an 8-bit register that stores data for tran smission. when the sci detects that tsr is empty, it transfers the transmit data written in tdr to tsr and starts transmission. the double-buffered structure of tdr and tsr enables continuous serial transmission. if the next transmit data has already been written to tdr during serial transmission, the sci transfers the written data to tsr to continue transmission. alt hough tdr can be read or written to by the cpu at all times, to achieve reliable serial transmission, write transmit data to tdr only once after confirming that the tdre bit in ssr is set to 1. 14.3.4 transmit shift register (tsr) tsr is a shift register that transmits serial data. to perform serial data transmission, the sci first transfers transmit data from tdr to tsr, then sends the data to the txd pin. tsr cannot be directly accessed by the cpu. section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 317 of 566 rej09b0211-0700 14.3.5 serial mode register (smr) smr is used to set the sci?s serial transfer format and select the ba ud rate generator clock source. some bit functions of smr differ between norma l serial communication interface mode and smart card interface mode. normal serial communication interface mode (when smif in scmr is 0) bit bit name initial value r/w description 7 c/ a 0 r/w communication mode 0: asynchronous mode 1: clocked synchronous mode 6 chr 0 r/w character length (enabled only in asynchronous mode) 0: selects 8 bits as the data length. 1: selects 7 bits as the data length. lsb-first is fixed and the msb of tdr is not transmitted in transmission. in clocked synchronous mode, a fixed data length of 8 bits is used. 5 pe 0 r/w parity enable (enabled only in asynchronous mode) when this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. for a multiprocessor format, parity bit addition and checking are not performed regardless of the pe bit setting. 4 o/ e 0 r/w parity mode (enabled only when the pe bit is 1 in asynchronous mode) 0: selects even parity. 1: selects odd parity. 3 stop 0 r/w stop bit length (enabled only in asynchronous mode) selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits in reception, only the first stop bit is checked. if the second stop bit is 0, it is treated as the start bit of the next transmit character. section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 318 of 566 rej09b0211-0700 bit bit name initial value r/w description 2 mp 0 r/w multiprocessor mode (enabled only in asynchronous mode) when this bit is set to 1, the multiprocessor communication function is enabled. the pe bit and o/ e bit settings are invalid in multiprocessor mode. 1 0 cks1 cks0 0 0 r/w r/w clock select 0 and 1 these bits select the clock source for the baud rate generator. 00: clock (n = 0) 01: /4 clock (n = 1) 10: /16 clock (n = 2) 11: /64 clock (n = 3) for the relationship between the bit rate register setting and the baud rate, see section 14.3.9, bit rate register (brr). n is the decimal representation of the value of n in brr (see section 14.3.9, bit rate register (brr)). section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 319 of 566 rej09b0211-0700 smart card interface mode (when smif in scmr is 1) bit bit name initial value r/w description 7 gm 0 r/w gsm mode when this bit is set to 1, the sci operates in gsm mode. in gsm mode, the timing of the tend setting is advanced by 11.0 etu (elementary time unit: the time for transfer of 1 bit), and clock output control mode addition is performed. for details, refer to section 14.7.8, clock output control. 6 blk 0 r/w when this bit is set to 1, the sci operates in block transfer mode. for details on block transfer mode, refer to section 14.7.3, block transfer mode. 5 pe 0 r/w parity enable (enabled only in asynchronous mode) when this bit is set to 1, the parity bit is added to transmit data in transmission, and the parity bit is checked in reception. in smart card interface mode, this bit must be set to 1. 4 o/ e 0 r/w parity mode (enabled only when the pe bit is 1 in asynchronous mode) 0: selects even parity. 1: selects odd parity. for details on setting this bit in smart card interface mode, refer to section 14.7.2, data format (except for block transfer mode). 3 2 bcp1 bcp0 0 0 r/w r/w basic clock pulse 1 and 2 these bits specify the number of basic clock periods in a 1-bit transfer interval on the smart card interface. 00: 32 clock (s = 32) 01: 64 clock (s = 64) 10: 372 clock (s = 372) 11: 256 clock (s = 256) for details, refer to section 14.7.4, receive data sampling timing and reception margin in smart card interface mode. s stands for the value of s in brr (see section 14.3.9, bit rate register (brr)). section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 320 of 566 rej09b0211-0700 bit bit name initial value r/w description 1 0 cks1 cks0 0 0 r/w r/w clock select 0 and 1 these bits select the clock source for the baud rate generator. 00: clock (n = 0) 01: /4 clock (n = 1) 10: /16 clock (n = 2) 11: /64 clock (n = 3) for the relationship between the bit rate register setting and the baud rate, see section 14.3.9, bit rate register (brr). n is the decimal representation of the value of n in brr (see section 14.3.9, bit rate register (brr)). section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 321 of 566 rej09b0211-0700 14.3.6 serial control register (scr) scr is a register that enables or disables sci transfer operations and interrupt requests, and is also used to selection of the transfer clock source. for details on interrupt requests, refer to section 14.8, interrupts. some bit functions of scr di ffer between normal seri al communication interface mode and smart card interface mode. normal serial communication interface mode (when smif in scmr is 0) bit bit name initial value r/w description 7 tie 0 r/w transmit interrupt enable when this bit is set to 1, the txi interrupt request is enabled. 6 rie 0 r/w receive interrupt enable when this bit is set to 1, rxi and eri interrupt requests are enabled. 5 te 0 r/w transmit enable when this bit s set to 1, transmission is enabled. 4 re 0 r/w receive enable when this bit is set to 1, reception is enabled. 3 mpie 0 r/w multiprocessor interrupt enable (enabled only when the mp bit in smr is 1 in asynchronous mode) when this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the rdrf, fer, and orer status flags in ssr is prohibited. on receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed. for details, refer to section 14.5, multiprocessor communication function. 2 teie 0 r/w transmit end interrupt enable this bit is set to 1, tei interrupt request is enabled. section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 322 of 566 rej09b0211-0700 bit bit name initial value r/w description 1 0 cke1 cke0 0 0 r/w r/w clock enable 0 and 1 selects the clock source and sck pin function. asynchronous mode 00: internal clock sck pin functions as i/o port 01: internal clock outputs a clock of the same frequency as the bit rate from the sck pin. 1x: external clock inputs a clock with a frequency 16 times the bit rate from the sck pin. clocked synchronous mode 0x: internal clock (sck pin functions as clock output) 1x: external clock (sck pin functions as clock input) legend: x: don?t care section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 323 of 566 rej09b0211-0700 smart card interface mode (when smif in scmr is 1) bit bit name initial value r/w description 7 tie 0 r/w transmit interrupt enable when this bit is set to 1, txi interrupt request is enabled. 6 rie 0 r/w receive interrupt enable when this bit is set to 1, rxi and eri interrupt requests are enabled. 5 te 0 r/w transmit enable when this bit is set to 1, transmission is enabled. 4 re 0 r/w receive enable when this bit is set to 1, reception is enabled. 3 mpie 0 r/w multiprocessor interrupt enable (enabled only when the mp bit in smr is 1 in asynchronous mode) write 0 to this bit in smart card interface mode. 2 teie 0 r/w transmit end interrupt enable write 0 to this bit in smart card interface mode. 1 0 cke1 cke0 0 0 r/w clock enable 0 and 1 enables or disables clock output from the sck pin. the clock output can be dynamically switched in gsm mode. for details, refer to section 14.7.8, clock output control. when the gm bit in smr is 0: 00: output disabled (sck pin can be used as an i/o port pin) 01: clock output 1x: reserved when the gm bit in smr is 1: 00: output fixed low 01: clock output 10: output fixed high 11: clock output legend: x: don?t care section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 324 of 566 rej09b0211-0700 14.3.7 serial status register (ssr) ssr is a register containing stat us flags of the sci and multiproce ssor bits for transfer. 1 cannot be written to flags tdre, rdrf, orer, per, and fer; they can only be cleared. some bit functions of ssr differ between normal serial communication interface mode and smart card interface mode. normal serial communication interface mode (when smif in scmr is 0) bit bit name initial value r/w description 7 tdre 1 r/w transmit data register empty displays whether tdr contains transmit data. [setting conditions] ? when the te bit in scr is 0 ? when data is transferred from tdr to tsr and data can be written to tdr [clearing conditions] ? when 0 is written to tdre after reading tdre = 1 ? when the dtc is activated by a txi interrupt request and writes data to tdr 6 rdrf 0 r/w receive data register full indicates that the received data is stored in rdr. [setting condition] ? when serial reception ends normally and receive data is transferred from rsr to rdr [clearing conditions] ? when 0 is written to rdrf after reading rdrf = 1 ? when the dtc is activated by an rxi interrupt and transferred data from rdr the rdrf flag is not affected and retains their previous values when the re bit in scr is cleared to 0. section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 325 of 566 rej09b0211-0700 bit bit name initial value r/w description 5 orer 0 r/w overrun error [setting condition] ? when the next serial reception is completed while rdrf = 1 [clearing condition] ? when 0 is written to orer after reading orer = 1 4 fer 0 r/w framing error [setting condition] ? when the stop bit is 0 [clearing condition] ? when 0 is written to fer after reading fer = 1 in 2-stop-bit mode, only the first stop bit is checked. 3 per 0 r/w parity error [setting condition] ? when a parity error is detected during reception [clearing condition] ? when 0 is written to per after reading per = 1 section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 326 of 566 rej09b0211-0700 bit bit name initial value r/w description 2 tend 1 r transmit end [setting conditions] ? when the te bit in scr is 0 ? when tdre = 1 at transmission of the last bit of a 1-byte serial transmit character [clearing conditions] ? when 0 is written to tdre after reading tdre = 1 ? when the dtc is activated by a txi interrupt and writes data to tdr 1 mpb 0 r multiprocessor bit mpb stores the multiprocessor bit in the receive data. when the re bit in scr is cleared to 0 its previous state is retained. 0 mpbt 0 r/w multiprocessor bit transfer mpbt stores the multiprocessor bit to be added to the transmit data. section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 327 of 566 rej09b0211-0700 smart card interface mode (when smif in scmr is 1) bit bit name initial value r/w description 7 tdre 1 r/w transmit data register empty displays whether tdr contains transmit data. [setting conditions] ? when the te bit in scr is 0 ? when data is transferred from tdr to tsr and data can be written to tdr [clearing conditions] ? when 0 is written to tdre after reading tdre = 1 ? when the dtc is activated by a txi interrupt request and writes data to tdr 6 rdrf 0 r/w receive data register full indicates that the received data is stored in rdr. [setting condition] ? when serial reception ends normally and receive data is transferred from rsr to rdr [clearing conditions] ? when 0 is written to rdrf after reading rdrf = 1 ? when the dtc is activated by an rxi interrupt and transferred data from rdr the rdrf flag is not affected and retains their previous values when the re bit in scr is cleared to 0. section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 328 of 566 rej09b0211-0700 bit bit name initial value r/w description 5 orer 0 r/w overrun error [setting condition] ? when the next serial reception is completed while rdrf = 1 [clearing condition] ? when 0 is written to orer after reading orer = 1 4 ers 0 r/w error signal status [setting condition] ? when the low level of the error signal is sampled [clearing condition] ? when 0 is written to ers after reading ers = 1 3 per 0 r/w parity error [setting condition] ? when a parity error is detected during reception [clearing condition] ? when 0 is written to per after reading per = 1 section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 329 of 566 rej09b0211-0700 bit bit name initial value r/w description 2 tend 1 r transmit end this bit is set to 1 when no error signal has been sent back from the receiving end and the next transmit data is ready to be transferred to tdr. [setting conditions] ? when the te bit in scr is 0 and the ers bit is also 0 ? when the ers bit is 0 and the tdre bit is 1 after the specified interval following transmission of 1- byte data. the timing of bit setting differs according to the register setting as follows: when gm = 0 and blk = 0, 2.5 etu after transmission starts when gm = 0 and blk = 1, 1.5 etu after transmission starts when gm = 1 and blk = 0, 1.0 etu after transmission starts when gm = 1 and blk = 1, 1.0 etu after transmission starts [clearing conditions] ? when 0 is written to tdre after reading tdre = 1 ? when the dtc is activated by a txi interrupt and writes data to tdr 1 mpb 0 r multiprocessor bit this bit is not used in smart card interface mode. 0 mpbt 0 r/w multiprocessor bit transfer write 0 to this bit in smart card interface mode. section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 330 of 566 rej09b0211-0700 14.3.8 smart card mode register (scmr) scmr is a register that selects smar t card interface mode and its format. bit bit name initial value r/w description 7 to 4 ? all 1 ? reserved these bits are always read as 1. 3 sdir 0 r/w smart card data transfer direction selects the serial/parallel conversion format. 0: lsb-first in transfer 1: msb-first in transfer the bit setting is valid only when the transfer data format is 8 bits. for 7-bit data, lsb-first is fixed. 2 sinv 0 r/w smart card data invert specifies inversion of the data logic level. the sinv bit does not affect the logic level of the parity bit. to invert the parity bit, invert the o/ e bit in smr. 0: tdr contents are transmitted as they are. receive data is stored as it is in rdr 1: tdr contents are inverted before being transmitted. receive data is stored in inverted form in rdr 1 ? 1 ? reserved this bit is always read as 1. 0 smif 0 r/w smart card interface mode select this bit is set to 1 to make the sci operate in smart card interface mode. 0: normal asynchronous mode or clocked synchronous mode 1: smart card interface mode section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 331 of 566 rej09b0211-0700 14.3.9 bit rate register (brr) brr is an 8-bit register that adjusts the bit rate. as the sci performs baud rate generator control independently for each channel, different bit rate s can be set for each channel. table 14.2 shows the relationships between the n setting in brr and bit rate b for normal asynchronous mode, clocked synchronous mode, and smart card interface mode. the initial value of brr is h'ff, and it can be read or written to by the cpu at all times. table 14.2 relationships between the n setting in brr and bit rate b mode bit rate error asynchronous mode b = 64 2 2n-1 (n + 1) 10 6 error (%) = { b 64 2 2n-1 (n + 1) ? 1 } 100 10 6 clocked synchronous mode b = 8 2 2n-1 (n + 1) 10 6 ? smart card interface mode b = s 2 2n + 1 (n + 1) 10 6 error (%) = { b s 2 2n + 1 (n + 1) ? 1 } 100 10 6 notes: b: bit rate (bit/s) n: brr setting for baud rate generator (0 n 255) : operating frequency (mhz) n and s: determined by the smr settings shown in the following tables. smr setting smr setting cks1 cks0 n bcp1 bcp0 s 0 0 0 0 0 32 0 1 1 0 1 64 1 0 2 1 0 372 1 1 3 1 1 256 table 14.3 shows sample n settings in brr in normal asynchronous mode. table 14.4 shows the maximum bit rate for each frequency in normal asynchronous mode. table 14.6 shows sample n settings in brr in clocked synchronous mode. table 14.8 shows sample n settings in brr in smart card interface mode. in smar t card interface mode, s (the numb er of basic clock periods in a 1-bit transfer interval) can be selected. for details, refer to section 14.7.4, receive data sampling timing and reception margin in smart card interface mode. tables 14.5 and 14.7 show the maximum bit rates with external clock input. section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 332 of 566 rej09b0211-0700 table 14.3 brr settings for various bit rates (asynchronous mode) operating frequency (mhz) 4 4.9152 5 bit rate (bit/s) n n error (%) n n error (%) n n error (%) 110 2 70 0.03 2 86 0.31 2 88 ?0.25 150 1 207 0.16 1 255 0.00 2 64 0.16 300 1 103 0.16 1 127 0.00 1 129 0.16 600 0 207 0.16 0 255 0.00 1 64 0.16 1200 0 103 0.16 0 127 0.00 0 129 0.16 2400 0 51 0.16 0 63 0.00 0 64 0.16 4800 0 25 0.16 0 31 0.00 0 32 ?1.36 9600 0 12 0.16 0 15 0.00 0 15 1.73 19200 ? ? ? 0 7 0.00 0 7 1.73 31250 0 3 0.00 0 4 ?1.70 0 4 0.00 38400 ? ? ? 0 3 0.00 0 3 1.73 operating frequency (mhz) 6 6.144 7.3728 8 bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 106 ?0.44 2 108 0.08 2 130 ?0.07 2 141 0.03 150 2 77 0.16 2 79 0.00 2 95 0.00 2 103 0.16 300 1 155 0.16 1 159 0.00 1 191 0.00 1 207 0.16 600 1 77 0.16 1 79 0.00 1 95 0.00 1 103 0.16 1200 0 155 0.16 0 159 0.00 0 191 0.00 0 207 0.16 2400 0 77 0.16 0 79 0.00 0 95 0.00 0 103 0.16 4800 0 38 0.16 0 39 0.00 0 47 0.00 0 51 0.16 9600 0 19 ?2.34 0 19 0.00 0 23 0.00 0 25 0.16 19200 0 9 ?2.34 0 9 0.00 0 11 0.00 0 12 0.16 31250 0 5 0.00 0 5 2.40 ? ? ? 0 7 0.00 38400 0 4 ?2.34 0 4 0.00 0 5 0.00 ? ? ? section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 333 of 566 rej09b0211-0700 operating frequency (mhz) 9.8304 10 12 12.288 bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 174 ?0.26 2 177 ?0.25 2 212 0.03 2 217 0.08 150 2 127 0.00 2 129 0.16 2 155 0.16 2 159 0.00 300 1 255 0.00 2 64 0.16 2 77 0.16 2 79 0.00 600 1 127 0.00 1 129 0.16 1 155 0.16 1 159 0.00 1200 0 255 0.00 1 64 0.16 1 77 0.16 1 79 0.00 2400 0 127 0.00 0 129 0.16 0 155 0.16 0 159 0.00 4800 0 63 0.00 0 64 0.16 0 77 0.16 0 79 0.00 9600 0 31 0.00 0 32 ?1.36 0 38 0.16 0 39 0.00 19200 0 15 0.00 0 15 1.73 0 19 ?2.34 0 19 0.00 31250 0 9 ?1.70 0 9 0.00 0 11 0.00 0 11 2.40 38400 0 7 0.00 0 7 1.73 0 9 ?2.34 0 9 0.00 operating frequency (mhz) 14 14.7456 16 17.2032 bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 248 ?0.17 3 64 0.70 3 70 0.03 3 75 0.48 150 2 181 0.13 2 191 0.00 2 207 0.13 2 223 0.00 300 2 90 0.13 2 95 0.00 2 103 0.13 2 111 0.00 600 1 181 0.13 1 191 0.00 1 207 0.13 1 223 0.00 1200 1 90 0.13 1 95 0.00 1 103 0.13 1 111 0.00 2400 0 181 0.13 0 191 0.00 0 207 0.13 0 223 0.00 4800 0 90 0.13 0 95 0.00 0 103 0.13 0 111 0.00 9600 0 45 ?0.93 0 47 0.00 0 51 0.13 0 55 0.00 19200 0 22 ?0.93 0 23 0.00 0 25 0.13 0 27 0.00 31250 0 13 0.00 0 14 ?1.70 0 15 0.00 0 13 1.20 38400 ? ? ? 0 11 0.00 0 12 0.13 0 13 0.00 section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 334 of 566 rej09b0211-0700 operating frequency (mhz) 18 19.6608 20 bit rate (bit/s) n n error (%) n n error (%) n n error (%) 110 3 79 ?0.12 3 86 0.31 3 88 ?0.25 150 2 233 0.16 2 255 0.00 3 64 0.16 300 2 116 0.16 2 127 0.00 2 129 0.16 600 1 233 0.16 1 255 0.00 2 64 0.16 1200 1 116 0.16 1 127 0.00 1 129 0.16 2400 0 233 0.16 0 255 0.00 1 64 0.16 4800 0 116 0.16 0 127 0.00 0 129 0.16 9600 0 58 ?0.69 0 63 0.00 0 64 0.16 19200 0 28 1.02 0 31 0.00 0 32 ?1.36 31250 0 17 0.00 0 19 ?1.70 0 19 0.00 38400 0 14 ?2.34 0 15 0.00 0 15 1.73 table 14.4 maximum bit rate for each frequency (asynchronous mode) (mhz) maximum bit rate (bit/s) n n (mhz) maximum bit rate (bit/s) n n 4 125000 0 0 12 375000 0 0 4.9152 153600 0 0 12.288 384000 0 0 5 156250 0 0 14 437500 0 0 6 187500 0 0 14.7456 460800 0 0 6.144 192000 0 0 16 500000 0 0 7.3728 230400 0 0 17.2032 537600 0 0 8 250000 0 0 18 562500 0 0 9.8304 307200 0 0 19.6608 614400 0 0 10 312500 0 0 20 625000 0 0 section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 335 of 566 rej09b0211-0700 table 14.5 maximum bit rate with external clock input (asynchronous mode) (mhz) external input clock (mhz) maximum bit rate (bit/s) (mhz) external input clock (mhz) maximum bit rate (bit/s) 4 1.0000 62500 12 3.0000 187500 4.9152 1.2288 76800 12.288 3.0720 192000 5 1.2500 78125 14 3.5000 218750 6 1.5000 93750 14.7456 3.6864 230400 6.144 1.5360 96000 16 4.0000 250000 7.3728 1.8432 115200 17.2032 4.3008 268800 8 2.0000 125000 18 4.5000 281250 9.8304 2.4576 153600 19.6608 4.9152 307200 10 2.5000 156250 20 5.0000 312500 section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 336 of 566 rej09b0211-0700 table 14.6 brr settings for various bit rates (clocked synchronous mode) operating frequency (mhz) 4 8 10 16 20 bit rate (bit/s) n n n n n n n n n n 110 ? ? 250 2 249 3 124 ? ? 3 249 500 2 124 2 249 ? ? 3 124 ? ? 1k 1 249 2 124 ? ? 2 249 ? ? 2.5k 1 99 1 199 1 249 2 99 2 124 5k 0 199 1 99 1 124 1 199 1 249 10k 0 99 0 199 0 249 1 99 1 124 25k 0 39 0 79 0 99 0 159 0 199 50k 0 19 0 39 0 49 0 79 0 99 100k 0 9 0 19 0 24 0 39 0 49 250k 0 3 0 7 0 9 0 15 0 19 500k 0 1 0 3 0 4 0 7 0 9 1m 0 0 * 0 1 0 3 0 4 2.5m 0 0 * 0 1 5m 0 0 * legend: blank: cannot be set. ?: can be set, but there will be a degree of error. * : continuous transfer is not possible. table 14.7 maximum bit rate with external clock input (clocked synchronous mode) (mhz) external input clock (mhz) maximum bit rate (bit/s) (mhz) external input clock (mhz) maximum bit rate (bit/s) 4 0.6667 666666.7 14 2.3333 2333333.3 6 1.0000 1.000000.0 16 2.6667 2666666.7 8 1.3333 1333333.3 18 3.0000 3000000.0 10 1.6667 1666666.7 20 3.3333 3333333.3 12 2.0000 2000000.0 section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 337 of 566 rej09b0211-0700 table 14.8 examples of bit rate for variou s brr settings (smart card interface mode) (when n = 0 and s = 372) operating frequency (mhz) 7.1424 10.00 10.7136 13.00 bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 9600 0 0 0.00 0 1 30 0 1 25 0 1 8.99 operating frequency (mhz) 14.2848 16.00 18.00 20.00 bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 9600 0 1 0.00 0 1 12.01 0 2 15.99 0 2 6.60 table 14.9 maximum bit rate at various f requencies (smart card interface mode) (when s = 372) (mhz) maximum bit rate (bit/s) n n (mhz) maximum bit rate (bit/s) n n 7.1424 9600 0 0 14.2848 19200 0 0 10.00 13441 0 0 16.00 21505 0 0 10.7136 14400 0 0 18.00 24194 0 0 13.00 17473 0 0 20.00 26882 0 0 section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 338 of 566 rej09b0211-0700 14.4 operation in as ynchronous mode figure 14.2 shows the general format for asynchronous serial communication. one frame consists of a start bit (low level), followed by data (in lsb-first order), a parity bit (high or low level), and finally stop bits (high level). in asynchronous serial communication, the transmission line is usually held in the mark state (high level). the sci monitors the transmission line. when the transmission line goes to the space state (low level), the sci recognizes a start bit and starts serial communication. in asynchronous serial communication, the communication line is usually held in the mark state (high level). the sci monitors the communication line, and when it goes to the space state (low level), recognizes a start bit and st arts serial communication. inside the sci, the transmitter and receiver are independent units, en abling full-duplex. both the transmitter and the receiver also have a double-buffered structure, so data can be read or written during transmission or reception, enabling con tinuous data transfer. lsb start bit msb idle state (mark state) stop bit 0 transmit/receive data d0 d1 d2 d3 d4 d5 d6 d7 0/1 1 1 1 1 serial data parity bit 1 bit 1 or 2 bit 7 or 8 bit 1 bit, or none one unit of transfer data (character or frame) figure 14.2 data format in asynchronous communication (example with 8-bit data, parity, two stop bits) 14.4.1 data transfer format table 14.10 shows the data transfer formats that can be used in asynchronous mode. any of 12 transfer formats can be selected according to the smr setting. for details on the multiprocessor bit, refer to section 14.5, multiprocessor communication function. section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 339 of 566 rej09b0211-0700 table 14.10 serial transfer formats (asynchronous mode) pe 0 0 1 1 0 0 1 1 ? ? ? ? s 8-bit data stop s 7-bit data stop s 8-bit data stop stop s 8-bit data p stop s 7-bit data stop p s 8-bit data mpb stop s 8-bit data mpb stop stop s 7-bit data stop mpb s 7-bit data stop mpb stop s 7-bit data stop stop chr 0 0 0 0 1 1 1 1 0 0 1 1 mp 0 0 0 0 0 0 0 0 1 1 1 1 stop 0 1 0 1 0 1 0 1 0 1 0 1 smr settin g s 123456789101112 serial transfer format and frame len g th stop s 8-bit data p stop s 7-bit data stop p stop legend: s: start bit stop: stop bit p: parity bit mpb: multiprocessor bit section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 340 of 566 rej09b0211-0700 14.4.2 receive data sampling timing and reception margin in asynchronous mode in asynchronous mode, the sci operates on a basic clock with a frequency of 16 times the transfer rate. in reception, the sci samples the falling edge of the start bit using the basic clock, and performs internal synchronization. receive data is latched internally at the rising edge of the 8th pulse of the basic clock as shown in figure 14.3. thus, the reception margin in asynchronous mode is given by formula (1) below. m = { (0. 5 ? ) ?? (l ? 0. 5 ) f } 100 [%] 1 2n d ? 0. 5 n ... formula (1) where m : reception margin n : ratio of bit rate to clock (n = 16) d : clock duty (d = 0.5 to 1.0) l : frame length (l = 9 to 12) f : absolute value of clock rate deviation assuming values of f (absolute value of clock rate deviation) = 0 and d (clock duty) = 0.5 in formula (1), the reception margin can be given by the formula. m = {0.5 ? 1/(2 16)} 100 [%] = 46.875% however, this is only the computed value, and a margin of 20% to 30% should be allowed for in system design. internal basic clock 16 clocks 8 clocks receive data (rxd) synchronization samplin g timin g start bit d0 d1 data samplin g timin g 15 0 7 15 0 07 figure 14.3 receive data samplin g timing in asynchronous mode section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 341 of 566 rej09b0211-0700 14.4.3 clock either an internal clock generated by the on-chip baud rate generator or an external clock input at the sck pin can be selected as the sci?s se rial clock, according to the setting of the c/ a bit in smr and the cke0 and cke1 bits in scr. when an external clock is input at the sck pin, the clock frequency should be 16 times the bit rate used. when the sci is operated on an internal clock, the clock can be output from the sck pin. the frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 14.4. 0 1 frame d0 d1 d2 d3 d4 d5 d6 d7 0/1 11 sck txd figure 14.4 relationship between output clock and transfer data phase (asynchronous mode) section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 342 of 566 rej09b0211-0700 14.4.4 sci initialization (asynchronous mode) before transmitting and receiving data, you should firs t clear the te and re bits in scr to 0, then initialize the sci as described below. when the operating mode, or transfer format, is changed for example, the te and re bits must be cleared to 0 before making the change using the following procedure. when the te bit is cleared to 0, the tdre flag is set to 1. note that clearing the re bit to 0 does not initialize the contents of the rdrf, per, fer, and orer flags, or the contents of rdr. when the external clock is used in async hronous mode, the clock must be supplied even during initialization. wait section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 343 of 566 rej09b0211-0700 14.4.5 data transmission (asynchronous mode) figure 14.6 shows an example of operation for transmission in asynchronous mode. in transmission, the sci operates as described below. 1. the sci monitors the tdre flag in ssr. if the flag is cleared to 0, the sci recognizes that data has been written to tdr, and transfers the data from tdr to tsr. 2. after transferring data from tdr to tsr, the sci sets the tdre flag to 1 and starts transmission. if the tie bit is set to 1 at this time, a transmit data empty interrupt request (txi) is generated. continuous transmission is possibl e because the txi interr upt routine writes next transmit data to tdr before transmission of the current transmit data has been completed. 3. data is sent from the txd pin in the following order: start bit, transmit data, parity bit or multiprocessor bit (may be omitted depending on the format), and stop bit. 4. the sci checks the tdre flag at the timing for sending the stop bit. 5. if the tdre flag is 0, the data is transferred from tdr to tsr, the stop bit is sent, and then serial transmission of the next frame is started. 6. if the tdre flag is 1, the tend flag in ssr is set to 1, the stop bit is sent, and then the ?mark state? is entered, in which 1 is output. if the te ie bit in scr is set to 1 at this time, a tei interrupt request is generated. figure 14.7 shows a sample flowchart for transmission in asynchronous mode. tdre tend 0 1 frame d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 1 1 1 data start bit parity bit stop bit start bit data parity bit stop bit txi interrupt request g enerated data written to tdr and tdre fla g cleared to 0 in txi interrupt service routine tei interrupt request g enerated idle state (mark state) txi interrupt request g enerated figure 14.6 example of operation in transmission in asynchronous mode (example with 8-bit data, parity, one stop bit) section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 344 of 566 rej09b0211-0700 no section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 345 of 566 rej09b0211-0700 14.4.6 serial data recepti on (asynchronous mode) figure 14.8 shows an example of operation fo r reception in asynchronous mode. in serial reception, the sci operates as described below. 1. the sci monitors the communication line. if a start bit is detected, the sci performs internal synchronization, receives receive data in rs r, and checks the parity bit and stop bit. 2. if an overrun error occurs (when reception of th e next data is completed while the rdrf flag is still set to 1), the orer bit in ssr is set to 1. if the rie bit in scr is set to 1 at this time, an eri interrupt request is generated. receive data is not transferred to rdr. the rdrf flag remains to be set to 1. 3. if a parity error is detected, the per bit in ssr is set to 1 and receive data is transferred to rdr. if the rie bit in scr is set to 1 at this time, an eri interrupt request is generated. 4. if a framing error is detected (when the stop bit is 0), the fer bit in ssr is set to 1 and receive data is transferred to rdr. if the rie bit in scr is set to 1 at this time, an eri interrupt request is generated. 5. if reception is completed succe ssfully, the rdrf bit in ssr is set to 1, and receive data is transferred to rdr. if the rie bit in scr is set to 1 at this time, an rxi interrupt request is generated. continuous reception is possible becau se the rxi interrupt r outine reads the receive data transferred to rdr before reception of the next receive data has been completed. rdrf fer 0 1 frame d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 0 1 1 data start bit parity bit stop bit start bit data parity bit stop bit eri interrupt request g enerated by framin g error idle state (mark state) rdr data read and rdrf fla g cleared to 0 in rxi interrupt service routine rxi interrupt request g enerated figure 14.8 example of sc i operation in reception (example with 8-bit data, parity, one stop bit) section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 346 of 566 rej09b0211-0700 table 14.11 shows the states of the ssr status flags and receive data handling when a receive error is detected. if a receive e rror is detected, the rdrf flag retains its state before receiving data. reception cannot be resumed while a receive e rror flag is set to 1. accordingly, clear the orer, fer, per, and rdrf bits to 0 before resuming reception. figure 14.9 shows a sample flowchart for serial data reception. table 14.11 ssr status flags and receive data handling ssr status flag rdrf * orer fer per receive data receive error type 1 1 0 0 lost overrun error 0 0 1 0 transferred to rdr framing error 0 0 0 1 transferred to rdr parity error 1 1 1 0 lost overrun error + framing error 1 1 0 1 lost overrun error + parity error 0 0 1 1 transferred to rdr framing error + parity error 1 1 1 1 lost overrun error + framing error + parity error note: * the rdrf flag retains the state it had before data reception. section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 347 of 566 rej09b0211-0700 yes section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 348 of 566 rej09b0211-0700 section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 349 of 566 rej09b0211-0700 14.5 multiprocessor comm unication function use of the multiprocessor communication function enables data transfer between a number of processors sharing communication lines by asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. when multiprocessor communication is performed, each receiving station is addressed by a unique id code. the serial communica tion cycle consists of two component cycles; an id transmission cycle that specifies the receiving station, and a data tr ansmission cycle. the multiprocessor bit is used to differentiate between the id transmission cy cle and the data transmission cycle. if the multiprocessor bit is 1, the cycle is an id transmission cycle; if the multiprocessor bit is 0, the cycle is a data transmission cycle. figure 14.10 shows an example of inter-processor communication using the multiprocessor format. the transmitting station first sends the id code of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. it then sends transmit data as data with a 0 multiprocessor bit added. when data with a 1 multiprocessor bit is received, the receiving station compares that data with its own id. the station whose id matc hes then receives the data sent next. stations whose ids do not match continue to skip data until data with a 1 multiprocessor bit is again received. the sci uses the mpie bit in scr to implement this function. when the mpie bit is set to 1, transfer of receive data from rsr to rdr, error flag detection, and setting the ssr status flags, rdrf, fer, and orer to 1, are inhibited until data with a 1 multiprocessor bit is received. on reception of a receive character with a 1 multiprocessor bit, the mpb bit in ssr is set to 1 and the mpie bit is automatically cleared, t hus normal reception is resumed. if the rie bit in scr is set to 1 at this time, an rxi interrupt is generated. when the multiprocessor format is selected, the parity bit setting is rendered invalid. all other bit settings are the same as those in normal asynchronous mode. the clock used for multiprocessor communication is the same as that in normal asynchronous mode. section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 350 of 566 rej09b0211-0700 transmittin g station receivin g station a receivin g station b receivin g station c receivin g station d (id = 01) (id = 02) (id = 03) (id = 04) serial transmission line serial data id transmission cycle = receivin g station specification data transmission cycle = data transmission to receivin g station specified by id (mpb = 1) (mpb = 0) h'01 h'aa le g end: mpb: multiprocessor bit figure 14.10 example of communication using multiprocessor format (transmission of data h'aa to receiving station a) 14.5.1 multiprocessor serial data transmission figure 14.11 shows a sample flowchart for multiprocessor serial data transmission. for an id transmission cycle, set the mpbt bit in ssr to 1 before transmission. for a data transmission cycle, clear the mpbt b it in ssr to 0 before transmission. all other sci operations are the same as those in asynchronous mode. section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 351 of 566 rej09b0211-0700 no section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 352 of 566 rej09b0211-0700 14.5.2 multiprocessor s erial data reception figure 14.13 shows a sample flowchart for multiprocessor serial data reception. if the mpie bit in scr is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. on receiving data with a 1 multiprocessor bit, the receive data is tr ansferred to rdr. an rxi interrupt request is generated at this time. all other sci operations are the same as in asynchronous mode. figure 14.12 shows an example of sci operation for multiprocessor format reception. mpie rdr value 0 d0 d1 d7 1 1 0 d0 d1 d7 0 1 1 1 data (id1) start bit mpb stop bit start bit data (data1) mpb stop bit data (id2) start bit stop bit start bit data (data2) stop bit rxi interrupt request (multiprocessor interrupt) g enerated idle state (mark state) rdrf rdr data read and rdrf fla g cleared to 0 in rxi interrupt service routine if not this station?s id, mpie bit is set to 1 a g ain rxi interrupt request is not g enerated, and rdr retains its state id1 (a) data does not match station?s id mpie rdr value 0 d0 d1 d7 1 1 0 d0 d1 d7 0 1 1 1 mpb mpb rxi interrupt request (multiprocessor interrupt) g enerated idle state (mark state) rdrf rdr data read and rdrf fla g cleared to 0 in rxi interrupt service routine matches this station?s id, so reception continues, and data is received in rxi interrupt service routine mpie bit set to 1 a g ain id2 (b) data matches station?s id data2 id1 mpie = 0 mpie = 0 figure 14.12 example of sci operation in reception (example with 8-bit data, multiprocessor bit, one stop bit) section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 353 of 566 rej09b0211-0700 yes section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 354 of 566 rej09b0211-0700 section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 355 of 566 rej09b0211-0700 14.6 operation in clocke d synchronous mode figure 14.14 shows the general format for clocked synchronous communication. in clocked synchronous mode, data is transmitted or receive d synchronous with clock pulses. in clocked synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. in clocked synchronous mode, the sc i receives data in synchronous with the rising edge of the serial clock. after 8-bit data is output, the transmission line holds the msb state. in clocked synchronous mode, no parity or multiprocessor bit is added. inside the sci, the transmitter and receiver are independent units, enabling full-duplex communication through the use of a common clock. both the transmitter and the receiver also have a double-buffered structure, so data can be read or written during transmission or reception, enabling continuous data transfer. don?t care don?t care one unit of transfer data (character or frame) bit 0 serial data synchronization clock bit 1 bit 3 bit 4 bit 5 lsb msb bit 2 bit 6 bit 7 * * note: * hi g h except in continuous transfer figure 14.14 data format in synchronous communication (for lsb-first) 14.6.1 clock either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the sck pin can be selected, according to the setting of cke0 and cke1 bits in scr. when the sci is operated on an internal clock, the serial clock is output from the sck pin. eight serial clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 356 of 566 rej09b0211-0700 14.6.2 sci initialization (clocked synchronous mode) before transmitting and receiving data, the te and re bits in scr should be cl eared to 0, then the sci should be initialized as described in a samp le flowchart in figure 14.15. when the operating mode, or transfer format, is changed for example, the te and re bits must be cleared to 0 before making the change using the following procedure. wh en the te bit is cleared to 0, the tdre flag is set to 1. note that clearing the re bit to 0 does not change the contents of the rdrf, per, fer, and orer flags, or the contents of rdr. wait section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 357 of 566 rej09b0211-0700 14.6.3 serial data transmission (clocked synchronous mode) figure 14.16 shows an example of sci operation for transmission in clocked synchronous mode. in serial transmission, the sci operates as described below. 1. the sci monitors the tdre flag in ssr, and if the flag is 0, the sci recognizes that data has been written to tdr, and transfers the data from tdr to tsr. 2. after transferring data from tdr to tsr, the sci sets the tdre flag to 1 and starts transmission. if the tie bit in scr is set to 1 at this time, a transmit data empty interrupt (txi) is generated. continuous transmission is possi ble because the txi inte rrupt routine writes the next transmit data to tdr before transmission of the current transmit data has been completed. 3. 8-bit data is sent from the txd pin synchronized with the output clock when output clock mode has been specified, and synchronized with the input clock when use of an external clock has been specified. 4. the sci checks the tdre flag at the timing for sending the msb (bit 7). 5. if the tdre flag is cleared to 0, data is tr ansferred from tdr to tsr, and serial transmission of the next frame is started. 6. if the tdre flag is set to 1, the tend flag in ssr is set to 1, and the tdre flag maintains the output state of the last bit. if the teie bit in scr is set to 1 at this time, a tei interrupt request is generated. the sck pin is fixed high. figure 14.17 shows a sample flow chart for serial data transmission. even if the tdre flag is cleared to 0, transmission will not start while a receive error flag (orer, fer, or per) is set to 1. make sure that the receive error flags are cleared to 0 before starting transmission. note that clearing the re bit to 0 does not clear the receive error flags. section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 358 of 566 rej09b0211-0700 transfer direction bit 0 serial data synchronization clock 1 frame tdre tend data written to tdr and tdre fla g cleared to 0 in txi interrupt service routine txi interrupt request g enerated bit 1 bit 7 bit 0 bit 1 bit 6 bit 7 txi interrupt request g enerated tei interrupt request g enerated figure 14.16 sample sci transmission operation in clocked synchronous mode section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 359 of 566 rej09b0211-0700 no section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 360 of 566 rej09b0211-0700 14.6.4 serial data reception (clocked synchronous mode) figure 14.18 shows an example of sci operation for reception in clocked synchronous mode. in serial reception, the sci operates as described below. 1. the sci performs internal initialization synchronous with a synchronous clock input or output, starts receiving data, and stores the received data in rsr. 2. if an overrun error occurs (when reception of th e next data is completed while the rdrf flag in ssr is still set to 1), the orer bit in ssr is set to 1. if the rie bit in scr is set to 1 at this time, an eri interrupt request is generated, r eceive data is not transferred to rdr, and the rdrf flag remains to be set to 1. 3. if reception is completed succe ssfully, the rdrf bit in ssr is set to 1, and receive data is transferred to rdr. if the rie bit in scr is set to 1 at this time, an rxi interrupt request is generated. continuous reception is possible becau se the rxi interrupt r outine reads the receive data transferred to rdr before reception of the next receive data has finished. bit 7 serial data synchronization clock 1 frame rdrf orer eri interrupt request g enerated by overrun error rxi interrupt request g enerated rdr data read and rdrf fla g cleared to 0 in rxi interrupt service routine rxi interrupt request g enerated bit 0 bit 7 bit 0 bit 1 bit 6 bit 7 figure 14.18 example of sci operation in reception reception cannot be resumed while a receive error fl ag is set to 1. accordingly, clear the orer, fer, per, and rdrf bits to 0 before resuming reception. figure 14.19 shows a sample flow chart for serial data reception. section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 361 of 566 rej09b0211-0700 yes section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 362 of 566 rej09b0211-0700 14.6.5 simultaneous serial data transmission and reception (clocked synchronous mode) figure 14.20 shows a sample flowchart for simulta neous serial transmit and receive operations. the following procedure should be used for simultaneous serial data transmit and receive operations. to switch from transmit mode to simultaneous transmit and receive mode, after checking that the sci has finished transmission and the tdre and tend flags are set to 1, clear te to 0. then simultaneously set te and re to 1 w ith a single instruction. to switch from receive mode to simultaneous transmit and receive m ode, after checking that the sci has finished reception, clear re to 0. then after checking that the rdrf and receive error flags (orer, fer, and per) are cleared to 0, simultaneously se t te and re to 1 with a single instruction. section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 363 of 566 rej09b0211-0700 yes section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 364 of 566 rej09b0211-0700 14.7 operation in smar t card interface the sci supports an ic card (smart card) interface that conforms to iso/iec 7816-3 (identification card) as a seri al communication interface extens ion function. switching between the normal serial communication interface and the smart card interface mode is carried out by means of a register setting. 14.7.1 pin connection example figure 14.21 shows an example of connection with the smart card. in communication with an ic card, as both transmission and reception are carried out on a single data transmission line, the txd pin and rxd pin should be connected to the lsi pin. the data transmission line should be pulled up to the v cc power supply with a resistor. if an ic card is not connected, and the te and re bits are both set to 1, closed transmission/reception is possible, enabling self-diagnosis to be carried out. when the clock generated on the smart card interface is used by an ic card, the sck pin output is input to the clk pin of the ic card. this lsi port output is used as the reset signal. txd rxd this lsi v cc i/o connected equipment ic card data line clock line reset line clk rst sck rx (port) figure 14.21 schematic diagram of smart card interfa ce pin connections section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 365 of 566 rej09b0211-0700 14.7.2 data format (except for block transfer mode) figure 14.22 shows the transfer data format in smart card interface mode. ? one frame consists of 8-bit data plus a parity bit in asynchronous mode. ? in transmission, a guard time of at least 2 etu (elementary time unit: the time for transfer of 1 bit) is left between the end of the parity bit and the start of the next frame. ? if a parity error is detected during reception, a low error signal level is output for one etu period, 10.5 etu after the start bit. ? if an error signal is sampled during transmission, the same data is retransmitted automatically after a delay of 2 etu or longer. ds d0 d1 d2 d3 d4 d5 d6 d7 dp when there is no parity error transmittin g station output ds d0 d1 d2 d3 d4 d5 d6 d7 dp when a parity error occurs transmittin g station output de receivin g station output start bit data bits parity bit error si g nal le g end: ds: d0 to d7: dp: de: figure 14.22 normal smart card interface data format data transfer with other types of ic cards (direct convention and inverse convention) are performed as described in the following. ds azzazz z za a (z) (z) state d0 d1 d2 d3 d4 d5 d6 d7 dp figure 14.23 direct conv ention (sdir = sinv = o/ e = 0) section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 366 of 566 rej09b0211-0700 with the direction convention type ic and the above sample start character, the logic 1 level corresponds to state z and the logic 0 level to state a, and transfer is performed in lsb-first order. the start character data above is h'3b. for the direct convention type, clear the sdir and sinv bits in scmr to 0. according to smart card regulations, clear the o/ e bit in smr to 0 to select even parity mode. ds azzaaa z aa a (z) (z) state d7 d6 d5 d4 d3 d2 d1 d0 dp figure 14.24 inverse convention (sdir = sinv = o/ e = 1) with the inverse convention type, the logic 1 level corresponds to state a and the logic 0 level to state z, and transfer is performed in msb-first order. the start character data for the above is h'3f. for the inverse convention type, set the sdir and sinv bits in scmr to 1. according to smart card regulations, even parity mode is the logic 0 level of the parity bit, and corresponds to state z. in this lsi, the sinv bit inverts only data bits d0 to d7. therefore, set the o/ e bit in smr to 1 to invert the parity bit for both transmission and reception. 14.7.3 block transfer mode operation in block transfer mode is the same as that in sci asynchronous mode, except for the following points. ? in reception, though the parity ch eck is performed, no error signal is output even if an error is detected. however, the per bit in ssr is set to 1 and must be cleared before receiving the parity bit of the next frame. ? in transmission, a guard time of at least 1 etu is left between the end of the parity bit and the start of the next frame. ? in transmission, because retransmission is not pe rformed, the tend flag is set to 1, 11.5 etu after transmission start. ? as with the normal smart card interface, the ers flag indicates the error signal status, but since error signal transfer is not performed , this flag is always cleared to 0. section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 367 of 566 rej09b0211-0700 14.7.4 receive data sampling timing and reception margin in smart card interface mode in smart card interface mode, the sci operates on a basic clock with a frequency of 32, 64, 372, or 256 times the transfer rate (fixed at 16 times in normal asynchronous mode) as determined by bits bcp1 and bcp0. in reception, the sci samples the falling edge of the start bit using the basic clock, and performs internal s ynchronization. as shown in figure 14.25, by sampling receive data at the rising-edge of the 16th, 32nd, 186th, or 128th pulse of the basic clock, data can be latched at the middle of the bit. the reception margin is given by the following formula. m = | (0. 5 ? ) ? (l ? 0. 5 ) f ? (1 + f ) | 100% 1 2n | d ? 0. 5 | n where m: reception margin (%) n: ratio of bit rate to clock (n = 32, 64, 372, and 256) d: clock duty (d = 0 to 1.0) l: frame length (l = 10) f: absolute value of clock frequency deviation assuming values of f = 0, d = 0.5 and n = 372 in the above formula, the reception margin formula is as follows. m = (0.5 ? 1/2 372) 100% = 49.866% section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 368 of 566 rej09b0211-0700 internal basic clock 372 clocks 186 clocks receive data (rxd) synchronization samplin g timin g d0 d1 data samplin g timin g 185 371 0 371 185 0 0 start bit figure 14.25 receive data samp ling timing in smart card mode (using clock of 372 times the transfer rate) 14.7.5 initialization before transmitting and receiving data, initialize the sci as described below. initialization is also necessary when switching from transmit mode to receive mode, or vice versa. 1. clear the te and re bits in scr to 0. 2. clear the error flags ers, per, and orer in ssr to 0. 3. set the gm, blk, o/ e , bcp0, bcp1, cks0, cks1 bits in smr. set the pe bit to 1. 4. set the smif, sdir, and sinv bits in scmr. when the smif bit is set to 1, the txd and rxd pins are both switched from ports to sci pins, and are placed in the high-impedance state. 5. set the value corresponding to the bit rate in brr. 6. set the cke0 and cke1 bits in scr. clear th e tie, rie, te, re, mpie, and teie bits to 0. if the cke0 bit is set to 1, the clock is output from the sck pin. 7. wait at least one bit interval, then set the tie, rie, te, and re bits in scr. do not set the te bit and re bit at the same time, except for self-diagnosis. to switch from receive mode to transmit mode, afte r checking that the sci has finished reception, initialize the sci, and set re to 0 and te to 1. whether sci has finished reception or not can be checked with the rdrf, per, or orer flags. to switch from transmit mode to receive mode, section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 369 of 566 rej09b0211-0700 after checking that the sci has finished transmission, initialize the sci, and set te to 0 and re to 1. whether sci has finished transmission or not can be checked with the tend flag. 14.7.6 data transmission (except for block transfer mode) as data transmission in smart card interf ace mode involves error signal sampling and retransmission processing, the operations are different from those in normal serial communication interface mode (except for block transfer mode). figure 14.26 illustrates the retransfer operation when the sci is in transmit mode. 1. if an error signal is sent back from the receiving end after transmission of one frame is complete, the ers bit in ssr is set to 1. if the rie bit in scr is enabled at this time, an eri interrupt request is generated. the ers bit in ssr should be kept cleared to 0 until the next parity bit is sampled. 2. the tend bit in ssr is not set for a frame in which an error signal indicating an abnormality is received. data is retransferred from td r to tsr, and retransmitted automatically. 3. if an error signal is not sent back from th e receiving end, the ers bit in ssr is not set. transmission of one frame, including a retransfer, is judged to have been completed, and the tend bit in ssr is set to 1. if the tie bit in scr is enabled at this time, a txi interrupt request is generated. writing transmit data to tdr transfers the next transmit data. figure 14.28 shows a flowchart for transmission. the sequence of transmit operations can be performed automatically by specifying the dtc to be activated with a txi interrupt source. in a transmit operation, the tdre flag is set to 1 at the same time as the tend flag in ssr is set, and a txi interrupt will be generated if the tie bit in scr has been set to 1. if the txi request is designated beforehand as a dtc activation source, the dtc will be activated by the txi request, and transfer of the transmit data will be carried out. the tdre and tend flags are automatically cleared to 0 when data is transferred by the dtc. in the event of an error, the sci retransmits the same data automatically. during this period, the tend flag remains cleared to 0 and the dtc is not activated. therefore, the sci and dtc will automatically transmit the specified number of bytes in the event of an error, including retran smission. however, the ers flag is not cleared automatically when an error occurs, and so the rie bit should be set to 1 beforehand so that an eri request will be generated in the event of an error, and the ers flag will be cleared. when performing transfer using the dtc, it is essential to set and enable the dtc before carrying out sci setting. for details of the dtc setting procedures, refer to section 8, data transfer controller (dtc). section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 370 of 566 rej09b0211-0700 d0 d1 d2 d3 d4 d5 d6 d7 dp de ds d0 d1 d2 d3 d4 d5 d6 d7 dp (de) ds d0 d1 d2 d3 d4 ds transfer frame n+1 retransferred frame nth transfer frame tdre tend [1] fer/ers transfer to tsr from tdr transfer to tsr from tdr transfer to tsr from tdr [2] [3] [3] figure 14.26 retransfer operation in sci transmit mode the timing for setting the tend flag depends on the value of the gm bit in smr. the tend flag set timing is shown in figure 14.27. ds d0 d1 d2 d3 d4 d5 d6 d7 dp i/o data note: etu: elementary time unit (time for transfer of 1 bit) 12.5 etu txi (tend interrupt) 11.0 etu de guard time when gm = 0 when gm = 1 start bit data bits parity bit error si g nal le g end: ds: d0 to d7: dp: de: figure 14.27 tend flag generation timing in transmission operation section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 371 of 566 rej09b0211-0700 initialization no yes clear te bit to 0 start transmission start no no no yes yes yes yes no end write data to tdr, and clear tdre fla g in ssr to 0 error processin g error processin g tend = 1? all data transmitted ? tend = 1? ers = 0? ers = 0? figure 14.28 example of transmission processing flow 14.7.7 serial data r eception (except for block transfer mode) data reception in smart card interface mode uses the same operation procedure as for normal serial communication interface mode. figure 14.29 illustrates the retransfer operation when the sci is in receive mode. 1. if an error is found when the received pa rity bit is ch ecked, the per bit in ssr is automatically set to 1. if the rie bit in scr is set at this time, an eri interrupt request is generated. the per bit in ssr should be kept clear ed to 0 until the next pa rity bit is sampled. section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 372 of 566 rej09b0211-0700 2. the rdrf bit in ssr is not set for a frame in which an error has occurred. 3. if no error is found when the received parity bit is checked, the per bit in ssr is not set to 1, the receive operation is judged to have been completed normally , and the rdrf flag in ssr is automatically set to 1. if the rie bit in scr is enabled at this time, an rxi interrupt request is generated. figure 14.30 shows a flowchart for reception. a se quence of receive operations can be performed automatically by specifying the dtc to be activated using an rxi interrupt source. in a receive operation, an rxi interrupt request is generated when the rdrf flag in ssr is set to 1. if the rxi request is designated beforehand as a dtc activation source, the dtc will be activated by the rxi request, and the receive data will be transferre d. the rdrf flag is cleared to 0 automatically when data is transferred by the dtc. if an er ror occurs in receive mode and the orer or per flag is set to 1, a transfer error interrupt (eri) request will be generated. hence, so the error flag must be cleared to 0. in the event of an error, th e dtc is not activated and receive data is skipped. therefore, receive data is transferred for only th e specified number of bytes in the event of an error. even when a parity error o ccurs in receive mode and the per fl ag is set to 1, the data that has been received is transferred to rdr and can be read from there. note: for details on receive operations in block tran sfer mode, refer to section 14.4, operation in asynchronous mode. d0 d1 d2 d3 d4 d5 d6 d7 dp de ds d0 d1 d2 d3 d4 d5 d6 d7 dp (de) ds d0 d1 d2 d3 d4 ds transfer frame n + 1 retransferred frame nth transfer frame rdrf [1] per [2] [3] [3] figure 14.29 retransfer opera tion in sci receive mode section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 373 of 566 rej09b0211-0700 initialization read rdr and clear rdrf fla g in ssr to 0 clear re bit to 0 start reception start error processin g no no no yes yes orer = 0 and per = 0 rdrf = 1? all data received? yes figure 14.30 example of reception processing flow 14.7.8 clock output control when the gm bit in smr is set to 1, the clock output level can be fixed with bits cke0 and cke1 in scr. at this time, the minimum clock pulse width can be made the specified width. figure 14.31 shows the timing for fixing the clock output level. in this example, gm is set to 1, cke1 is cleared to 0, and the cke0 bit is controlled. specified pulse width sck cke0 specified pulse width figure 14.31 timing for fixing clock output level section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 374 of 566 rej09b0211-0700 when turning on the power or switching between sm art card interface mode and software standby mode, the following procedures should be followed in order to maintain the clock duty. powering on: to secure clock duty from power-on, the following switching procedure should be followed. 1. the initial state is port input and high im pedance. use a pull-up resistor or pull-down resistor to fix the potential. 2. fix the sck pin to the specified output level with the cke1 bit in scr. 3. set smr and scmr, and switch to smart card mode operation. 4. set the cke0 bit in scr to 1 to start clock output. when changing from smart card interface mode to software standby mode: 1. set the data register (dr) and data direction register (ddr) corresponding to the sck pin to the value for the fixed output state in software standby mode. 2. write 0 to the te bit and re bit in the seri al control register (scr) to halt transmit/receive operation. at the same time, set the cke1 bit to the value for the fixed output state in software standby mode. 3. write 0 to the cke0 bit in scr to halt the clock. 4. wait for one serial clock period. during this interval, clock output is fixed at the specified level, with the duty preserved. 5. make the transition to the software standby state. when returning to smart card interface mode from software standby mode: 1. exit the software standby state. 2. write 1 to the cke0 bit in scr and output the clock. signal generation is started with the normal duty. [1] [2] [3] [4] [5] [2] software standby normal operation normal operation [1] figure 14.32 clock halt and restart procedure section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 375 of 566 rej09b0211-0700 14.8 interrupts 14.8.1 interrupts in normal serial communication interface mode table 14.12 shows the interrupt sources in no rmal serial communication interface mode. a different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in scr. when the tdre flag in ssr is set to 1, a txi interrupt request is generated. when the tend flag in ssr is set to 1, a tei interrupt request is generated. a txi interrupt can activate the dtc to perform data transfer. the tdre flag is cleared to 0 automatically when data is transferred by the dtc. when the rdrf flag in ssr is set to 1, an rxi interrupt request is generated. when the orer, per, or fer flag in ssr is set to 1, an eri interrupt request is generated. an rxi interrupt request can activate the dtc to tr ansfer data. the rdrf flag is cleared to 0 auto matically when data is transferred by the dtc. a tei interrupt is requested when the tend flag is set to 1 and the teie bit is set to 1. if a tei interrupt and a txi interrupt are requested simultaneously, the txi interrupt has priority for acceptance. however, if the tdre and tend flags are cleared simultaneously by the txi interrupt routine, the sci cannot branch to the tei interrupt routine later. table 14.12 sci interrupt sources channel name interrupt source interrupt flag dtc activation eri_0 receive error orer, fer, per not possible rxi_0 receive data full rdrf possible txi_0 transmit data empty tdre possible 0 tei_0 transmission end tend not possible eri_1 receive error orer, fer, per not possible rxi_1 receive data full rdrf possible txi_1 transmit data empty tdre possible 1 tei_1 transmission end tend not possible eri_2 receive error orer, fer, per not possible rxi_2 receive data full rdrf possible 2 txi_2 transmit data empty tdre possible tei_2 transmission end tend not possible section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 376 of 566 rej09b0211-0700 14.8.2 interrupts in smart card interface mode table 14.13 shows the interrupt sources in smart card interface mode. the transmit end interrupt (tei) request cannot be used in this mode. table 14.13 sci interrupt sources channel name interrupt source interrupt flag dtc activation eri_0 receive error, detection orer, per, ers not possible rxi_0 receive data full rdrf possible 0 txi_0 transmit data empty tend possible eri_1 receive error, detection orer, per, ers not possible rxi_1 receive data full rdrf possible 1 txi_1 transmit data empty tend possible 2 eri_2 receive error, detection orer, per, ers not possible rxi_2 receive data full rdrf possible txi_2 transmit data empty tend possible in smart card interface mode, as in normal seri al communication interface mode, transfer can be carried out using the dtc. in transmit operations, the tdre flag is also set to 1 at the same time as the tend flag in ssr is set, and a txi interrup t is generated. if the txi request is designated beforehand as a dtc activation source, the dtc will be activated by the txi request, and transmit data will be transferred. the tdre and tend flags are automatically cleared to 0 when data is transferred by the dtc. in the event of an error, the sci retransmits the same data automatically. during this period, the tend flag remains cleared to 0 and the dtc is not activated. therefore, the sci and dtc will automatically transmit the specified number of bytes in the event of an error, in cluding retransmission. however, the ers flag is not cleared automatically when an error occurs . hence, the rie bit should be set to 1 beforehand so that an eri request will be generated in the event of an error, and the ers flag will be cleared. when transferring using the dtc, it is essential to set and enable the dtc before carrying out sci setting. for details of the dtc setting procedures, refer to section 8, data transfer controller (dtc). in receive operations, an rxi interrupt request is generated when the rdrf flag in ssr is set to 1. if the rxi request is designated beforehand as a dtc activation source, the dtc will be activated by the rxi request, and the receive data will be transferred. the rdrf flag is cleared to 0 automatically when data is transferred by the dtc. if an error occurs, an error flag is set but the section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 377 of 566 rej09b0211-0700 rdrf flag is not. consequently, the dtc is not activated, instead, an eri interrupt request is sent to the cpu. therefore, the error flag should be cleared. 14.9 usage notes 14.9.1 module stop mode setting sci operation can be disabled or enabled using the module stop control register. the initial setting is for sci operation to be halted. register acce ss is enabled by clearing module stop mode. for details, refer to section 20, power-down modes. 14.9.2 break detectio n and processing when framing error detection is performed, a break can be detected by reading the rxd pin value directly. in a break, the input from the rxd pin becomes all 0s, setting the fer flag, and possibly the per flag. note that as the sci continues the receive oper ation after receiving a break, even if the fer flag is cleared to 0, it will be set to 1 again. 14.9.3 mark state a nd break detection when te is 0, the txd pin is used as an i/o port whose direction (input or output) and level are determined by dr and ddr. this can be used to set the txd pin to mark state (high level) or send a break during serial data transmission. to maintain the communication line at mark state until te is set to 1, set both pcr and pdr to 1. as te is cleared to 0 at this point, the txd pin becomes an i/o port, and 1 is output from the txd pin. to send a break during serial transmission, first set pcr to 1 and pdr to 0, and then clear te to 0. when te is cleared to 0, the transmitter is initialized regardless of the current transmission state, the txd pin becomes an i/o port, and 0 is output from the txd pin. 14.9.4 receive error flags and transmit op erations (clocked sync hronous mode only) transmission cannot be started when a receive error fl ag (orer, per, or fer) is set to 1, even if the tdre flag is cleared to 0. be sure to cl ear the receive error flags to 0 before starting transmission. note also that receive error flags cannot be cleared to 0 even if the re bit is cleared to 0. section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 378 of 566 rej09b0211-0700 14.9.5 restrictions on using dtc when the external clock source is used as a synchronization clock, update tdr by the dtc and wait for at least five clock cycles before allowing the transmit clock to be input. if the transmit clock is input within four clock cycles after tdr modification, the sci may malfunction (figure 14.33). when using the dtc to read rdr, be sure to se t the receive end interrupt source (rxi) as a dtc activation source. t d0 lsb serial data sck d1 d3 d4 d5 d2 d6 d7 note: when external clock is supplied, t must be more than four clock cycles. tdre figure 14.33 sample transmission using dtc in clocked synchronous mode 14.9.6 sci operations during mode transitions transmission: before making the transition to module stop, software standby, watch, sub-active, or sub-sleep mode, stop all transmit operations (te = tie = teie = 0). tsr, tdr, and ssr are reset. the states of the output pins during each mode depend on the port settings, and the pins output a high-level signal after mode is cancelled and then the te is set to 1 again. if the transition is made during data transmission, the data being transmitted will be undefined. to transmit data in the same transmission mode after mode cancellation, set te to 1, read ssr, write to tdr, clear tdre in this order, and then start transmission. to transmit data in a different transmission mode, initialize the sci first. figure 14.34 shows a sample flowchart for mode transition during transmission. figures 14.35 and 14.36 show the pin states during transmission. before making the transition from the transmission mode using dtc transfer to module stop, software standby, watch, sub-active, or sub-sleep mode, stop all transmit operations (te = tie = teie = 0). setting te and tie to 1 after mode cancellation generates a txi interrupt request to start transmission using the dtc. section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 379 of 566 rej09b0211-0700 start transmission transmission [1] no no no yes yes yes read tend fla g in ssr make transition to software standby mode etc. cancel software standby mode etc. te = 0 initialization te = 1 [2] [3] all data transmitted? chan g e operatin g mode? tend = 1 [1] data bein g transmitted is lost halfway. data can be normally transmitted from the cpu by settin g te to 1, readin g ssr, writin g to tdr, and clearin g tdre to 0 after mode cancellation; however, if the dtc has been initiated, the data remainin g in dtc ram will be transmitted when te and tie are set to 1. [2] also clear tie and teie to 0 when they are 1. [3] module stop, watch, sub-active, and sub-sleep modes are included. figure 14.34 sample flowchart for mode transition during transmission te bit sck output pin txd output pin port input/output port input/output port input/output start stop hi g h output hi g h output transmission start transmission end transition to software standby mode software standby mode cancelled sci txd output port port sci txd output figure 14.35 pin states during transmission in asynchronous mode (internal clock) section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 380 of 566 rej09b0211-0700 te bit sck output pin txd output pin port input/output port input/output port input/output hi g h output * markin g output transmission start transmission end transition to software standby mode software standby mode cancelled sci txd output port port sci txd output last txd bit retained note: * initialized in software standby mode figure 14.36 pin states during transmission in clocked synchronous mode (internal clock) reception: before making the transition to module stop, software standby, watch, sub-active, or sub-sleep mode, stop reception (re = 0). rsr, rdr, and ssr are reset. if transition is made during data reception, the data being received will be invalid. to receive data in the same reception mode after mode cancellation, set re to 1, and then start reception. to receive data in a differen t reception mode, initialize the sci first. figure 14.37 shows a sample flowchart for mode transition during reception. section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 381 of 566 rej09b0211-0700 start reception reception [1] no no yes yes read receive data in rdr read rdrf fla g in ssr make transition to software standby mode etc. cancel software standby mode etc. re = 0 initialization re = 1 [2] chan g e operatin g mode? rdrf = 1 [1] data bein g received will be invalid. [2] module stop, watch, sub-active, and sub- sleep modes are included. figure 14.37 sample fl owchart for mode transi tion during reception 14.9.7 notes when switching from sck pin to port pin ? problem in operation: when ddr and dr are set to 1, sci clock output is used in clocked synchronous mode, and the sck pin is changed to the port pin while transmission is ended, port output is enabled after low-level output occurs for one half-cycle. when switching the sck pin to the port pin by making the following settings while ddr = 1, dr = 1, c/ a = 1, cke1 = 0, cke0 = 0, and te = 1, low-level output occurs for one half- cycle. 1. end of serial data transmission 2. te bit = 0 3. c/ a bit = 0 ... switchover to port output 4. occurrence of low-level output (see figure 14.38) section 14 serial communication interface (sci) rev. 7.00 sep. 11, 2009 page 382 of 566 rej09b0211-0700 sck/port data te c/a cke1 cke0 bit 7 bit 6 1. end of transmission 4. low-level output 3. c/ a = 0 2. te = 0 half-cycle low-level output figure 14.38 operation when switching from sck pin to port pin section 15 controller area network (hcan) rev. 7.00 sep. 11, 2009 page 383 of 566 rej09b0211-0700 section 15 controller area network (hcan) the hcan is a module for controlling a c ontroller area network (can) for realtime communication in vehicular and industrial equipment systems, etc. for details on can specification, refer to bosch can specification version 2.0 1991, robert bosch gmbh. the block diagram of the hcan is shown in figure 15.1. note: no dtc is implemented in the h8s/2614 and h8s/2616. 15.1 features ? can version: bosch 2.0b active compatible ? communication systems: nrz (non-return to zero) system (with bit-stuffing function) ? broadcast communication system ? transmission path: bidirectional 2-wire serial communication ? communication speed: max. 1 mbps ? data length: 0 to 8 bytes ? number of channels: 1 ? data buffers: 16 (one receive-only buffer and 15 buffers settable for transmission/reception) ? data transmission: two methods ? mailbox (buffer) number order (low-to-high) ? message priority (identifier) reverse-order (high-to-low) ? data reception: two methods ? message identifier match (transmit/receive-setting buffers) ? reception with message identifier masked (receive-only) ? cpu interrupts: 12 ? error interrupt ? reset processing interrupt ? message reception interrupt ? message transmission interrupt ? hcan operating modes ? support for various modes ? hardware reset ? software reset ? normal status (error-active, error-passive) ? bus off status section 15 controller area network (hcan) rev. 7.00 sep. 11, 2009 page 384 of 566 rej09b0211-0700 ? hcan configuration mode ? hcan sleep mode ? hcan halt mode ? other features ? dtc can be activated by message r eception mailbox (hcan mailbox 0 only) ? module stop mode can be set peripheral address bus peripheral data bus htxd mbi hrxd can data link controller mpi (cdlc) tx buffer rx buffer messa g e buffer messa g e control messa g e data mc0 to mc15, md0 to md15 lafm mailboxes microprocessor interface cpu interface control re g ister status re g ister hcan bosch can 2.0b active figure 15.1 hcan block diagram ? message buffer interface (mbi) the mbi, consisting of mailboxes and a local acceptance filter mask (lafm), stores can transmit/receive messages (identifiers, data, et c.) transmit messages ar e written by the cpu. for receive messages, the data received by the cdlc is stored automatically. ? microprocessor interface (mpi) the mpi, consisting of a bus interface, control re gister, status register, etc., controls hcan internal data, status, and so forth. ? can data link controller (cdlc) the cdlc transmits and receives of messages conforming to the bosch can ver. 2.0b active standard (data frames, remote frames, error fra mes, overload frames, inter-frame spacing), as well as crc checking, bus arbitration, and other functions. section 15 controller area network (hcan) rev. 7.00 sep. 11, 2009 page 385 of 566 rej09b0211-0700 15.2 input/output pins table 15.1 shows the hcan's pins. when using hcan pins, settings must be made in the hcan configuration mode (during initialization: mcr0 = 1 and gsr3 = 1). table 15.1 hcan pins name abbreviation input/output function hcan transmit data pin htxd output can bus transmission pin hcan receive data pin hrxd input can bus reception pin a bus driver is necessary for the interface between the pins and the can bus. a philips pca82c250 compatible model is recommended. 15.3 register descriptions the hcan has the following registers. for details on register addresses and register states during each process, refer to appendix a, on-chip i/o register. ? master control register (mcr) ? general status register (gsr) ? bit configuration register (bcr) ? mailbox configuration register (mbcr) ? transmit wait register (txpr) ? transmit wait cancel register (txcr) ? transmit acknowledge register (txack) ? abort acknowledge register (aback) ? receive complete register (rxpr) ? remote request register (rfpr) ? interrupt register (irr) ? mailbox interrupt mask register (mbimr) ? interrupt mask register (imr) ? receive error counter (rec) ? transmit error counter (tec) ? unread message status register (umsr) ? local acceptance filter mask h (lafmh) section 15 controller area network (hcan) rev. 7.00 sep. 11, 2009 page 386 of 566 rej09b0211-0700 ? local acceptance filter mask l (lafml) ? message control (8 bit 8 registers 16 sets) (mc0 to mc15) ? message data (8 bit 8 registers 16 sets) (md0 to md15) ? hcan monitor register (hcanmon) 15.3.1 master control register (mcr) the master control register (mcr) is an 8-bit register that controls the hcan. bit bit name initial value r/w description 7 mcr7 0 r/w hcan sleep mode release when this bit is set to 1, the hcan automatically exits hcan sleep mode on detection of can bus operation. 6 ? 0 r reserved this bit is always read as 0. only 0 should be written to this bit. 5 mcr5 0 r/w hcan sleep mode when this bit is set to 1, the hcan transits to hcan sleep mode. when this bit is cleared to 0, hcan sleep mode is released. 4, 3 ? all 0 r reserved these bits are always read as 0. only 0 should be written to these bits. 2 mcr2 0 r/w message transmission method 0: transmission order determined by message identifier priority 1: transmission order determined by mailbox (buffer) number priority (txpr1 > txpr15) 1 mcr1 0 r/w halt request when this bit is set to 1, the hcan transits to hcan halt mode. when this bit is cleared to 0, hcan halt mode is released. section 15 controller area network (hcan) rev. 7.00 sep. 11, 2009 page 387 of 566 rej09b0211-0700 bit bit name initial value r/w description 0 mcr0 1 r/w reset request when this bit is set to 1, the hcan transits to reset mode. for details, refer to section 15.4.1, hardware and software resets. [setting conditions] ? power-on reset ? hardware standby ? software standby ? 1-write (software reset) [clearing condition] ? when 0 is written to this bit while the gsr3 bit in gsr is 1 15.3.2 general status register (gsr) the general status register (gsr) is an 8-b it that indicates the status of the can bus. bit bit name initial value r/w description 7 to 4 ? all 0 r reserved these bits are always read as 0. only 0 should be written to these bits. 3 gsr3 1 r reset status bit indicates whether the hcan module is in the normal operating state or the reset state. this bit cannot be modified. [setting conditions] ? when entering configuration mode after the hcan internal reset has finished ? sleep mode [clearing condition] ? when entering normal operation mode after the mcr0 bit in mcr is cleared to 0 (note that there is a delay between clearing of the mcr0 bit and the gsr3 bit.) section 15 controller area network (hcan) rev. 7.00 sep. 11, 2009 page 388 of 566 rej09b0211-0700 bit bit name initial value r/w description 2 gsr2 1 r message transmission status flag flag that indicates whether the module is currently in the message transmission period. this bit cannot be modified. [setting condition] ? third intermission bit after eof (end of frame) [clearing condition] ? start of message transmission (sof) 1 gsr1 0 r transmit/receive warning flag this bit cannot be modified. [clearing conditions] ? when tec < 96 and rec < 96 ? when tec 256 [setting condition] ? when tec 96 or rec 96 0 gsr0 0 r bus off flag this bit cannot be modified. [setting condition] ? when tec 256 (bus off state) [clearing condition] ? recovery from bus off state section 15 controller area network (hcan) rev. 7.00 sep. 11, 2009 page 389 of 566 rej09b0211-0700 15.3.3 bit configuration register (bcr) the bit configuration register (bcr) is a 16-bit register that is used to set hcan bit timing parameters and the baud rate prescaler. for de tails on parameters, refer to section 15.4.2, initialization after hardware reset. bit bit name initial value r/w description 15 14 bcr7 bcr6 0 0 r/w r/w re-synchronization jump width (sjw) set the maximum bit synchronization width. 00: 1 time quantum 01: 2 time quanta 10: 3 time quanta 11: 4 time quanta 13 12 11 10 9 8 bcr5 bcr4 bcr3 bcr2 bcr1 bcr0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w baud rate prescaler (brp) set the length of time quantum. 000000: 2 system clock 000001: 4 system clock 000010: 6 system clock : 111111: 128 system clock 7 bcr15 0 r/w bit sample point (bsp) sets the point at which data is sampled. 0: bit sampling at one point (end of time segment 1 (tseg1)) 1: bit sampling at three points (end of tseg1 and preceding and following one time quantum) section 15 controller area network (hcan) rev. 7.00 sep. 11, 2009 page 390 of 566 rej09b0211-0700 bit bit name initial value r/w description 6 5 4 bcr14 bcr13 bcr12 0 0 0 r/w r/w r/w time segment 2 (tseg2) set the tseg2 width within a range of 2 to 8 time quanta. 000: setting prohibited 001: 2 time quanta 010: 3 time quanta 011: 4 time quanta 100: 5 time quanta 101: 6 time quanta 110: 7 time quanta 111: 8 time quanta 3 2 1 0 bcr11 bcr10 bcr9 bcr8 0 0 0 0 r/w r/w r/w r/w time segment 1 (tseg1) set the tseg1 (prseg + phseg1) width to between 4 and 16 time quanta. 0000: setting prohibited 0001: setting prohibited 0010: setting prohibited 0011: 4 time quanta 0100: 5 time quanta 0101: 6 time quanta 0110: 7 time quanta 0111: 8 time quanta 1000: 9 time quanta 1001: 10 time quanta 1010: 11 time quanta 1011: 12 time quanta 1100: 13 time quanta 1101: 14 time quanta 1110: 15 time quanta 1111: 16 time quanta section 15 controller area network (hcan) rev. 7.00 sep. 11, 2009 page 391 of 566 rej09b0211-0700 15.3.4 mailbox configuration register (mbcr) the mailbox configuration register (mbcr) is a 16-bit register that is used to set the transfer direction for each mailbox. bit bit name initial value r/w description 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mbcr7 mbcr6 mbcr5 mbcr4 mbcr3 mbcr2 mbcr1 ? mbcr15 mbcr14 mbcr13 mbcr12 mbcr11 mbcr10 mbcr9 mbcr8 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r r/w r/w r/w r/w r/w r/w r/w r/w these bits set the transfer direction for the corresponding mailboxes from 1 to 15. mbcrn determines the transfer direction for mailbox n (n = 1 to 15). 0: corresponding mailbox is set for transmission 1: corresponding mailbox is set for reception bit 8 is reserved. this bit is always read as 1 and the write value should always be 1. section 15 controller area network (hcan) rev. 7.00 sep. 11, 2009 page 392 of 566 rej09b0211-0700 15.3.5 transmit wait register (txpr) the transmit wait register (txpr) is a 16-bit register that is used to set a transmit wait after a transmit message is stored in a mailbox (buffer) (can bus arbitration wait). bit bit name initial value r/w description 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 txpr7 txpr6 txpr5 txpr4 txpr3 txpr2 txpr1 ? txpr15 txpr14 txpr13 txpr12 txpr11 txpr10 txpr9 txpr8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r r/w r/w r/w r/w r/w r/w r/w r/w these bits set a transmit wait (can bus arbitration wait) for the corresponding mailboxes 1 to 15. when txprn (n = 1 to 15) is set to 1, the message in mailbox n becomes the transmit wait state. [clearing conditions] ? completion of message transmission ? completion of transmission cancellation bit 8 is reserved. this bit is always read as 1 and the write value should always be 1. section 15 controller area network (hcan) rev. 7.00 sep. 11, 2009 page 393 of 566 rej09b0211-0700 15.3.6 transmit wait cancel register (txcr) the transmit wait cancel register (txcr) is a 16-b it register that controls the cancellation of transmit wait messages in mailboxes (buffers). bit bit name initial value r/w description 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 txcr7 txcr6 txcr5 txcr4 txcr3 txcr2 txcr1 ? txcr15 txcr14 txcr13 txcr12 txcr11 txcr10 txcr9 txcr8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r r/w r/w r/w r/w r/w r/w r/w r/w these bits cancel the transmit wait message in the corresponding mailboxes 1 to 15. when txcrn (n = 1 to 15) is set to 1, the transmit wait message in mailbox n is canceled. [clearing condition] ? completion of txpr clearing when transmit message is canceled normally bit 8 is reserved. this bit is always read as 0 and the write value should always be 0. section 15 controller area network (hcan) rev. 7.00 sep. 11, 2009 page 394 of 566 rej09b0211-0700 15.3.7 transmit acknowledge register (txack) the transmit acknowledge register (txack) is a 16-bit register containing status flags that indicate the normal transmission of mailbox (buffer) transmit messages. bit bit name initial value r/w description 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 txack7 txack6 txack5 txack4 txack3 txack2 txack1 ? txack15 txack14 txack13 txack12 txack11 txack10 txack9 txack8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * these bits are status flags that indicate error-free transmission of the transmit message in the corresponding mailboxes 1 to 15. when the message in mailbox n (n = 1 to 15) has been transmitted error-free, txackn is set to 1. [setting condition] ? completion of message transmission for corresponding mailbox [clearing condition] ? writing 1 bit 8 is reserved. this bit is always read as 0 and the write value should always be 0. note: * only 1 can be written to clear the flag. section 15 controller area network (hcan) rev. 7.00 sep. 11, 2009 page 395 of 566 rej09b0211-0700 15.3.8 abort acknowledge register (aback) the abort acknowledge register (aback) is a 16-bit register containing status flags that indicate the normal cancellation (aborting) of mailbox (buffer) transmit messages. bit bit name initial value r/w description 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 aback7 aback6 aback5 aback4 aback3 aback2 aback1 ? aback15 aback14 aback13 aback12 aback11 aback10 aback9 aback8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * these bits are status flags that indicate error-free cancellation (abortion) of the transmit message in the corresponding mailboxes 1 to 15. when the message in mailbox n (n = 1 to 15) has been canceled error-free, abackn is set to 1. [setting condition] ? completion of transmit message cancellation for corresponding mailbox [clearing condition] ? writing 1 bit 8 is reserved. this bit is always read as 0. the write value should always be 0. note: * only 1 can be written to clear the flag. section 15 controller area network (hcan) rev. 7.00 sep. 11, 2009 page 396 of 566 rej09b0211-0700 15.3.9 receive complete register (rxpr) the receive complete register (rxpr) is a 16-bit re gister containing status flags that indicate the normal reception of messages in mailboxes (buffers). for reception of a remote frame, when a bit in this register is set to 1, the corresponding remote request register (rfpr) bit is also set to 1 simultaneously. bit bit name initial value r/w description 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rxpr7 rxpr6 rxpr5 rxpr4 rxpr3 rxpr2 rxpr1 rxpr0 rxpr15 rxpr14 rxpr13 rxpr12 rxpr11 rxpr10 rxpr9 rxpr8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * when the message in mailbox n (n = 0 to 15) has been received error-free, rxprn is set to 1. [setting condition] ? completion of message (data frame or remote frame) reception in corresponding mailbox [clearing condition] ? writing 1 note: * only 1 can be written to clear the flag. section 15 controller area network (hcan) rev. 7.00 sep. 11, 2009 page 397 of 566 rej09b0211-0700 15.3.10 remote request register (rfpr) the remote request register (rfpr) is a 16-bit register containing status flags that indicate normal reception of remote frames in mailboxes (buffers). wh en a bit in this register is set to 1, the corresponding receive complete register (rxp r) bit is also set to 1 simultaneously. bit bit name initial value r/w description 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rfpr7 rfpr6 rfpr5 rfpr4 rfpr3 rfpr2 rfpr1 rfpr0 rfpr15 rfpr14 rfpr13 rfpr12 rfpr11 rfpr10 rfpr9 rfpr8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * when mailbox n (n = 0 to 15) has received the remote frame error-free, rfprn (n = 0 to 15) is set to 1. [setting condition] ? completion of remote frame reception in corresponding mailbox [clearing condition] ? writing 1 note: * only 1 can be written to clear the flag. section 15 controller area network (hcan) rev. 7.00 sep. 11, 2009 page 398 of 566 rej09b0211-0700 15.3.11 interrupt register (irr) the interrupt register (irr) is a 16-bit interrupt status flag register. bit bit name initial value r/w description 15 irr7 0 r/(w) * overload frame [setting condition] ? when an overload frame is transmitted [clearing condition] ? writing 1 14 irr6 0 r/(w) * bus off interrupt flag status flag indicating the bus off state caused by the transmit error counter. [setting condition] ? when tec 256 [clearing condition] ? writing 1 13 irr5 0 r/(w) * error passive interrupt flag status flag indicating the error passive state caused by the transmit/receive error counter. [setting condition] ? when tec 128 or rec 128 [clearing condition] ? writing 1 section 15 controller area network (hcan) rev. 7.00 sep. 11, 2009 page 399 of 566 rej09b0211-0700 bit bit name initial value r/w description 12 irr4 0 r/(w) * receive overload warning interrupt flag status flag indicating the error warning state caused by the receive error counter. [setting condition] ? when rec 96 [clearing condition] ? writing 1 11 irr3 0 r/(w) * transmit overload warning interrupt flag status flag indicating the error warning state caused by the transmit error counter. [setting condition] ? when tec 96 [clearing condition] ? writing 1 10 irr2 0 r remote frame request interrupt flag status flag indicating that a remote frame has been received in a mailbox (buffer). [setting condition] ? when remote frame reception is completed, when corresponding mbimr = 0 [clearing condition] ? clearing of all bits in rfpr (remote request register) 9 irr1 0 r receive message interrupt flag status flag indicating that a mailbox (buffer) receive message has been received normally. [setting condition] ? when data frame or remote frame reception is completed, when corresponding mbimr = 0 [clearing condition] ? clearing of all bits in rxpr (receive complete register) section 15 controller area network (hcan) rev. 7.00 sep. 11, 2009 page 400 of 566 rej09b0211-0700 bit bit name initial value r/w description 8 irr0 1 r/(w) * reset interrupt flag status flag indicating that the hcan module has been reset. this bit cannot be masked by the interrupt mask register (imr). if this bit is not cleared to 0 after entering power-on reset or returning from software standby mode, interrupt processing will start immediately when the interrupt controller enables interrupts. [setting condition] ? when the reset operation has finished after entering power-on reset or software standby mode [clearing condition] ? writing 1 7 to 5 ? all 0 ? reserved these bits are always read as 0. only 0 should be written to these bits. 4 irr12 0 r/(w) * bus operation interrupt flag status flag indicating detection of a dominant bit due to bus operation when the hcan module is in hcan sleep mode. [setting condition] ? bus operation (dominant bit) detection in hcan sleep mode [clearing condition] ? writing 1 3, 2 ? all 0 ? reserved these bits are always read as 0. only 0 should be written to these bits. section 15 controller area network (hcan) rev. 7.00 sep. 11, 2009 page 401 of 566 rej09b0211-0700 bit bit name initial value r/w description 1 irr9 0 r unread interrupt flag status flag indicating that a receive message has been overwritten before being read. [setting condition] ? when umsr (unread message status register) is set [clearing condition] ? clearing of all bits in umsr (unread message status register) 0 irr8 0 r/(w) * mailbox empty interrupt flag status flag indicating that the next transmit message can be stored in the mailbox. [setting condition] ? when txpr (transmit wait register) is cleared by completion of transmission or completion of transmission abort [clearing condition] ? writing 1 note: * only 1 can be written to clear the flag. section 15 controller area network (hcan) rev. 7.00 sep. 11, 2009 page 402 of 566 rej09b0211-0700 15.3.12 mailbox interrupt mask register (mbimr) the mailbox interrupt mask register (mbimr) is a 16-bit register that controls the enabling or disabling of individual mailbox (buffer) interrupt requests. bit bit name initial value r/w description 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mbimr7 mbimr6 mbimr5 mbimr4 mbimr3 mbimr2 mbimr1 mbimr0 mbimr15 mbimr14 mbimr13 mbimr12 mbimr11 mbimr10 mbimr9 mbimr8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w mailbox interrupt mask (mbimrx) when mbimrn (n = 1 to 15) is cleared to 0, the interrupt request in mailbox n is enabled. when set to 1, the interrupt request is masked. the interrupt source in a transmit mailbox is txpr clearing caused by transmission end or transmission cancellation. the interrupt source in a receive mailbox is rxpr setting on reception end. section 15 controller area network (hcan) rev. 7.00 sep. 11, 2009 page 403 of 566 rej09b0211-0700 15.3.13 interrupt mask register (imr) the interrupt mask register (imr) is a 16-bit register containing flags that enable or disable requests by individual interrupt sources. the interrupt flag cannot be masked. bit bit name initial value r/w description 15 imr7 1 r/w overload frame when this bit is cleared to 0, ovr0 (interrupt request by irr7) is enabled. when set to 1, ovr0 is masked. 14 imr6 1 r/w bus off interrupt mask when this bit is cleared to 0, ers0 (interrupt request by irr6) is enabled. when set to 1, ers0 is masked. 13 imr5 1 r/w error passive interrupt mask when this bit is cleared to 0, ers0 (interrupt request by irr5) is enabled. when set to 1, ers0 is masked. 12 imr4 1 r/w receive overload warning interrupt mask when this bit is cleared to 0, ovr0 (interrupt request by irr4) is enabled. when set to 1, ovr0 is masked. 11 imr3 1 r/w transmit overload warning interrupt mask when this bit is cleared to 0, ovr0 (interrupt request by irr3) is enabled. when set to 1, ovr0 is masked. 10 imr2 1 r/w remote frame request interrupt mask when this bit is cleared to 0, ovr0 (interrupt request by irr2) is enabled. when set to 1, ovr0 is masked. 9 imr1 1 r/w receive message interrupt mask when this bit is cleared to 0, rm1 (interrupt request by irr1) is enabled. when set to 1, rmi is masked. 8 ? 0 r reserved this bit is always read as 0. only 0 should be written to this bit. section 15 controller area network (hcan) rev. 7.00 sep. 11, 2009 page 404 of 566 rej09b0211-0700 bit bit name initial value r/w description 7 to 5 ? all 1 r reserved these bits are always read as 1. only 1 should be written to these bits. 4 imr12 1 r/w bus operation interrupt mask when this bit is cleared to 0, ovr0 (interrupt request by irr12) is enabled. when set to 1, ovr0 is masked. 3, 2 ? all 1 r reserved these bits are always read as 1. only 1 should be written to these bits. 1 imr9 1 r/w unread interrupt mask when this bit is cleared to 0, ovr0 (interrupt request by irr9) is enabled. when set to 1, ovr0 is masked. 0 imr8 1 r/w mailbox empty interrupt mask when this bit is cleared to 0, sle0 (interrupt request by irr8) is enabled. when set to 1, sle0 is masked. 15.3.14 receive error counter (rec) the receive error counter (rec) is an 8-bit read-onl y register that functions as a counter indicating the number of receive message errors on the can bus. the count value is stipulated in the can protocol. 15.3.15 transmit error counter (tec) the transmit error counter (tec) is an 8-bit read-only register that functions as a counter indicating the number of transmit message errors on the can bus. the count value is stipulated in the can protocol. section 15 controller area network (hcan) rev. 7.00 sep. 11, 2009 page 405 of 566 rej09b0211-0700 15.3.16 unread message status register (umsr) the unread message status register (umsr) is a 16-bit register containing status flags that indicate, for individual mailboxes (buffers), that a received message has been overwritten by a new receive message before being read. when overwritten by a new message, data in the unread receive message is lost. bit bit name initial value r/w description 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 umsr7 umsr6 umsr5 umsr4 umsr3 umsr2 umsr1 umsr0 umsr15 umsr14 umsr13 umsr12 umsr11 umsr10 umsr9 umsr8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/(w) * r/(w) * r/(w) * [setting condition] ? when a new message is received before rxpr is cleared [clearing condition] ? writing 1 note: * only 1 can be written to clear the flag. section 15 controller area network (hcan) rev. 7.00 sep. 11, 2009 page 406 of 566 rej09b0211-0700 15.3.17 local acceptance filter masks (lafml, lafmh) the local acceptance filter masks (lafml and lafmh) are 16-bit registers that individually set the identifier bits of the message to be stored in mailbox 0 as don't care. for details, refer to section 15.4.4, massage reception. the relationship between the iden tifier bits and mask bits are shown in the following. section 15 controller area network (hcan) rev. 7.00 sep. 11, 2009 page 407 of 566 rej09b0211-0700 lafml bit bit name initial value r/w description 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lafml7 lafml6 lafml5 lafml4 lafml3 lafml2 lafml1 lafml0 lafml15 lafml14 lafml13 lafml12 lafml11 lafml10 lafml9 lafml8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w when this bit is set to 1, id-7 of the receive message identifier is not compared. when this bit is set to 1, id-6 of the receive message identifier is not compared. when this bit is set to 1, id-5 of the receive message identifier is not compared. when this bit is set to 1, id-4 of the receive message identifier is not compared. when this bit is set to 1, id-3 of the receive message identifier is not compared. when this bit is set to 1, id-2 of the receive message identifier is not compared. when this bit is set to 1, id-1 of the receive message identifier is not compared. when this bit is set to 1, id-0 of the receive message identifier is not compared. when this bit is set to 1, id-15 of the receive message identifier is not compared. when this bit is set to 1, id-14 of the receive message identifier is not compared. when this bit is set to 1, id-13 of the receive message identifier is not compared. when this bit is set to 1, id-12 of the receive message identifier is not compared. when this bit is set to 1, id-11 of the receive message identifier is not compared. when this bit is set to 1, id-10 of the receive message identifier is not compared. when this bit is set to 1, id-9 of the receive message identifier is not compared. when this bit is set to 1, id-8 of the receive message identifier is not compared. section 15 controller area network (hcan) rev. 7.00 sep. 11, 2009 page 408 of 566 rej09b0211-0700 lafmh bit bit name initial value r/w description 15 14 13 lafmh7 lafmh6 lafmh5 0 0 0 r/w r/w r/w when this bit is set to 1, id-20 of the receive message identifier is not compared. when this bit is set to 1, id-19 of the receive message identifier is not compared. when this bit is set to 1, id-18 of the receive message identifier is not compared. 12 to 10 ? all 0 r reserved these bits are always read as 0. only 0 should be written to these bits. 9 8 7 6 5 4 3 2 1 0 lafmh1 lafmh0 lafmh15 lafmh14 lafmh13 lafmh12 lafmh11 lafmh10 lafmh9 lafmh8 0 0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w when this bit is set to 1, id-17 of the receive message identifier is not compared. when this bit is set to 1, id-16 of the receive message identifier is not compared. when this bit is set to 1, id-28 of the receive message identifier is not compared. when this bit is set to 1, id-27 of the receive message identifier is not compared. when this bit is set to 1, id-26 of the receive message identifier is not compared. when this bit is set to 1, id-25 of the receive message identifier is not compared. when this bit is set to 1, id-24 of the receive message identifier is not compared. when this bit is set to 1, id-23 of the receive message identifier is not compared. when this bit is set to 1, id-22 of the receive message identifier is not compared. when this bit is set to 1, id-21 of the receive message identifier is not compared. section 15 controller area network (hcan) rev. 7.00 sep. 11, 2009 page 409 of 566 rej09b0211-0700 15.3.18 message control (mc0 to mc15) the message control register sets consist of eight 8-bit registers for one mailbox. the hcan has 16 sets of these registers. because message contro l registers are in ram, their initial values after power-on are undefined. be sure to initialize them by writing 0 or 1. figure 15.2 shows the register names for each mailbox. mc0[1] mc1[1] mc2[1] mc3[1] mc15[1] mc0[2] mc1[2] mc2[2] mc3[2] mc15[2] mc0[3] mc1[3] mc2[3] mc3[3] mc15[3] mc0[4] mc1[4] mc2[4] mc3[4] mc15[4] mc0[5] mc1[5] mc2[5] mc3[5] mc15[5] mc0[6] mc1[6] mc2[6] mc3[6] mc15[6] mc0[7] mc1[7] mc2[7] mc3[7] mc15[7] mc0[8] mc1[8] mc2[8] mc3[8] mc15[8] mail box 0 mail box 1 mail box 2 mail box 3 mail box 15 figure 15.2 message control register configuration the setting of message control registers are shown in the following. figures 15.3 and 15.4 show the correspondence between the iden tifiers and register bit names. sof id-28 id-27 id-18 rtr ide r0 identifier figure 15.3 standard format sof id-28 id-27 id-18 srr ide id-17 id-16 id-0 rtr r1 standard identifier extended identifier figure 15.4 extended format section 15 controller area network (hcan) rev. 7.00 sep. 11, 2009 page 410 of 566 rej09b0211-0700 register name bit bit name r/w description 7 to 4 ? r/w the initial value of these bits is undefined; they must be initialized (by writing 0 or 1). mcx[1] 3 to 0 dlc3 to dlc0 r/w data length code set the data length of a data frame or the data length requested in a remote frame within the range of 0 to 8 bits. 0000: 0 bytes 0001: 1 byte 0010: 2 bytes 0011: 3 bytes 0100: 4 bytes 0101: 5 bytes 0110: 6 bytes 0111: 7 bytes 1000: 8 bytes : : 1111: 8 bytes mcx[2] mcx[3] mcx[4] 7 to 0 7 to 0 7 to 0 ? ? ? r/w r/w r/w the initial value of these bits is undefined; they must be initialized (by writing 0 or 1). 7 to 5 id-20 to id-18 r/w sets id -20 to id-18 in the identifier. 4 rtr r/w remote transmission request used to distinguish between data frames and remote frames. 0: data frame 1: remote frame 3 ide r/w identifier extension used to distinguish between the standard format and extended format of data frames and remote frames. 0: standard format 1: extended format 2 ? r/w the initial value of this bit is undefined. it must be initialized by writing 0 or 1. mcx[5] 1 and 0 id-17 and id-16 r/w sets id-17 and id-16 in the identifier. mcx[6] 7 to 0 id-28 to id-21 r/w sets id-28 to id-21 in the identifier. section 15 controller area network (hcan) rev. 7.00 sep. 11, 2009 page 411 of 566 rej09b0211-0700 register name bit bit name r/w description mcx[7] 7 to 0 id-7 to id-0 r/w sets id-7 to id-0 in the identifier. mcx[8] 7 to 0 id-15 to id-8 r/w sets id-15 to id-8 in the identifier. note: x: mailbox number 15.3.19 message data (md0 to md15) the message data register sets consist of eight 8-bit registers for one mailbox. the hcan has 16 sets of these registers. because message data regi sters are in ram, their initial values after power- on are undefined. be sure to initialize them by writing 0 or 1. figure 15.5 shows the register names for each mailbox. md0[1] md1[1] md2[1] md3[1] md15[1] md0[2] md1[2] md2[2] md3[2] md15[2] md0[3] md1[3] md2[3] md3[3] md15[3] md0[4] md1[4] md2[4] md3[4] md15[4] md0[5] md1[5] md2[5] md3[5] md15[5] md0[6] md1[6] md2[6] md3[6] md15[6] md0[7] md1[7] md2[7] md3[7] md15[7] md0[8] md1[8] md2[8] md3[8] md15[8] mail box 0 mail box 1 mail box 2 mail box 3 mail box 15 figure 15.5 message data configuration 15.3.20 hcan monitor register (hcanmon) the hcan monitor register (hcanmon) is an 8-bit read-only register that reflects the states of the hcan pins. this register cannot be modified. bit bit name initial value r/w description 7 to 2 ? undefined ? reserved only 0 should be written to these bits. 1 txd undefined r transmission pin the state of the htxd pin is read. this bit cannot be modified. 0 rxd undefined r reception pin the state of the hrxd pin is read. this bit cannot be modified. section 15 controller area network (hcan) rev. 7.00 sep. 11, 2009 page 412 of 566 rej09b0211-0700 15.4 operation 15.4.1 hardware and software resets the hcan can be reset by a hardware reset or software reset. ? hardware reset at power-on reset, or in hardware or software standby mode, the hcan is initialized by automatically setting the mcr reset request bit (mcr0) in mcr and the reset state bit (gsr3) in gsr. at the same time, all internal registers, except for message control and message data registers, are initialized by a hardware reset. ? software reset the hcan can be reset by setting the mcr reset request bit (mcr0) in mcr via software. in a software reset, the error counters (tec and rec) are initialized, however other registers are not. if the mcr0 bit is set while the can controller is performing a communication operation (transmission or reception), the initialization state is not entered until message transfer has been completed. the reset status bit (gsr3) in gsr is set on completion of initialization. 15.4.2 initialization after hardware reset after a hardware reset, the following initia lization processing s hould be carried out: 1. clearing of irr0 bit in the interrupt register (irr) 2. bit rate setting 3. mailbox transmit/receive settings 4. mailbox (ram) initialization 5. message transmission method setting these initial settings must be made while the hcan is in bit configuration mode. configuration mode is a state in which the gsr3 bit in gsr is set to 1 by a reset. configuration mode is exited by clearing the mcr0 bit in mcr to 0; when the mcr0 bit is cleared to 0, the hcan automatically clears the gsr3 bit in gsr. ther e is a delay between clearing the mcr0 bit and clearing the gsr3 bit because th e hcan needs time to be interna lly reset, there is a delay between clearing of the mcr0 bit and gsr3 bit. after the hcan exits configuration mode, the power-up sequence begins, and communication with the can bus is possible as soon as 11 consecutive recessive bits have been detected. section 15 controller area network (hcan) rev. 7.00 sep. 11, 2009 page 413 of 566 rej09b0211-0700 irr0 clearing: the reset interrupt flag (irr0) is always set after a power-on reset or recovery from software standby mode. as an hcan interrupt is initiated immediately when interrupts are enabled, irr0 should be cleared. hardware reset mcr0 = 1 (automatic) irr0 = 1 (automatic) gsr3 = 1 (automatic) mcr0 = 0 gsr3 = 0? yes no gsr3 = 0 & 11 recessive bits received? can bus communication enabled yes no bit confi g uration mode period in which bcr, mbcr, etc., are initialized : settin g s by user : processin g by hardware initialization of hcan module clear irr0 bcr settin g mbcr settin g mailbox initialization messa g e transmission method initialization imr settin g (interrupt mask settin g ) mbimr settin g (interrupt mask settin g ) mc[x] settin g (receive identifier settin g ) lafm settin g (receive identifier mask settin g ) figure 15.6 hardware reset flowchart section 15 controller area network (hcan) rev. 7.00 sep. 11, 2009 page 414 of 566 rej09b0211-0700 mcr0 = 1 gsr3 = 1 (automatic) initialization of rec and tec only mcr0 = 0 gsr3 = 0? can bus communication enabled bus idle? yes correction yes correction : settin g s by user : processin g by hardware no no no gsr3 = 1? no no no bcr settin g mbcr settin g mailbox (ram) initialization messa g e transmission method initialization ok? imr settin g mbimr settin g mc[x] settin g lafm settin g ok? gsr3 = 0 & 11 recessive bits received? yes yes yes figure 15.7 software reset flowchart section 15 controller area network (hcan) rev. 7.00 sep. 11, 2009 page 415 of 566 rej09b0211-0700 bit rate and bit timing settings: the bit rate and bit timing settings are made in the bit configuration register (bcr). settings should be made such that all can controllers connected to the can bus have the same baud rate and bit width. the 1-bit time consists of the total of the settable time quantum (tq). sync_seg prseg phseg1 phseg2 time segment 2 (tseg2) time segment 1 (tseg1) 1-bit time (8 to 25 time quanta) 4 to 16 time quanta 2 to 8 time quanta 1 time quantum figure 15.8 detailed description of one bit sync_seg is a segment for establishing the synchronization of nodes on the can bus. normal bit edge transitions occur in this segment. prseg is a segment for compensating for the physical delay between networks. phseg1 is a buffer segment for correcting phase drift (positive). this segment is extended when synchronization (resynchronization) is established. phseg2 is a buffer segment for correcting phase drift (negative). this segment is shortened when synchronization (resynchronization) is established. limits on the settable value (tseg1, tseg2, brp, sample point, and sjw) are shown in table 15.2. table 15.2 limits for settable value name abbreviation min value max value time segment 1 tseg1 b'0011 * 2 b'1111 time segment 2 tseg2 b'001 * 3 b'111 baud rate prescaler brp b'000000 b'111111 bit sample point bsp b'0 b'1 re-synchronization jump width sjw * 1 b'00 b'11 notes: 1. sjw is stipulated in the can specifications: 3 sjw 0 2. the minimum value of tseg2 is stipulated in the can specifications: tseg2 sjw 3. the minimum value of tseg1 is stipulated in the can specifications: tseg1 > tseg2 section 15 controller area network (hcan) rev. 7.00 sep. 11, 2009 page 416 of 566 rej09b0211-0700 time quanta (tq) is an integer multiple of the number of system clocks, and is determined by the baud rate prescaler (brp) as follows. f clk is the system clock frequency. tq = 2 (bpr setting + 1)/f clk the following formula is used to calculate the 1-bit time and bit rate. 1-bit time = tq (3 + tseg1 + tseg2) bit rate = 1/bit time = f clk /{2 (bpr setting + 1) (3 + tseg1 + tseg2)} note: f clk = (system clock) a bcr value is used for brp, tseg1, and tseg2. example: with a system clock of 20 mhz, a brp setting of b'000000, a tseg1 setting of b'0100, and a tseg2 setting of b'011: bit rate = 20/{2 (0 + 1) (3 + 4 + 3)} = 1 mbps table 15.3 setting range for tseg1 and tseg2 in bcr tseg2 (bcr[14:12]) 001 010 011 100 101 110 111 2 3 4 5 6 7 8 0011 no yes no no no no no tseg1 (bcr[11:8]) 0100 yes * yes yes no no no no 0101 yes * yes yes yes no no no 0110 yes * yes yes yes yes no no 0111 yes * yes yes yes yes yes no 1000 yes * yes yes yes yes yes yes 1001 yes * yes yes yes yes yes yes 1010 yes * yes yes yes yes yes yes 1011 yes * yes yes yes yes yes yes 1100 yes * yes yes yes yes yes yes 1101 yes * yes yes yes yes yes yes 1110 yes * yes yes yes yes yes yes 1111 yes * yes yes yes yes yes yes notes: the time quantum value for tseg1 and tseg2 is the tseg value + 1. * only a value other than brp[13:8] = b'000000 can be set. section 15 controller area network (hcan) rev. 7.00 sep. 11, 2009 page 417 of 566 rej09b0211-0700 mailbox transmit/receive settings: the hcan has 16 mailboxes. mailbox 0 is receive-only, while mailboxes 1 to 15 can be set for transmissi on or reception. the initial status of mailboxes 1 to 15 is for transmission. mailbox transmit/receive se ttings are not initialized by a software reset. clearing a bit to 0 in the mailbox configuration register (mbcr) designates the corres ponding mailbox for transmission use, whereas a setting of 1 in mbcr designates the corresponding mailbox for reception use. when setting mailboxes for reception, in order to improve message reception efficiency, high-priority messages s hould be set in low-to-high mailbox order. mailbox (message control/data) initial settings: message control/data are held in ram, and so their initial values are undefined after power is supplied. initial values mu st therefore be set in all the mailboxes (by writing 0s or 1s). setting the message transmission method: the following two kinds of message transmission methods are available. ? transmission order determined by message identifier priority ? transmission order determined by mailbox number priority either of the message transmission methods can be selected with the message transmission method bit (mcr2) in the master control register (mcr): when messages are set to be transmitted according to the message identifier priority, if several messages are designated as waiting for transmission (txpr = 1), the message with the highest priority in the message identifier is stored in the transmit buffer. can bus arbitration is then carried out for the message stored in the transmit buffer, and the message is transmitted when the transmission right is acquired. when the txpr bit is set, the highest-priority message is found and stored in the transmit buffer. when messages are set to be tr ansmitted according to the mailbox number proiority, if several messages are designated as waiting for transmission (txpr = 1), messages are stored in the transmit buffer in low-to-high mailbox order. can bus arbitration is then carried out for the message stored in the transmit buffer, and the message is transmitted when the transmission right is acquired. section 15 controller area network (hcan) rev. 7.00 sep. 11, 2009 page 418 of 566 rej09b0211-0700 15.4.3 message transmission messages are transmitted using mailboxes 1 to 15. the transmission procedure after initial settings is described below, and a transmission flowchart is shown in figure 15.9. initialization (after hardware reset only) clear irr0 bcr settin g mbcr settin g mailbox initialization messa g e transmission method settin g yes no yes yes : settin g s by user : processin g by hardware no no interrupt settin g s transmit data settin g arbitration field settin g control field settin g data field settin g messa g e transmission gsr2 = 0 (durin g transmission only) txack = 1 irr8 = 1 clear txack clear irr8 messa g e transmission wait txpr settin g bus idle? transmission completed? imr8 = 1? interrupt to cpu end of transmission figure 15.9 transmission flowchart section 15 controller area network (hcan) rev. 7.00 sep. 11, 2009 page 419 of 566 rej09b0211-0700 cpu interrupt source settings: the cpu interrupt source is set by the interrupt mask register (imr) and mailbox interrupt mask register (mbimr). transmission acknowledge and transmission abort acknowledge interrupts can be generated for individual mailboxes in the mailbox interrupt mask register (mbimr). arbitration field setting: the arbitration field is set by message control registers mcx[5] to mcx[8] in a transmit mailbox. for a standard format, an 11-bit identifier (id-28 to id-18) and the rtr bit are set, and the ide bit is cleared to 0. for an extended format, a 29-bit identifier (id-28 to id-0) and the rtr bit are set, and the ide bit is set to 1. control field setting: in the control field, the byte length of the data to be transmitted is set within the range of zero to eight bytes. the register to be set is the message control register mcx[1] in a transmit mailbox. data field setting: in the data field, the data to be transmitted is set within the range zero to eight. the registers to be set are the message data registers mdx[1] to mdx[8]. the byte length of the data to be transmitted is determined by the data length code in the control field. even if data exceeding the value set in the contro l field is set in the data field, up to the byte length set in the control field will actually be transmitted. message transmission: if the corresponding mailbox transmit wait bit (txpr1 to txpr15) in the transmit wait register (txpr) is set to 1 after message control and message data registers have been set, the message enters transmit wait state. if the message is transmitted error-free, the corresponding acknowledge bit (txack1 to txack15) in the transmit acknowledge register (txack) is set to 1, and the corresponding transmit wait bit (txpr1 to txpr15) in the transmit wait register (txpr) is automatically cleared to 0. also, if the corresponding bit (mbimr1- mbimr15) in the mailbox interrupt mask register (mbimr) and the mailbox empty interrupt bit (irr8) in the interrupt mask register (imr) are both simultaneously set to enable interrupts, interrupts may be sent to the cpu. if transmission of a transmit message is aborted in the following cases, the message is retransmitted automatically: ? can bus arbitration failure (failure to acquire the bus) ? error during transmission (bit error, stuff error, crc error, frame error, or ack error) message transmission cancellation: transmission cancellation can be specified for a message stored in a mailbox as a transmit wait message. a transmit wait message is canceled by setting the bit for the corresponding mailbox (txcr1 to txcr15) to 1 in the transmit cancel register (txcr). clearing the transmit wait register (txpr) does not cancel transmission. when cancellation is executed, the transmit wait register (txpr) is automatically reset, and the corresponding bit is set to 1 in the abort acknowledge register (aback). an interrupt to the cpu section 15 controller area network (hcan) rev. 7.00 sep. 11, 2009 page 420 of 566 rej09b0211-0700 can be requested, and if the mailbox empty interrupt (irr8) is enabled for the bits (mbimr1 to mbimr15) corresponding to the mailbox interrupt mask register (mbimr) and interrupt mask register (imr), interrupts may be sent to the cpu. however, a transmit wait message cannot be canceled at the following times: ? during internal arbitration or can bus arbitration ? during data frame or remote frame transmission figure 15.10 shows a flowchart for transmit message cancellation. messa g e transmit wait txpr settin g yes no yes no : settin g s by user : processin g by hardware set txcr bit correspondin g to messa g e to be canceled messa g e not sent clear txcr, txpr aback = 1 irr8 = 1 clear txack clear aback clear irr8 completion of messa g e transmission txack = 1 clear txcr, txpr irr8 = 1 cancellation possible? imr8 = 1? end of transmission/transmission cancellation interrupt to cpu figure 15.10 transmit message cancellation flowchart section 15 controller area network (hcan) rev. 7.00 sep. 11, 2009 page 421 of 566 rej09b0211-0700 15.4.4 message reception the reception procedure after initial settings is desc ribed below. a reception flowchart is shown in figure 15.11. rxpr irr1 = 1 no imr2 = 1? interrupt to cpu yes no yes yes yes no : settin g s by user : processin g by hardware no yes initialization clear irr0 bcr settin g mbcr settin g mailbox (ram) initialization receive data settin g arbitration field settin g local acceptance filter settin g s interrupt settin g s messa g e reception (match of identifier in mailbox?) same rxpr = 1? imr1 = 1? data frame? interrupt to cpu clear irr1 end of reception clear irr2, irr1 unread messa g e no rxpr, rfpr = 1 irr2 = 1, irr1 = 1 messa g e control read messa g e data read messa g e control read messa g e data read transmission of data frame correspondin g to remote frame figure 15.11 r eception flowchart section 15 controller area network (hcan) rev. 7.00 sep. 11, 2009 page 422 of 566 rej09b0211-0700 cpu interrupt source settings: cpu interrupt source settings are made in the interrupt mask register (imr) and mailbox interrupt register (m bimr). the message to be received is also specified. data frame and remote frame receive wait interrupt requests can be generated for individual mailboxes in the mbimr. arbitration field setting: to receive a message, the message id entifier must be set in advance in the message control registers (mcx[1] to mcx[8] ) for the receiving mailbox. when a message is received, all the bits in the re ceive message identifier are compar ed with those in each message control register identifier, and if a 100% match is found, the message is stored in the matching mailbox. mailbox 0 has a local acceptance filter mask (lafm) that allows don't care settings to be made. the lafm setting can be made only for mailbox 0. by making the don't care setting for all the bits in the receive message identifier, messages of multiple identifiers can be received. examples: ? when the identifier of mailbox 1 is 010_1010_1010 (standard format), only one kind of message identifier can be received by mailbox 1: identifier 1: 010_1010_1010 ? when the identifier of mailbox 0 is 010_1010_1010 (standard format) and the lafm setting is 000_0000_0011 (0: care, 1: don't care), a total of four kinds of message identifiers can be received by mailbox 0: identifier 1: 010_1010_1000 identifier 2: 010_1010_1001 identifier 3: 010_1010_1010 identifier 4: 010_1010_1011 message reception: when a message is received, a crc check is performed automatically. if the result of the crc check is normal, ack is tran smitted in the ack field irrespective of whether the message can be received or not. ? data frame reception if the received message is confirmed to be erro r-free by the crc check, the identifier in the mailbox (and also lafm in the case of mailbox 0 only) and the identifier of the receive message, are compared. if a complete match is found, the message is stored in the mailbox. the message identifier comparison is carried out on each mailbox in turn, starting with mailbox 0 and ending with mailbox 15. if a complete match is found, the comparison ends at that point, the message is stored in the matching mailbox, and the corresponding receive complete bit (rxpr0 to rxpr15) is set in the receive comple te register (rxpr). however, when a mailbox 0 lafm comparison is carried out, even if the identifier matches, the mailbox comparison sequence does not end at that point, but continues with mailbox 1 and then the section 15 controller area network (hcan) rev. 7.00 sep. 11, 2009 page 423 of 566 rej09b0211-0700 remaining mailboxes. it is therefore possible for a message matching mailbox 0 to be received by another mailbox. note that the same message cannot be stored in more than one of mailboxes 1 to 15. on receiving a message, a cpu interrupt request may be generated depending on the mailbox interrupt mask register (mbimr) and interrupt mask register (imr) settings. ? remote frame reception two kinds of messages?data frames and remote frames?can be stored in mailboxes. a remote frame differs from a data frame in that the remote transmission request bit (rtr) in the message control register and the data field are 0 bytes long. the data length to be returned in a data frame must be stored in the data length code (dlc) in the control field. when a remote frame (rtr = recessive) is receive d, the corresponding bit is set in the remote request wait register (rfpr). if the corresponding bit (mbimr0 to mbimr15) in the mailbox interrupt mask register (mbimr) and the remote frame request interrupt mask (irr2) in the interrupt mask register (imr) are set to the interrupt enable value at this time, an interrupt can be sent to the cpu. unread message overwrite: if the receive message identifier ma tches the mailbox identifier, the receive message is stored in the mailbox regardle ss of whether the mailbox contains an unread message or not. if a message overwrite occurs, the corresponding bit (umsr0 to umsr15) is set in the unread message register (umsr). in overwriting an unread message, when a new message is received before the corresponding bit in the recei ve complete register (rxpr) has been cleared, the unread message register (umsr) is set. if the unread interrupt flag (irr9) in the interrupt mask register (imr) is set to the interrupt enable value at this time, an interrupt can be sent to the cpu. figure 15.12 shows a flowchart for unread message overwriting. section 15 controller area network (hcan) rev. 7.00 sep. 11, 2009 page 424 of 566 rej09b0211-0700 no : settin g s by user unread messa g e overwrite interrupt to cpu end imr9 = 1? umsr = 1 irr9 = 1 clear irr9 messa g e control/messa g e data read : processin g by hardware yes figure 15.12 unread mess age overwrite flowchart 15.4.5 hcan sleep mode the hcan is provided with an hcan sleep mode that places the hcan module in the sleep state in order to reduce current dissipation. figure 15.13 shows a flowchart of the hcan sleep mode. section 15 controller area network (hcan) rev. 7.00 sep. 11, 2009 page 425 of 566 rej09b0211-0700 irr12 = 1 yes mcr5 = 0 yes yes mcr5 = 0 clear sleep mode? yes no no no yes (manual) no (automatic) mcr5 = 1 bus idle? initialize tec and rec bus operation? : settin g s by user : processin g by hardware mb should not be accessed yes no gsr3 = 1? yes no gsr3 = 1? no no imr12 = 1? sleep mode clearin g method mcr7 = 0? 11 recessive bits? can bus communication possible cpu interrupt figure 15.13 hcan sleep mode flowchart section 15 controller area network (hcan) rev. 7.00 sep. 11, 2009 page 426 of 566 rej09b0211-0700 hcan sleep mode is entered by setting the hcan sleep mode bit (mcr5) to 1 in the master control register (mcr). if the can bus is operating, the transition to hcan sleep mode is delayed until the bus becomes idle. either of the following methods of cl earing hcan sleep mode can be selected: ? clearing by software ? clearing by can bus operation eleven recessive bits must be received afte r hcan sleep mode is cleared before can bus communication is re-enabled. clearing by software: hcan sleep mode is cleared by writing a 0 to mcr5 from the cpu. clearing by can bus operation: the cancellation method is selected by the mcr7 bit setting in mcr. clearing by can bus operation occurs automatically when the can bus performs an operation and this change is detected. in this case, the first message is not stored in a mailbox; messages will be received normally from the second message onward. when a change is detected on the can bus in hcan sleep mode, the bus operation interrupt flag (irr12) is set in the interrupt register (irr). if the bus interrupt mask (imr12) in the interrupt mask register (imr) is set to the interrupt enable value at this time, an interrupt can be sent to the cpu. section 15 controller area network (hcan) rev. 7.00 sep. 11, 2009 page 427 of 566 rej09b0211-0700 15.4.6 hcan halt mode the hcan halt mode is provided to enable mailbox settings to be changed without performing an hcan hardware or software reset. figure 15.14 shows a flowchart of the hcan halt mode. mcr1 = 1 yes : settin g s by user : processin g by hardware no bus idle? mbcr settin g mcr1 = 0 can bus communication possible figure 15.14 hcan halt mode flowchart hcan halt mode is entered by setting the halt request bit (mcr1) to 1 in the master control register (mcr). if the can bus is operating, th e transition to hcan halt mode is delayed until the bus becomes idle. hcan halt mode is cleared by clearing mcr1 to 0. section 15 controller area network (hcan) rev. 7.00 sep. 11, 2009 page 428 of 566 rej09b0211-0700 15.5 interrupts table 15.4 lists the hcan interrupt sources. with the exception of the reset processing vector (irr0), these sources can be masked. masking is implemented using the mailbox interrupt mask register (mbimr) and interrupt mask register (i mr). for details on the interrupt vector of each interrupt source, refer to section 5, interrupt controller. table 15.4 hcan interrupt sources name description interrupt flag dtc activation error passive interrupt (tec 128 or rec 128) irr5 bus off interrupt (tec 256) irr6 reset process interrupt by power-on reset irr0 remote frame reception irr2 error warning interrupt (tec 96) irr3 error warning interrupt (rec 96) irr4 overload frame transmission interrupt irr7 unread message overwrite irr9 ers0/ovr0 detection of can bus operation in hcan sleep mode irr12 not possible rm0 mailbox 0 message reception irr1 possible rm1 mailboxes 1 to 15 message reception irr1 not possible sle0 message transmission/cancellation irr8 not possible section 15 controller area network (hcan) rev. 7.00 sep. 11, 2009 page 429 of 566 rej09b0211-0700 15.6 dtc interface the dtc can be activated by the reception of a message in hcan mailbox 0. when dtc transfer ends after dtc activation has been set, the rxpr0 and rfpr0 flags are acknowledge automatically. an interrupt request due to a receive interrupt from the hcan cannot be sent to the cpu in this case. figure 15.15 shows a dtc transfer flowchart. dtc initialization dtc enable re g ister settin g dtc re g ister information settin g yes yes : settin g s by user : processin g by hardware no no messa g e reception in hcan?s mailbox 0 transfer counter = 0 or disel = 1? dtc activation end of dtc transfer? rxpr and rfpr clearin g interrupt to cpu end figure 15.15 dtc transfer flowchart section 15 controller area network (hcan) rev. 7.00 sep. 11, 2009 page 430 of 566 rej09b0211-0700 15.7 can bus interface a bus transceiver ic is necessary to connect this chip to a can bus. a philips pca82c250 transceiver ic is recommended. any other product must be compatible with the pca82c250. figure 15.16 shows a sample connection diagram. rs rxd txd vref vcc canh canl gnd hrxd nc note: nc: no connection htxd this lsi can bus 124 124 vcc pca82c250 figure 15.16 high-speed interface using pca82c250 15.8 usage notes 15.8.1 module stop mode setting hcan operation can be disabled or enabled using the module stop control register. the initial setting is for hcan operation to be halted. regi ster access is enabled by clearing module stop mode. for details, refer to section 20, power-down modes. 15.8.2 reset the hcan is reset by a power-on reset, in hardware standby mode, and in software standby mode. all the registers are in itialized in a reset, however mailboxes (message control (mcx[x])/message data (mdx[x])) are not. after power-on, mailboxes (message control (mcx[x])/message data (mdx[x])) are un-initialized, and their values are undefined. therefore, mailbox initialization must always be carried out after a power-on reset, a transition to hardware standby mode, or software standby mode. the reset interrupt flag (irr0) is always set after a power-on reset or recovery from software sta ndby mode. as this bit cannot be masked in the interrupt mask register (imr), if hcan interrupt enabling is set in the interrupt controller without clearing the flag, an hcan interrupt will be in itiated immediately. irr0 should therefore be cleared during initialization. section 15 controller area network (hcan) rev. 7.00 sep. 11, 2009 page 431 of 566 rej09b0211-0700 15.8.3 hcan sleep mode the bus operation interrupt flag (irr12) in the interrupt register (irr) is set by can bus operation in hcan sleep mode. therefore, this fl ag is not used by the hcan to indicate sleep mode release. note that the reset status bit (gsr3) in the general status register (gsr) is set in sleep mode. 15.8.4 interrupts when the mailbox interrupt mask register (mbimr) is set, the interrupt register (irr8, 2, 1) is not set by reception completion, transmission comple tion, or transmission cancellation for the set mailboxes. 15.8.5 error counters in the case of error active and error passive, re c and tec normally count up and down. in the bus-off state, 11-bit recessive sequences are counted (rec + 1) using rec. if rec reaches 96 during the count, irr4 and gsr1 are set. 15.8.6 register access byte or word access can be used on all hcan registers. longword access cannot be used. 15.8.7 hcan medium-speed mode in medium-speed mode, neither read nor write is possible for the hcan registers. 15.8.8 register hold in standby modes all hcan registers are initialized in hardware standby mode and software standby mode. 15.8.9 usage of bit manipulation instructions the hcan status flags are cleared by writing 1, so do not use a bit manipulation instruction to clear a flag. when clearing a flag, use the mov instruction to write 1 to only the bit that is to be cleared. section 15 controller area network (hcan) rev. 7.00 sep. 11, 2009 page 432 of 566 rej09b0211-0700 15.8.10 hcan txcr operation 1. when the transmit wait cancel regi ster (txcr) is used to cancel a transmit wait message in a transmit wait mailbox, the corresponding bit to txcr and the transmit wait register (txpr) may not be cleared even if transmission is canceled. this occurs when the following conditions are all satisfied. ? the hrxd pin is stacked to 1 because of a can bus error, etc. ? there is at least one mailbox waiting for transmission or being transmitted. ? the message transmission in a mailbox being transmitted is canceled by txcr. if this occurs, transmission is canceled. however, since txpr a nd txcr states are indicated wrongly that a message is being cancelled, transmission cannot be restarted even if the stack state of the hrxd pin is canceled and the can bus recovers the normal state. if there are at least two transmission messages, a message which is not being transmitted is canceled and a message being transmitted retains its state. to avoid this, one of the following countermeasures must be executed. ? transmission must not be canceled by txcr. when transmission is normally completed after the can bus has recovered, txpr is cleared and the hcan recovers the normal state. ? to cancel transmission, the corresponding bit to txcr must be written to 1 continuously until the bit becomes 0. txpr and txcr are cleared and the hcan recovers the normal state. 2. when the bus-off state is entered while txpr is set and the transmit wait state is entered, the internal state machine does not ope rate even if txcr is set during the bus-off state. therefore transmission cannot be canceled. the message can be canceled when one message is transmitted or a transmission error occurs after the bus-off state is recovered. to clear a message after the bus-off state is recovered, th e following countermeasure must be executed. ? a transmit wait message must be cleared by resetting the hcan during the bus-off period. to reset the hcan, the module stop bit (mstpc3 in mstpcrc) must be set or cleared. in this case, the hcan is entirely reset. therefore the initial settings must be made again. section 15 controller area network (hcan) rev. 7.00 sep. 11, 2009 page 433 of 566 rej09b0211-0700 15.8.11 hcan transmit procedure when transmission is set while the bus is in the idle state, if the next transmission is set or the set transmission is canceled under the following conditions within 50 s, the transmit message id of being set may be damaged. ? when the second transmission has the message whose priority is higher than the first one ? when the massage of the highest priority is canceled in the first transmission make whichever setting shown below to avoi d the message ids from being damaged. ? set transmission in one txpr. after transmission of all transmit messages is completed, set transmission again (mass transmission setting). the interval between transmission settings should be 50 s or longer. ? make the transmission setting according to the priority of transmit messages. ? set the interval to be 50 s or longer between txpr and another txpr or between txpr and txcr. table 15.5 interval limitation between txpr and txpr or between txpr and txcr baud rate (bps) set interval ( s) 1 m 50 500 k 50 250 k 50 15.8.12 note on releasing the hcan reset or hcan sleep before releasing the hcan reset or hcan sleep (mcr0 = 0 or mcr5 = 0), confirm that the gsr3 bit (the reset status bit) is set to 1. 15.8.13 note on accessing mailbox during the hcan sleep do not access the mailbox during the hcan sleep . if accessed, the cpu might halt. accessing registers during the hcan sleep does not cause the cpu halt, nor does accessing the mailbox in other than the hcan sleep mode. section 15 controller area network (hcan) rev. 7.00 sep. 11, 2009 page 434 of 566 rej09b0211-0700 section 16 a/d converter rev. 7.00 sep. 11, 2009 page 435 of 566 rej09b0211-0700 section 16 a/d converter this lsi includes a successive approximation type 10-bit a/d converter that allows up to twelve analog input channels to be selected. the block diagram of the a/d converter is shown in figure 16.1. note: the dtc is not supported in h8s/2614 and h8s/2616. 16.1 features ? 10-bit resolution ? twelve input channels ? conversion time: 13.3 s per channel (at 20-mhz operation) ? two operating modes ? single mode: single-channel a/d conversion ? scan mode: continuous a/d conversion on 1 to 4 channels ? four data registers ? conversion results are held in a 16-bit data register for each channel ? sample and hold function ? three methods conversion start ? software ? 16-bit timer pulse unit (tpu) conversion start trigger ? external trigger signal ? interrupt request ? an a/d conversion end interrupt request (adi) can be generated ? module stop mode can be set section 16 a/d converter rev. 7.00 sep. 11, 2009 page 436 of 566 rej09b0211-0700 module data bus control circuit internal data bus 10-bit d/a comparator + ? sample-and- hold circuit adi interrupt bus interface successive approximations re g ister multiplexer adcsr adcr addrd addrc addrb addra an0 an1 an2 an3 an4 an5 an6 an7 le g end: adcr: a/d control re g ister adcsr: a/d control/status re g ister addra: a/d data re g ister a addrb: a/d data re g ister b addrc: a/d data re g ister c addrd: a/d data re g ister d adtrg conversion start tri gg er from tpu an8 an9 an10 an11 /2 /4 /8 /16 av cc av ss figure 16.1 block diagram of a/d converter section 16 a/d converter rev. 7.00 sep. 11, 2009 page 437 of 566 rej09b0211-0700 16.2 input/output pins table 16.1 summarizes the input pins used by the a/d converter. the 12 analog input pins are divided into four channel sets and three groups; analog input pins 0 to 3 (an0 to an3) comprising group 0, analog input pins 4 to 7 (an4 to an7) comprising group 1, and analog input pins 8 to 11 (an8 to an11) comprising group 2. the avcc and avss pins are the power supply pins for the analog block in the a/d converter. table 16.1 pin configuration pin name symbol i/o function analog power supply pin av cc input analog block power supply and reference voltage analog ground pin av ss input analog block ground and reference voltage analog input pin 0 an0 input analog input pin 1 an1 input analog input pin 2 an2 input analog input pin 3 an3 input group 0 analog input pins analog input pin 4 an4 input analog input pin 5 an5 input analog input pin 6 an6 input analog input pin 7 an7 input group 1 analog input pins analog input pin 8 an8 input analog input pin 9 an9 input analog input pin 10 an10 input analog input pin 11 an11 input group 2 analog input pins a/d external trigger input pin adtrg input external trigger input pin for starting a/d conversion section 16 a/d converter rev. 7.00 sep. 11, 2009 page 438 of 566 rej09b0211-0700 16.3 register description the a/d converter has the following registers. for details on register addresses, refer to appendix a, on-chip i/o register. the mstpa1 bit in the module stop control register (mstpcra) specifies the modes of this module as module stop mode. for details on the module stop control register a (mstpcra), refer to section 20.1.2, module stop control register a to c (mstpcra to mstpcrc). ? a/d data register a (addra) ? a/d data register b (addrb) ? a/d data register c (addrc) ? a/d data register d (addrd) ? a/d control/status register (adcsr) ? a/d control register (adcr) 16.3.1 a/d data registers a to d (addra to addrd) there are four 16-bit read-only addr registers; addra to addrd, used to store the results of a/d conversion. the addr registers, which store a conversion result for each channel, are shown in table 16.2. the converted 10-bit data is stored in bits 6 to 15. the lower 6 bits are always read as 0. the data bus between the cpu and the a/d converte r is 8 bits wide. the upper byte can be read directly from the cpu, however the lower byte should be read via a temporary register. the temporary register contents are transferred from the addr when the upper byte data is read. when reading the addr, read the upper byte before the lower byte, or read in word unit. when only the lower byte is read, the contents are not guaranteed. section 16 a/d converter rev. 7.00 sep. 11, 2009 page 439 of 566 rej09b0211-0700 table 16.2 analog input channels and corresponding addr registers analog input channel ch3 = 0 ch3 = 1 group 0 (ch2 = 0) group 1 (ch2 = 1) group 2 (ch2 = 0) ? (ch2 = 1) a/d data register to be stored the results of a/d conversion an0 an4 an8 setting prohibited addra an1 an5 an9 setting prohibited addrb an2 an6 an10 setting prohibited addrc an3 an7 an11 setting prohibited addrd 16.3.2 a/d control/status register (adcsr) adcsr controls a/d conversion operations. bit bit name initial value r/w description 7 adf 0 r/(w) a/d end flag a status flag that indicates the end of a/d conversion. [setting conditions] ? when a/d conversion ends ? when a/d conversion ends on all specified channels [clearing conditions] ? when 0 is written after reading adf = 1 ? when the dtc is activated by an adi interrupt and addr is read 6 adie 0 r/w a/d interrupt enable a/d conversion end interrupt (adi) request enabled when 1 is set section 16 a/d converter rev. 7.00 sep. 11, 2009 page 440 of 566 rej09b0211-0700 bit bit name initial value r/w description 5 adst 0 r/w a/d start clearing this bit to 0 stops a/d conversion, and the a/d converter enters the wait state. setting this bit to 1 starts a/d conversion. in single mode, this bits is cleared to 0 automatically when conversion on the specified channel is complete. in scan mode, conversion continues sequentially on the specified channels until this bit is cleared to 0 by software, a reset, or a transition to software standby mode, hardware standby mode or module stop mode. 4 scan 0 r/w scan mode selects single mode or scan mode as the a/d conversion operating mode. 0: single mode 1: scan mode 3 2 1 0 ch3 ch2 ch1 ch0 0 0 0 0 r/w r/w r/w r/w channel select 0 to 3 select analog input channels. when scan = 0 when scan = 1 0000: an0 0000: an0 0001: an1 0001: an0 and an1 0010: an2 0010: an0 to an2 0011: an3 0011: an0 to an3 0100: an4 0100: an4 0101: an5 0101: an4 and an5 0110: an6 0110: an4 to an6 0111: an7 0111: an4 to an7 1000: an8 1000: an8 1001: an9 1001: an8 and an9 1010: an10 1010: an8 to an10 1011: an11 1011: an8 to an11 1100: setting prohibited 1100: setting prohibited 1101: setting prohibited 1101: setting prohibited 1110: setting prohibited 1110: setting prohibited 1111: setting prohibited 1111: setting prohibited section 16 a/d converter rev. 7.00 sep. 11, 2009 page 441 of 566 rej09b0211-0700 16.3.3 a/d control register (adcr) the adcr enables a/d conversion started by an external trigger signal. bit bit name initial value r/w description 7 6 trgs1 trgs0 0 0 r/w r/w timer trigger select 0 and 1 enables the start of a/d conversion by a trigger signal. only set bits trgs0 and trgs1 while conversion is stopped (adst = 0). 00: a/d conversion start by software is enabled 01: a/d conversion start by tpu conversion start trigger is enabled 10: setting prohibited 11: a/d conversion start by external trigger pin ( adtrg ) is enabled 5, 4 ? all 1 ? reserved these bits are always read as 1. 3 2 cks1 cks0 0 0 r/w r/w clock select 0 and 1 these bits specify the a/d conversion time. the conversion time should be changed only when adst = 0. specify a setting that gives a value within the range shown in table 21.7. 00: conversion time = 530 states (max.) 01: conversion time = 266 states (max.) 10: conversion time = 134 states (max.) 11: conversion time = 68 states (max.) 1, 0 ? all 1 ? reserved these bits are always read as 1. section 16 a/d converter rev. 7.00 sep. 11, 2009 page 442 of 566 rej09b0211-0700 16.4 operation the a/d converter operates by successive appr oximation with 10-bit resolution. it has two operating modes; single mode and scan mode. when changing the operating mode or analog input channel, in order to prevent incorrect operation, first clear the bit adst to 0 in adcsr. the adst bit can be set at the same time as the opera ting mode or analog input channel is changed. 16.4.1 single mode in single mode, a/d conversion is to be performed only once on the specified single channel. the operations are as follows. 1. a/d conversion is started when the adst bit is set to 1, according to software or external trigger input. 2. when a/d conversion is completed, the result is transferred to the corresponding a/d data register to the channel. 3. on completion of conversion, the adf bit in adcsr is set to 1. if the adie bit is set to 1 at this time, an adi interrupt request is generated. 4. the adst bit remains set to 1 during a/d conversion. when a/d converion ends, the adst bit is automatically cleared to 0 and the a/d converter enters the wait state. 16.4.2 scan mode in scan mode, a/d conversion is to be performed sequentially on the specified channels (four channels maximum). the operations are as follows. 1. when the adst bit is set to 1 by software, tpu or external trigger input, a/d conversion starts on the first channel in the group (an0 when ch3 and ch2 = 00, an4 when ch3 and ch2 = 01, or an8 when ch3 and ch2 = 10). 2. when a/d conversion for each channel is completed, the result is sequentially transferred to the a/d data register corresponding to each channel. 3. when conversion of all the selected channels is completed, the adf flag is set to 1. if the adie bit is set to 1 at this time, an adi in terrupt is requested after a/d conversion ends. conversion of the first channel in the group starts again. 4. steps 2 to 3 are repeated as long as the adst bit remains set to 1. when the adst bit is cleared to 0, a/d conversion stops and the a/d converter enters the wait state. section 16 a/d converter rev. 7.00 sep. 11, 2009 page 443 of 566 rej09b0211-0700 16.4.3 input sampling and a/d conversion time the a/d converter has a built-in sample-and-hold circuit. the a/d converter samples the analog input when the a/d conversion start delay time (t d ) has passed after the adst bit is set to 1, then starts conversion. figure 16.2 shows the a/d conversion timing. table 16.3 shows the a/d conversion time. as indicated in figure 16.2, the a/d conversion time (t conv ) includes t d and the input sampling time (t spl ). the length of t d varies depending on the timing of the write access to adcsr. the total conversion time therefore varies within the ranges indicated in table 16.3. in scan mode, the values given in table 16.3 apply to the first conversion time. the values given in table 16.4 apply to the second and subsequent conversions. in both cases, set bits cks1 and cks0 in adcr to give an a/d conversion time within the range shown in table 21.7. (1) (2) t d t spl t conv address write si g nal input samplin g timin g adf le g end: (1): adcsr write cycle (2) adcsr address t d : a/d conversion start delay t spl : input samplin g time t conv : a/d conversion time figure 16.2 a/d conversion timing section 16 a/d converter rev. 7.00 sep. 11, 2009 page 444 of 566 rej09b0211-0700 table 16.3 a/d conversion time (single mode) cks1 = 0 cks1 = 1 cks0 = 0 cks0 = 1 cks0 = 0 cks0 = 1 item symbol min. typ. max. min. typ. max. min. typ. max. min. typ. max. a/d conversion start delay t d 18 ? 33 10 ? 17 6 ? 9 4 ? 5 input sampling time t spl ? 127 ? ? 63 ? ? 31 ? ? 15 ? a/d conversion time t conv 515 ? 530 259 ? 266 131 ? 134 67 ? 68 note: all values represent the number of states. table 16.4 a/d conversion time (scan mode) cks1 cks0 conversion time (state) 0 512 (fixed) 0 1 256 (fixed) 1 0 128 (fixed) 1 64 (fixed) section 16 a/d converter rev. 7.00 sep. 11, 2009 page 445 of 566 rej09b0211-0700 16.4.4 external trigger input timing a/d conversion can be externally triggered. when the trgs0 and trgs1 bits are set to 11 in adcr, external trigger input is enabled at the adtrg pin. a falling edge at the adtrg pin sets the adst bit to 1 in adcsr, starting a/d conversion. other operations, in both single and scan modes, are the same as when the bit adst has been set to 1 by software. figure 16.3 shows the timing. adtrg internal tri gg er si g nal adst a/d conversion figure 16.3 external trigger input timing 16.5 interrupts the a/d converter generates an a/d conversion end interrupt (adi) at the end of a/d conversion. setting the adie bit to 1 enables adi interrupt requests while the bit adf in adcsr is set to 1 after a/d conversion is completed. the dtc can be activated by an adi interrupt. having the converted data read by the dtc in response to an adi interrupt enables continuous conversion without imposing a load on software. table 16.5 a/d converter interrupt source name interrupt source interrupt source flag dtc activation adi a/d conversion completed adf possible section 16 a/d converter rev. 7.00 sep. 11, 2009 page 446 of 566 rej09b0211-0700 16.6 a/d conversion precision definitions this lsi's a/d conversion precisi on definitions are given below. ? resolution the number of a/d converter digital output codes ? quantization error the deviation inherent in the a/d converter, given by 1/2 lsb (see figure 16.4). ? offset error the deviation of the analog input voltage value from the ideal a/d conversion characteristic when the digital output changes from the minimum voltage value b'0000000000 (h'00) to b'0000000001 (h'01) (see figure 16.5). ? full-scale error the deviation of the analog input voltage value from the ideal a/d conversion characteristic when the digital output changes from b'1111111110 (h'3e) to b'1111111111 (h'3f) (see figure 16.5). ? nonlinearity error the error with respect to the ideal a/d conversion characteristic between zero voltage and full- scale voltage. does not include offset error, fu ll-scale error, or quantization error (see figure 16.5). ? absolute precision the deviation between the digital value and the analog input value. includes offset error, full- scale error, quantization erro r, and nonlinearity error. section 16 a/d converter rev. 7.00 sep. 11, 2009 page 447 of 566 rej09b0211-0700 111 110 101 100 011 010 001 000 1 1024 2 1024 1022 1024 1023 1024 fs quantization error digital output ideal a/d conversion characteristic analog input voltage figure 16.4 a/d conversio n precision definitions fs di g ital output ideal a/d conversion characteristic nonlinearity error analo g input volta g e offset error actual a/d conversion characteristic full-scale error figure 16.5 a/d conversio n precision definitions section 16 a/d converter rev. 7.00 sep. 11, 2009 page 448 of 566 rej09b0211-0700 16.7 usage notes 16.7.1 module stop mode setting operation of the a/d converter can be disabled or enabled using the module stop control register. the initial setting is for operation of the a/d convert er to be halted. register access is enabled by clearing module stop mode. for details, refer to section 20, power-down modes. 16.7.2 permissible sign al source impedance this lsi's analog input is designed such that conversion precision is guaranteed for an input signal for which the signal source impedance is 5 k or less. this specification is provided to enable the a/d converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 5 k , charging may be insufficient and it may not be possible to guarantee a/d conversion precision. however, for a/d conversion in single mode with a large capacitance provided externa lly, the input load will essentia lly comprise only the internal input resistance of 10 k , and the signal source impedance is ignored. however, as a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mv/ s or greater) (see figure 16.6). when converting a high-speed analog signal, a low-impedance buffer should be inserted. 16.7.3 influences on absolute precision adding capacitance results in coupling with gnd, and therefore noise in gnd may adversely affect absolute precision. be sure to make the connection to an electrically stable gnd such as avss. care is also required to insure that filter circuits do not communicate with digital signals on the mounting board (i.e, acting as antennas). 20 pf 10 k c in = 15 pf sensor output impedance to 5 k this lsi low-pass filter c to 0.1 f sensor input a/d converter equivalent circuit figure 16.6 example of analog input circuit section 16 a/d converter rev. 7.00 sep. 11, 2009 page 449 of 566 rej09b0211-0700 16.7.4 range of analog power supply and other pin settings if the conditions below are not met, the reliability of the device may be adversely affected. ? analog input voltage range the voltage applied to analog input pin ann during a/d conversion should be in the range avss v an avcc. ? relationship between avcc, avss and vcc, vss set avss = vss as the relationship between avcc, avss and vcc, vss. if the a/d converter is not used, the avcc and avss pins must not be left open. 16.7.5 notes on board design in board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. fa ilure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting a/d conversion values. also, digital circuitry must be isolated from the analog input signals (an0 to an11), and analog power supply (avcc) by the analog ground (avss). also, the analog ground (avss) should be connected at one point to a stable digital ground (vss) on the board. 16.7.6 notes on noise countermeasures a protection circuit should be connected in order to prevent damage due to abnormal voltage, such as an excessive surge at the analog input pins (an0 to an11), between avcc and avss, as shown in figure 16.7. also, the bypass capacitors connect ed to avcc and the filte r capacitor connected to an0 to an11 must be connected to avss. if a filter capacitor is connected, th e input currents at the analog input pins (an0 to an11) are averaged, and so an error may arise. also, when a/d conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the a/d converter exceeds the curre nt input via the input impedance (r in ), an error will arise in the analog input pin voltage. careful consideration is therefore required when deciding circuit constants. section 16 a/d converter rev. 7.00 sep. 11, 2009 page 450 of 566 rej09b0211-0700 avcc * 1 an0 to an11 avss r in * 2 100 0.1 f 0.01 f 10 f notes: values are reference values. 1. 2. r in : input impedance figure 16.7 example of analog input protection circuit table 16.6 analog pin specifications item min max unit analog input capacitance ? 20 pf permissible signal source impedance ? 5 k 20 pf an0 to an11 note: values are reference values. 10 k to a/d converte r figure 16.8 analog input pin equivalent circuit section 17 ram rev. 7.00 sep. 11, 2009 page 451 of 566 rej09b0211-0700 section 17 ram this lsi has 4 kbytes of on-chip high-speed static ram. the ram is connected to the cpu by a 16-bit data bus, enabling one-state access by th e cpu to both byte data and word data. the on-chip ram can be enabled or disabled by means of the rame bit in the system control register (syscr). for details on the system cont rol register (syscr), refer to section 3.2.2, system control register (syscr). note: no dtc is implemented in the h8s/2614 and h8s/2616. section 17 ram rev. 7.00 sep. 11, 2009 page 452 of 566 rej09b0211-0700 section 18 rom rev. 7.00 sep. 11, 2009 page 453 of 566 rej09b0211-0700 section 18 rom the features of the flash memory are summarized below. the block diagram of the flash memory is shown in figure 18.1. 18.1 features ? size: 128 kbytes ? programming/erase methods ? the flash memory is programmed 128 bytes at a time. erase is performed in single-block units. the flash memory is configured as follows: 32 kbytes 2 blocks, 28 kbytes 1 block, 16 kbytes 1 block, 8 kbytes 2 blocks, and 1 kbyte 4 blocks. to erase the entire flash memory, each block must be erased in turn. ? reprogramming capability ? the flash memory can be reprogrammed up to 100 times. ? three programming modes ? boot mode ? user mode ? programmer mode on-board programming/erasing can be done in boot mode, in which the boot program built into the chip is started to erase or program of the entire flash memory. in normal user program mode, individual blocks can be erased or programmed. ? programmer mode ? flash memory can be programmed/erased in programmer mode using a prom programmer, as well as in on-board programming mode. ? automatic bit rate adjustment ? for data transfer in boot mode, this lsi's bit rate can be automatically adjusted to match the transfer bit rate of the host. ? programming/erasing protection ? sets software protection against flash memory programming/erasing. section 18 rom rev. 7.00 sep. 11, 2009 page 454 of 566 rej09b0211-0700 module bus bus interface/controller flash memory (128 kbytes) operatin g mode flmcr2 internal address bus internal data bus (16 bits) fwe pin mode pin ebr1 ebr2 ramer flmcr1 flash memory control re g ister 1 flash memory control re g ister 2 erase block re g ister 1 erase block re g ister 2 ram emulation re g ister le g end: flmcr1: flmcr2: ebr1: ebr2: ramer: figure 18.1 block diagram of flash memory 18.2 mode transitions when the mode pins and the fwe pin are set in th e reset state and a reset-start is executed, this lsi enters an operating mode as shown in figure 18.2. in user mode, flash memory can be read but not programmed or erased. the boot, user program and programmer modes are provided as modes to write and erase the flash memory. the differences between boot mode and user program mode are shown in table 18.1. section 18 rom rev. 7.00 sep. 11, 2009 page 455 of 566 rej09b0211-0700 figure 18.3 shows the operation flow for boot mode and figure 18.4 shows that for user program mode. boot mode on-board pro g rammin g mode user pro g ram mode user mode (on-chip rom enabled) reset state pro g rammer mode res = 0 fwe = 1 fwe = 0 * 1 * 1 * 2 notes: only make a transition between user mode and user pro g ram mode when the cpu is not accessin g the flash memory. 1. ram emulation possible 2. this lsi transits to pro g rammer mode by usin g the dedicated prom pro g rammer. res = 0 md2 = 0, md1 = 1, fwe = 1 res = 0 res = 0 md1 = 1, md2 = 1, fwe = 0 md1 = 1, md2 = 1, fwe = 1 figure 18.2 flash memory state transitions table 18.1 differences between boot mode and user program mode boot mode user program mode total erase yes yes block erase no yes programming control program * (2) (1) (2) (3) (1) erase/erase-verify (2) program/program-verify (3) emulation note: * to be provided by the user, in accordance with the recommended algorithm. section 18 rom rev. 7.00 sep. 11, 2009 page 456 of 566 rej09b0211-0700 flash memory this lsi ram host pro g rammin g control pro g ram sci application pro g ram (old version) new application pro g ram flash memory this lsi ram host sci application pro g ram (old version) boot pro g ram area new application pro g ram flash memory this lsi ram host sci flash memory prepro g rammin g erase boot pro g ram new application pro g ram flash memory this lsi pro g ram execution state ram host sci new application pro g ram boot pro g ram pro g rammin g control pro g ram 1. initial state the old pro g ram version or data remains written in the flash memory. the user should prepare the pro g rammin g control pro g ram and new application pro g ram beforehand in the host. 2. pro g rammin g control pro g ram transfer when boot mode is entered, the boot pro g ram in this lsi (ori g inally incorporated in the chip) is started and the pro g rammin g control pro g ram in the host is transferred to ram via sci communication. the boot pro g ram required for flash memory erasin g is automatically transferred to the ram boot pro g ram area. 3. flash memory initialization the erase pro g ram in the boot pro g ram area (in ram) is executed, and the flash memory is initialized (to h'ff). in boot mode, total flash memory erasure is performed, without re g ard to blocks. 4. writin g new application pro g ram the pro g rammin g control pro g ram transferred from the host to ram is executed, and the new application pro g ram in the host is written into the flash memory. pro g rammin g control pro g ram boot pro g ram boot pro g ram boot pro g ram area boot pro g ram area pro g rammin g control pro g ram figure 18.3 boot mode section 18 rom rev. 7.00 sep. 11, 2009 page 457 of 566 rej09b0211-0700 flash memory this lsi ram host pro g rammin g / erase control pro g ram sci boot pro g ram new application pro g ram flash memory this lsi ram host sci new application pro g ram flash memory this lsi ram host sci flash memory erase boot pro g ram new application pro g ram flash memory this lsi pro g ram execution state ram host sci boot pro g ram boot pro g ram fwe assessment pro g ram application pro g ram (old version) new application pro g ram 1. initial state the fwe assessment pro g ram that confirms that user pro g ram mode has been entered, and the pro g ram that will transfer the pro g rammin g /erase control pro g ram from flash memory to on-chip ram should be written into the flash memory by the user beforehand. the pro g rammin g /erase control pro g ram should be prepared in the host or in the flash memory. 2. pro g rammin g /erase control pro g ram transfer when user pro g ram mode is entered, user software confirms this fact, executes transfer pro g ram in the flash memory, and transfers the pro g rammin g /erase control pro g ram to ram. 3. flash memory initialization the pro g rammin g /erase pro g ram in ram is executed, and the flash memory is initialized (to h'ff). erasin g can be performed in block units, but not in byte units. 4. writin g new application pro g ram next, the new application pro g ram in the host is written into the erased flash memory blocks. do not write to unerased blocks. pro g rammin g / erase control pro g ram pro g rammin g / erase control pro g ram pro g rammin g / erase control pro g ram transfer pro g ram application pro g ram (old version) transfer pro g ram fwe assessment pro g ram fwe assessment pro g ram transfer pro g ram fwe assessment pro g ram transfer pro g ram figure 18.4 user program mode section 18 rom rev. 7.00 sep. 11, 2009 page 458 of 566 rej09b0211-0700 18.3 block configuration figure 18.5 shows the block configuration of 128-kbyte flash memory. the thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. the flash memory is divided into 32 kbytes (2 blocks), 28 kbytes (1 block), 16 kbytes (1 block), 8 kbytes (2 blocks), and 1 kbyte (4 blocks). erasing is performed in these units. programming is performed in 128-byte units starting from an address with lower eight bits h'00 or h'80. eb0 erase unit 1 kbyte eb1 erase unit 1 kbyte eb2 erase unit 1 kbyte eb3 erase unit 1 kbyte eb4 erase unit 28 kbytes eb5 erase unit 16 kbytes eb6 erase unit 8 kbytes eb7 erase unit 8 kbytes eb8 erase unit 32 kbytes eb9 erase unit 32 kbytes h'000000 h'000001 h'000002 h'00007f h'0003ff h'00047f h'00087f h'000c7f h'00107f h'007fff h'00807f h'00bfff h'0007ff h'000bff h'000fff h'01ffff h'00c07f h'00dfff h'00e07f h'00ffff h'01007f h'017fff h'01807f h'000400 h'000401 h'000402 h'000780 h'000781 h'000782 h'000800 h'000801 h'000802 h'000b80 h'000b81 h'000b82 h'000f80 h'000f81 h'000f82 h'007f80 h'007f81 h'007f82 h'00bf80 h'00bf81 h'00bf82 h'00df80 h'00df81 h'00df82 h'00ff80 h'00ff81 h'00ff82 h'017f80 h'017f81 h'017f82 h'01ff80 h'01ff81 h'01ff82 h'000c00 h'000c01 h'000c02 h'001000 h'001001 h'001002 h'008000 h'008001 h'008002 h'00c000 h'00c001 h'00c002 h'00e000 h'00e001 h'00e002 h'010000 h'010001 h'010002 h'018000 h'018001 h'018002 h'000380 h'000381 h'000382 pro g rammin g unit: 128 bytes pro g rammin g unit: 128 bytes pro g rammin g unit: 128 bytes pro g rammin g unit: 128 bytes pro g rammin g unit: 128 bytes pro g rammin g unit: 128 bytes pro g rammin g unit: 128 bytes pro g rammin g unit: 128 bytes pro g rammin g unit: 128 bytes pro g rammin g unit: 128 bytes figure 18.5 flash memory block configuration section 18 rom rev. 7.00 sep. 11, 2009 page 459 of 566 rej09b0211-0700 18.4 input/output pins the flash memory is controlled by means of the pins shown in table 18.2. table 18.2 pin configuration pin name i/o function res input reset fwe input flash program/erase protection by hardware md2 input sets this lsi?s operating mode md1 input sets this lsi?s operating mode md0 input sets this lsi?s operating mode txd2 output serial transmit data output rxd2 input serial receive data input 18.5 register descriptions the flash memory has the following registers. for details on register addresses and register states during each processing, refer to appendix a, on-chip i/o register. ? flash memory control register 1 (flmcr1) ? flash memory control register 2 (flmcr2) ? erase block register 1 (ebr1) ? erase block register 2 (ebr2) ? ram emulation register (ramer) 18.5.1 flash memory control register 1 (flmcr1) flmcr1 is a register that makes the flash memory change to program mode, program-verify mode, erase mode, or erase-verify mode. for details on register setting, refer to section 18.8, flash memory programming/erasing. section 18 rom rev. 7.00 sep. 11, 2009 page 460 of 566 rej09b0211-0700 bit bit name initial value r/w description 7 fwe ? r reflects the input level at the fwe pin. it is cleared to 0 when a low level is input to the fwe pin, and set to 1 when a high level is input. 6 swe 0 r/w software write enable bit when this bit is set to 1, flash memory programming/erasing is enabled. when this bit is cleared to 0, other flmcr1 register bits and all ebr1 and ebr2 bits cannot be set. 5 esu1 0 r/w erase setup bit when this bit is set to 1, the flash memory changes to the erase setup state. when it is cleared to 0, the erase setup state is cancelled. 4 psu1 0 r/w program setup bit when this bit is set to 1, the flash memory changes to the program setup state. when it is cleared to 0, the program setup state is cancelled. set this bit to 1 before setting the p1 bit in flmcr1. 3 ev1 0 r/w erase-verify when this bit is set to 1, the flash memory changes to erase-verify mode. when it is cleared to 0, erase- verify mode is cancelled. 2 pv1 0 r/w program-verify when this bit is set to 1, the flash memory changes to program-verify mode. when it is cleared to 0, program-verify mode is cancelled. 1 e1 0 r/w erase when this bit is set to 1, and while the swe1 and esu1 bits are 1, the flash memory changes to erase mode. when it is cleared to 0, erase mode is cancelled. 0 p1 0 r/w program when this bit is set to 1, and while the swe1 and psu1 bits are 1, the flash memory changes to program mode. when it is cleared to 0, program mode is cancelled. section 18 rom rev. 7.00 sep. 11, 2009 page 461 of 566 rej09b0211-0700 18.5.2 flash memory control register 2 (flmcr2) flmcr2 is a register that displays the state of flash memory programming/erasing. flmcr2 is a read-only register, and should not be written to. bit bit name initial value r/w description 7 fler 0 r indicates that an error has occurred during an operation on flash memory (programming or erasing). when fler is set to 1, flash memory goes to the error-protection state. see section 18.9.3, error protection, for details. 6 to 0 ? all 0 ? reserved these bits are always read as 0. 18.5.3 erase block register 1 (ebr1) ebr1 specifies the flash memory erase area block. ebr1 is initialized to h'00 when the swe bit in flmcr1 is 0. do not set more than one bit at a time, as this will cause all the bits in ebr1 to be automatically cleared to 0. bit bit name initial value r/w description 7 eb7 0 r/w when this bit is set to 1, 8 kbytes of eb7 (h'00e000 to h'00ffff) will be erased. 6 eb6 0 r/w when this bit is set to 1, 8 kbytes of eb6 (h'00c000 to h'00dfff) will be erased. 5 eb5 0 r/w when this bit is set to 1, 16 kbytes of eb5 (h'008000 to h'00bfff) will be erased. 4 eb4 0 r/w when this bit is set to 1, 28 kbytes of eb4 (h'001000 to h'007fff) will be erased. 3 eb3 0 r/w when this bit is set to 1, 1 kbyte of eb3 (h'000c00 to h'000fff) will be erased. 2 eb2 0 r/w when this bit is set to 1, 1 kbyte of eb2 (h'000800 to h'000bff) will be erased. 1 eb1 0 r/w when this bit is set to 1, 1 kbyte of eb1 (h'000400 to h'0007ff) will be erased. 0 eb0 0 r/w when this bit is set to 1, 1 kbyte of eb0 (h'000000 to h'0003ff) will be erased. section 18 rom rev. 7.00 sep. 11, 2009 page 462 of 566 rej09b0211-0700 18.5.4 erase block register 2 (ebr2) ebr2 specifies the flash memory erase area block. ebr2 is initialized to h'00 when the swe bit in flmcr1 is 0. do not set more than one bit at a time, as this will cause all the bits in ebr2 to be automatically cleared to 0. bit bit name initial value r/w description 7 to 2 ? all 0 ? reserved these bits are always read as 0. 1 eb9 0 r/w when this bit is set to 1, 32 kbytes of eb9 (h'018000 to h'01ffff) will be erased. 0 eb8 0 r/w when this bit is set to 1, 32 kbytes of eb8 (h'010000 to h'017fff) will be erased. 18.5.5 ram emulation register (ramer) ramer specifies the area of flash memory to be overlapped with part of ram when emulating real-time flash memory programming. ramer settings should be made in user mode or user program mode. to ensure correct operation of the emulation function, the rom for which ram emulation is performed sh ould not be accessed immedi ately after this regist er has been modified. normal execution of an access immediately afte r register modificati on is not guaranteed. bit bit name initial value r/w description 7, 6 ? all 0 ? reserved these bits are always read as 0. 5, 4 ? all 0 r/w reserved only 0 should be written to these bits. 3 rams 0 r/w ram select specifies selection or non-selection of flash memory emulation in ram. when rams = 1, the flash memory is overlapped with part of ram, and all flash memory block are program/erase- protected. section 18 rom rev. 7.00 sep. 11, 2009 page 463 of 566 rej09b0211-0700 bit bit name initial value r/w description 2 1 0 ram2 ram1 ram0 0 0 0 r/w r/w r/w flash memory area selection when the rams bit is set to 1, one of the following flash memory areas are selected to overlap the ram area of h'ffe000 to h'ffe3ff. the areas correspond with 1-kbyte erase blocks. 00x: h'000000 to h'0003ff (eb0) 01x: h'000400 to h'0007ff (eb1) 10x: h'000800 to h'000bff (eb2) 11x: h'000c00 to h'000fff (eb3) note: x: don?t care 18.6 on-board programming modes there are two modes for programming/erasing of the flash memory; boot mode, which enables on- board programming/erasing, and programmer mode , in which programming/erasing is performed with a prom programmer. on-board programming/erasing can also be performed in user program mode. at reset-start in reset mode, this lsi changes to a mode depending on the md pin settings and fwe pin setting, as s hown in table 18.3. the input leve l of each pin must be defined four states before the reset ends. when changing to boot mode, the boot program bu ilt into this lsi is in itiated. the boot program transfers the programming control program from the externally-connected host to on-chip ram via sci_2. after erasing the entire flash memory, the programming control program is executed. this can be used for programming initial values in the on-board state or for a forcible return when programming/erasing can no longer be done in user program mode. in user program mode, individual blocks can be erased and programmed by branching to the user program/erase control program prepared by the user. table 18.3 setting on-board programming modes md2 md1 md0 fwe lsi state after reset end 1 1 1 1 user mode 0 1 1 1 boot mode section 18 rom rev. 7.00 sep. 11, 2009 page 464 of 566 rej09b0211-0700 18.6.1 boot mode table 18.4 shows the boot mode operations between reset end and branching to the programming control program. 1. when boot mode is used, the flash memory programming control program must be prepared in the host beforehand. prepare a programming control program in accordance with the description in section 18.8, flash memory programming/erasing. 2. sci_2 should be set to asynchronous mode, and the transfer format as follows: 8-bit data, 1 stop bit, and no parity. 3. when the boot program is initiated, the chip measures the low-level period of asynchronous sci communication data (h'00) transmitted continuously from the host. the chip then calculates the bit rate of transmission from the host, and adjusts the sci_2 bit rate to match that of the host. the reset should end with the rxd pin high. the rxd and txd pins should be pulled up on the board if necessary. after the reset is complete, it takes approximately 100 states before the chip is ready to measure the low-level period. 4. after matching the bit rates, the chip transmits one h'00 byte to the host to indicate the completion of bit rate adjustment. the host should confirm that this adjustment end indication (h'00) has been received normally, and transmit one h'55 byte to the chip. if reception could not be performed normally, initiate boot mode again by a reset. depending on the host's transfer bit rate and system clock frequency of this lsi, there will be a discrepancy between the bit rates of the host and the chip. to operate the sci properly, set the host's transfer bit rate and system clock frequency of this lsi within the ranges listed in table 18.5. 5. in boot mode, a part of the on-chip ram area is used by the boot program. the area h'ffe800 to h'ffefbf is the area to which the programming control program is transferred from the host. the boot program area cannot be used until the execution state in boot mode switches to the programming control program. 6. before branching to the programming control program, the chip terminates transfer operations by sci_2 (by clearing the re and te bits in scr to 0), however the adjusted bit rate value remains set in brr. therefore, the programming control program can still use it for transfer of write data or verify data with the host. the txd pin is high. the contents of the cpu general registers are undefined immediately after branching to the programming control program. these registers must be initialized at the beginning of the programming control program, as the stack pointer (sp), in particular, is used implicitly in subroutine calls, etc. 7. boot mode can be cleared by a reset. end the reset after driving the reset pin low, waiting at least 20 states, and then setting the mode (md) pins. boot mode is also cleared when a wdt overflow occurs. 8. do not change the md pin input levels in boot mode. 9. all interrupts are disabled during programming or erasing of the flash memory. section 18 rom rev. 7.00 sep. 11, 2009 page 465 of 566 rej09b0211-0700 table 18.4 boot mode operation item host operation communi c ations contents lsi operation boot mode start branches to boot pro g ram at reset-start. pro c essing contents pro c essing contents bit rate adjustment continuously transmits data h'00 at specified bit rate. h'00, h'00 ...... h'00 h'00 h'55 . measures low-level period of receive data h'00. . calculates bit rate and sets it in brr of sci_2. . transmits data h'00 to host as adjustment end indication. transmits data h'aa to host when data h'55 is received. transmits data h'55 when data h'00 is received error-free. transmits number of bytes (n) of pro g rammin g control pro g ram to be transferred as 2-byte data (low-order byte followin g hi g h-order byte). receives data h'aa. transmits 1-byte of pro g rammin g control pro g ram (repeated for n times). receives data h'aa. transfer of pro g rammin g control pro g ram flash memory erase boot pro g ram initiation echobacks the 2-byte data received. branches to pro g rammin g control pro g ram transferred to on-chip ram and starts execution. echobacks received data to host and also transfers it to ram (repeated for n times). checks flash memory data, erases all flash memory blocks in case of written data existin g , and transmits data h'aa to host. (if erase could not be done, transmits data h'ff to host and aborts operation.) hi g h-order byte and low-order byte h'xx h'aa echoback echoback h'ff h'aa boot pro g ram erase error table 18.5 system clock frequencies for which automatic adjustment of lsi bit rate is possible host bit rate system clock frequency range of lsi 19,200 bps 20 mhz 9,600 bps 8 to 20 mhz 4,800 bps 4 to 20 mhz section 18 rom rev. 7.00 sep. 11, 2009 page 466 of 566 rej09b0211-0700 18.6.2 programming/erasing in user program mode on-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program. the user must set branching conditions and provide on-board means of supplying programming data. the flash memory must contain the user program/erase control program or a program that provides the user program/erase control program from external memory. as the flash memory itself cannot be read during programming/erasing, transfer the user program/erase control program to on-chip ram, as in boot mode. figure 18.6 shows a sample procedure for programming/erasing in user program mode. prepare a user program/erase control program in accordance with the description in section 18.8, flash memory programming/erasing. section 18 rom rev. 7.00 sep. 11, 2009 page 467 of 566 rej09b0211-0700 ye s no pro g ram/erase? transfer user pro g ram/erase control pro g ram to ram reset-start branch to user pro g ram/erase control pro g ram in ram execute user pro g ram/erase control pro g ram (flash memory rewrite) branch to flash memory application pro g ram branch to flash memory application pro g ram fwe = hi g h * clear fwe do not constantly apply a hi g h level to the fwe pin. only apply a hi g h level to the fwe pin when pro g rammin g or erasin g the flash memory. to prevent excessive pro g rammin g or excessive erasin g , while a hi g h level is bein g applied to the fwe pin, activate the watchdo g timer in case of handlin g cpu runaways. note: * figure 18.6 programming/erasing flowchart example in user program mode section 18 rom rev. 7.00 sep. 11, 2009 page 468 of 566 rej09b0211-0700 18.7 flash memory emulation in ram a setting in the ram emulation register (ramer) enables part of ram to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in ram in real time. emulation can be performed in user mode or user program mode. figure 18.7 shows an example of emulation of real-time flash memory programming. 1. set ramer to overlap part of ram onto the area for which real-time programming is required. 2. emulation is performed using the overlapping ram. 3. after the program data has been confirmed, the rams bit is cleared, thus releasing the ram overlap. 4. the data written in the overlapping ram is written into the flash memory space (eb0). start of emulation pro g ram set ramer write tunin g data to overlap ram execute application pro g ram tunin g ok? clear ramer write to flash memory emulation block end of emulation pro g ram no ye s figure 18.7 flowchart for flash memory emulation in ram section 18 rom rev. 7.00 sep. 11, 2009 page 469 of 566 rej09b0211-0700 an example in which flash memory block area eb0 is overlapped is shown in figure 18.8. 1. the ram area to be overlapped is fixed at a 1-kbyte area in the range h'ffe000 to h'ffe3ff. 2. the flash memory area to overlap is selected by ramer from a 1-kbyte area of the eb0 to eb3 blocks. 3. the overlapped ram area can be accessed from both the flash memory addresses and ram addresses. 4. when the rams bit in ramer is set to 1, program/erase protection is enabled for all flash memory blocks (emulation protection). in this state, setting the p1 or e1 bit in flmcr1 to 1 does not cause a transition to program mode or erase mode. 5. a ram area cannot be erased by execution of software in accordance with the erase algorithm. 6. block area eb0 contains the vector table. when performing ram emulation, the vector table is needed in the overlap ram. h'000000 flash memory (eb0) flash memory (eb0) (eb1) (eb2) (eb3) h'0003ff h'000400 h'0007ff h'000800 h'000bff h'000c00 h'000fff h'ffe000 h'ffe3ff on-chip ram (1 kbyte) on-chip ram (shadow of h'ffe000 to h'ffe3ff) flash memory (eb2) on-chip ram (1 kbyte) (eb3) normal memory map ram overlap memory map figure 18.8 example of ram overlap operation section 18 rom rev. 7.00 sep. 11, 2009 page 470 of 566 rej09b0211-0700 18.8 flash memory programming/erasing a software method using the cpu is employed to program and erase flash memory in the on- board programming modes. depending on the flmcr1 setting, the flash memory operates in one of the following four modes: program mode, program-verify mode, erase mode, and erase-verify mode. the programming control program in boot mode and the user program/erase control program in user program mode use these operating modes in combination to perform programming/erasing. flash memory programming and erasing should be performed in accordance with the descriptions in section 18.8. 1, program/program-verify and section 18.8.2, erase/erase-verify, respectively. 18.8.1 program/program-verify when writing data or programs to the flash memory, the program/program-verify flowchart shown in figure 18.9 should be followed. perform ing programming operations according to this flowchart will enable data or programs to be written to the flash memory without subjecting the chip to voltage stress or sacrificing program data reliability. 1. programming must be done to an empty address. do not reprogram an address to which programming has already been performed. 2. programming should be carried out 128 bytes at a time. a 128-byte data transfer must be performed even if writing fewer than 128 bytes. in this case, h'ff data must be written to the extra addresses. 3. prepare the following data storage areas in ram: a 128-byte programming data area, a 128- byte reprogramming data area, and a 128-byte additional-programming data area. perform reprogramming data computati on and additional programming data computation according to figure 18.9. 4. consecutively transfer 128 bytes of data in byte units from the reprogramming data area or additional-programming data area to the flash memory. the program address and 128-byte data are latched in the flash memory. the lower 8 bits of the start address in the flash memory destination area must be h'00 or h'80. 5. the time during which the p bit is set to 1 is the programming time. figure 18.9 shows the allowable programming times. 6. the watchdog timer (wdt) is set to prevent overprogramming due to program runaway, etc. an overflow cycle of approximately 6.6 ms is allowed. 7. for a dummy write to a verify address, write 1-byte data h'ff to an address whose lower 2 bits are b'00. verify data can be read in longwords from the address to which a dummy write was performed. 8. the maximum number of repetitions of the program/program-verify sequence of the same bit is 1,000. section 18 rom rev. 7.00 sep. 11, 2009 page 471 of 566 rej09b0211-0700 start end of pro g rammin g set swe bit in flmcr1 start of pro g rammin g write pulse application subroutine wait (t sswe ) s apply write pulse end sub set psu bit in flmcr1 wdt enable disable wdt number of writes n 1 2 3 4 5 6 7 8 9 10 11 12 13 998 999 1000 note: 6. write pulse width write time (tsp) s 30 30 30 30 30 30 200 200 200 200 200 200 200 200 200 200 wait (t spsu ) s set p bit in flmcr1 wait (t sp ) s clear p bit in flmcr1 wait (t cp ) s clear psu bit in flmcr1 wait (t cpsu ) s n = 1 m = 0 no no no no yes yes yes wait (t spv ) s wait (t spvr ) s * 2 * 7 * 7 * 4 * 7 * 7 start of pro g rammin g end of pro g rammin g * 5 * 7 * 7 * 7 * 1 wait (t cpv ) s apply write pulse sub-routine-call set pv bit in flmcr1 h'ff dummy write to verify address read verify data write data = verify data? * 4 * 3 * 7 * 7 * 7 * 1 transfer repro g ram data to repro g ram data area repro g ram data computation * 4 transfer additional-pro g rammin g data to additional-pro g rammin g data area additional-pro g rammin g data computation clear pv bit in flmcr1 clear swe bit in flmcr1 m = 1 repro g ram see note *6 for pulse width m = 0 ? increment address pro g rammin g failure yes clear swe bit in flmcr1 wait (t cswe ) s no yes 6 n? no yes 6 n ? wait (t cswe ) s n (n)? n n + 1 ori g inal data (d) verify data (v) repro g ram data (x) comments pro g rammin g completed pro g rammin g incomplete; repro g ram still in erased state; no action note: * use a 10 s write pulse for additional pro g rammin g . write 128-byte data in ram repro g ram data area consecutively to flash memory ram pro g ram data stora g e area (128 bytes) repro g ram data stora g e area (128 bytes) additional-pro g rammin g data stora g e area (128 bytes) store 128-byte pro g ram data in pro g ram data area and repro g ram data area apply write pulse (additional pro g rammin g ) sub-routine-call 128-byte data verification completed? successively write 128-byte data from additional- pro g rammin g data area in ram to flash memory repro g ram data computation table repro g ram data (x') verify data (v) additional- pro g rammin g data (y) 0 1 1 1 0 1 0 1 0 0 1 1 comments additional pro g rammin g to be executed additional pro g rammin g not to be executed additional pro g rammin g not to be executed additional pro g rammin g not to be executed additional-pro g rammin g data computation table 1 0 1 1 0 1 0 1 0 0 1 1 perform pro g rammin g in the erased state. do not perform additional pro g rammin g on previously pro g rammed addresses. notes: 1. data transfer is performed by byte transfer. the lower 8 bits of the first address written to must be h'00 or h'80. a 128-byte data transfer must be performed even if writin g fewer than 128 bytes; in this case, h'ff data must be written to the extra addresses. 2. verify data is read in 16-bit (word) units. 3. repro g ram data is determined by the operation shown in the table below (comparison between the data stored in the pro g ram data area and the verify data). bits for which the repro g ram data is 0 are pro g rammed in the next repro g rammin g loop. therefore, even bits for which pro g rammin g has been completed will be subjected to pro g rammin g once a g ain if the result of the subsequent verify operation is ng. 4. a 128-byte area for storin g pro g ram data, a 128-byte area for storin g repro g ram data, and a 128-byte area for storin g additional data must be provided in ram. the contents of the repro g ram data area and additional data area are modified as pro g rammin g proceeds. 5. a write pulse of 30 s or 200 s is applied accordin g to the pro g ress of the pro g rammin g operation. see note 6 for details of the pulse widths. when writin g of additional-pro g rammin g data is executed, a 10 s write pulse should be applied. repro g ram data x' means repro g ram data when the write pulse is applied. 7. the wait times and value of n are shown in section 21.5, flash memory characteristics. * * * * * * figure 18.9 program/program-verify flowchart section 18 rom rev. 7.00 sep. 11, 2009 page 472 of 566 rej09b0211-0700 18.8.2 erase/erase-verify when erasing flash memory, the erase/erase-verify flowchart shown in figure 18.10 should be followed. 1. prewriting (setting erase block data to all 0s) is not necessary. 2. erasing is performed in block units. make only a single-bit specification in the erase block registers (ebr1 and ebr2). to erase multiple blocks, each block must be erased in turn. 3. the time during which the e bit is set to 1 is the flash memory erase time. 4. the watchdog timer (wdt) is set to prevent overerasing due to program runaway, etc. an overflow cycle of approximately 19.8 ms is allowed. 5. for a dummy write to a verify address, write 1-byte data h'ff to an address whose lower two bits are b'00. verify data can be read in longwords from the address to which a dummy write was performed. 6. if the read data is not erased successfully, se t erase mode again, and repeat the erase/erase- verify sequence as before. the maximum number of repetitions of the erase/erase-verify sequence is 100. 18.8.3 interrupt handling when programming/erasing flash memory all interrupts, including the nmi interrupt, are disabled while flash memory is being programmed or erased, or while the boot program is executing, for the following three reasons: 1. interrupt during programming/erasing may cause a violation of the programming or erasing algorithm, with the result that normal operation cannot be assured. 2. if interrupt exception handling starts before the vector address is written or during programming/erasing, a correct vector cannot be fetched and the cpu malfunctions. 3. if an interrupt occurs during boot program execution, normal boot mode sequence cannot be carried out. section 18 rom rev. 7.00 sep. 11, 2009 page 473 of 566 rej09b0211-0700 erase start set ebr1 and ebr2 enable wdt disable wdt read verify data increment address verify data = all 1s ? last address of block ? all erase block erased ? set block start address as verify address h'ff dummy write to verify address swe bit 1 n 1 esu bit 1 e bit 1 wait 1 s wait 100 s e bit 0 ev bit 1 wait 10 ms esu bit 0 wait 10 s wait 10 s wait 20 s ev bit 0 n n + 1 wait 4 s swe bit 0 wait 100 s ev bit 0 n 100 ? wait 4 s swe bit 0 wait 100 s erase failure end of erasing wait 2 s no no ye s ye s no no ye s ye s figure 18.10 erase/erase-verify flowchart section 18 rom rev. 7.00 sep. 11, 2009 page 474 of 566 rej09b0211-0700 18.9 program/erase protection there are three kinds of flash memory program/er ase protection; hardware protection, software protection, and error protection. 18.9.1 hardware protection hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset or standby mode. flash memory control register 1 (flmcr1), flash memory control register 2 (flmcr2), and erase block register 1 (ebr1) are initialized. in a reset via the res pin, the reset state is not entered unless the res pin is held low until oscillation stabilizes after powering on. in the case of a reset during operation, hold the res pin low for the res pulse width specified in the ac characteristics section. 18.9.2 software protection software protection can be implemented against programming/erasing of all flash memory blocks by clearing the swe bit in flmcr1. when software protection is in effect, setting the p1 or e1 bit in flmcr1 does not cause a transition to pr ogram mode or erase mode. by setting the erase block register 1 (ebr1), erase protection can be set for individual blocks. when ebr1 is set to h?00, erase protection is set for all blocks. 18.9.3 error protection in error protection, an error is detected when cpu runaway occurs during flash memory programming/erasing, or operati on is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. when the following errors are detected during programming/erasing of flash memory, the fler bit in flmcr2 is set to 1, and the error protection state is entered. ? when the flash memory of the relevant address area is read during programming/erasing (including vector read and instruction fetch) ? immediately after exception handling (excluding a reset) during programming/erasing ? when a sleep instruction is executed during programming/erasing the flmcr1, flmcr2, and ebr1 settings are retained, however program mode or erase mode is aborted at the point at which the error occu rred. program mode or erase mode cannot be re- entered by re-setting the p1 or e1 bit. however, pv1 and ev1 bit setting is enabled, and a transition can be made to verify mode. error protection can be cleared only by a power-on reset. section 18 rom rev. 7.00 sep. 11, 2009 page 475 of 566 rej09b0211-0700 18.10 programmer mode in programmer mode, a prom programmer can be used to perform programming/erasing via a socket adapter, just as for a discrete flash memory. use a prom programmer that supports the renesas 128-kbyte flash memory on-chip mcu device type (fztat128v5a). 18.11 power-down states for flash memory in user mode, the flash memory will operate in either of the following states: ? normal operating mode the flash memory can be read and written to. ? standby mode all flash memory circuits are halted. table 18.6 shows the correspondence between the operating modes of the h8s/2612 group and the flash memory. when the flash memory returns to its normal operating state from standby mode, a period to stabilize the power supply circuits that were stopped is needed. when the flash memory returns to its normal operating state, bits sts2 to sts0 in sbycr must be set to provide a wait time of at least 20 s, even when the external clock is being used. table 18.6 flash memory operating states lsi operating state flash memory operating state active mode normal operating mode standby mode standby mode section 18 rom rev. 7.00 sep. 11, 2009 page 476 of 566 rej09b0211-0700 18.12 note on switching from f-zta t version to mask rom version the mask rom version does not have the internal registers for flash memory control that are provided in the f-ztat version. table 18.7 lists the registers that are present in the f-ztat version but not in the mask rom version. if a register listed in table 18.7 is read in the mask rom version, an undefined value will be returned. therefore, if application software developed on the f-ztat version is switched to a mask rom version product, it must be modified to ensure that the registers in table 18.7 have no effect. table 18.7 registers present in f-ztat v ersion but absent in mask rom version register abbreviation address flash memory control register 1 flmcr1 h'ffa8 flash memory control register 2 flmcr2 h'ffa9 erase block register 1 ebr1 h'ffaa erase block register 2 ebr2 h'ffab ram emulation register ramer h'fedb flash memory power control register flpwcr h'ffac section 19 clock pulse generator rev. 7.00 sep. 11, 2009 page 477 of 566 rej09b0211-0700 section 19 clock pulse generator this lsi has an on-chip clock pulse generator that generates the system clock ( ), the bus master clock, and internal clocks. the clock pulse generator consists of an oscillator, pll circuit, clock selection circuit, medium-speed clock divider, and bus master clock selection circuit. a block diagram of the clock pulse generator is shown in figure 19.1. extal xtal sck2 to sck0 sckcr stc1, stc0 lpwrcr le g end: lpwrcr: low-power control re g ister sckcr: system clock control re g ister clock oscillator pll circuit ( 1, 2, 4) clock selection circuit system clock to pin internal clock to supportin g modules bus master cloc k to cpu and dtc medium- speed clock divider bus master clock selection circuit /2 to /32 figure 19.1 block diagram of clock pulse generator the frequency can be changed by means of the pll circuit. frequency changes are performed by software by settings in the low-power control register (lpwrcr) and system clock control register (sckcr). section 19 clock pulse generator rev. 7.00 sep. 11, 2009 page 478 of 566 rej09b0211-0700 19.1 register descriptions the on-chip clock pulse generator has the following registers. for details on register addresses, refer to appendix a, on-chip i/o register. ? system clock control register (sckcr) ? low-power control register (lpwrcr) 19.1.1 system clock control register (sckcr) sckcr performs clock output control, selection of ope ration when the pll circuit frequency multiplication factor is changed, and medium-speed mode control. bit bit name initial value r/w description 7 pstop 0 r/w clock output disable controls output. high-speed mode, medium-speed mode 0: output 1: fixed high sleep mode 0: output 1: fixed high software standby mode 0: fixed high 1: fixed high hardware standby mode 0: high impedance 1: high impedance 6 to 4 ? all 0 ? reserved these bits are always read as 0. section 19 clock pulse generator rev. 7.00 sep. 11, 2009 page 479 of 566 rej09b0211-0700 bit bit name initial value r/w description 3 stcs 0 r/w frequency multiplication factor switching mode select selects the operation when the pll circuit frequency multiplication factor is changed. 0: specified multiplication factor is valid after transition to software standby mode 1: specified multiplication factor is valid immediately after stc1 bit and stc0 bit are rewritten 2 1 0 sck2 sck1 sck0 0 0 0 r/w r/w r/w system clock select 0 to 2 these bits select the bus master clock. 000: high-speed mode 001: medium-speed clock is /2 010: medium-speed clock is /4 011: medium-speed clock is /8 100: medium-speed clock is /16 101: medium-speed clock is /32 11x: setting prohibited legend: x: don?t care 19.1.2 low-power control register (lpwrcr) bit bit name initial value r/w description 7 to 4 ? all 0 ? reserved only 0 should be written to these bits. 3, 2 ? all 0 r/w these bits can be read and write, but should not be set to 1. 1 0 stc1 stc0 0 0 r/w r/w frequency multiplication factor the stc bits specify the frequency multiplication factor of the pll circuit. 00: 1 01: 2 10: 4 11: setting prohibited section 19 clock pulse generator rev. 7.00 sep. 11, 2009 page 480 of 566 rej09b0211-0700 19.2 oscillator clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. in either case, the input clock should not exceed 20 mhz. 19.2.1 connecting a crystal resonator circuit configuration: a crystal resonator can be connected as shown in the example in figure 19.2. select the damping resistance r d according to table 19.1. an at-cut parallel-resonance crystal should be used. extal xtal r d c l2 c l1 c l1 = c l2 = 10 to 22 pf figure 19.2 connection of crystal resonator (example) table 19.1 damping resistance value frequency (mhz) 4 8 10 12 16 20 r d ( ) 500 200 0 0 0 0 figure 19.3 shows the equivalent circuit of the crystal resonator. use a crystal resonator that has the characteristics shown in table 19.2. xtal c l at-cut parallel-resonance type extal c 0 lr s figure 19.3 crystal resonator equivalent circuit section 19 clock pulse generator rev. 7.00 sep. 11, 2009 page 481 of 566 rej09b0211-0700 table 19.2 crystal resonator characteristics frequency (mhz) 4 8 10 12 16 20 r s max ( ) 120 80 70 60 50 40 c 0 max (pf) 7 7 7 7 7 7 19.2.2 external clock input circuit configuration: an external clock signal can be input as shown in the examples in figure 19.4. if the xtal pin is left open, ensure th at stray capacitance does not exceed 10 pf. when complementary clock is input to the xtal pin, the external clock input should be fixed high in standby mode. extal xtal extal xtal external clock input open external clock input (a) xtal pin left open (b) complementary clock input at xtal pin figure 19.4 external clock input (examples) section 19 clock pulse generator rev. 7.00 sep. 11, 2009 page 482 of 566 rej09b0211-0700 table 19.3 shows the input conditions for the external clock. table 19.3 external clock input conditions v cc = 5.0 v 10% item symbol min max unit test conditions external clock input low pulse width t exl 15 ? ns external clock input high pulse width t exh 15 ? ns external clock rise time t exr ? 5 ns external clock fall time t exf ? 5 ns figure 19.5 0.4 0.6 t cyc 5 mhz clock low pulse width level t cl 80 ? ns < 5 mhz 0.4 0.6 t cyc 5 mhz clock high pulse width level t ch 80 ? ns < 5 mhz figure 21.2 t exh t exl t exr t exf v cc 0.5 extal figure 19.5 external clock input timing section 19 clock pulse generator rev. 7.00 sep. 11, 2009 page 483 of 566 rej09b0211-0700 19.3 pll circuit the pll circuit multiplies the frequency of the clock from the oscillator by a factor of 1, 2, or 4. the multiplication factor is set by the stc0 bit and the stc1 bit in lpwrcr. the phase of the rising edge of the internal clock is controlled so as to match that at the extal pin. when the multiplication factor of the pll circuit is changed, the operation varies according to the setting of the stcs bit in sckcr. when stcs = 0, the setting becomes valid afte r a transition to software standby mode. the transition time count is performed in accordance with the setting of bits sts0 to sts2 in sbycr. for details on sbycr, refer to section 20.1.1, standby control register (sbycr). 1. the initial pll circuit multiplication factor is 1. 2. sts0 to sts2 are set to gi ve the specified transition time. 3. the target value is set in stc0 and stc1, and a transition is made to software standby mode. 4. the clock pulse generator stops and the value set in stc0 and stc1 becomes valid. 5. software standby mode is cleared, and a tr ansition time is secured in accordance with the setting in sts0 to sts2. 6. after the set transition time has elapsed, this lsi resumes operation using the target multiplication factor. if a pc break is set for the sleep instruction, software standby mode is entered and break exception handling is executed after the oscillation stabilization time. in this case, the instruction following the sleep instruction is executed after execution of the rte instruction. when stcs = 1, this lsi operates on the changed multiplication factor immediately after bits stc0 and stc1 are rewritten. 19.4 medium-speed clock divider the medium-speed clock divider divides the system clock to generate /2, /4, /8, /16, and /32. 19.5 bus master clock selection circuit the bus master clock selection circuit selects the clock supplied to the bus master by setting the bits sck 2 to sck 0 in sckcr. the bus master clock can be selected from high-speed mode, or medium-speed clocks ( /2, /4, /8, /16, /32). section 19 clock pulse generator rev. 7.00 sep. 11, 2009 page 484 of 566 rej09b0211-0700 19.6 usage notes 19.6.1 note on crystal resonator as various characteristics related to the crystal resonator are closely linked to the user's board design, thorough evaluation is necessary on the user's part, using the resonator connection examples shown in this section as a guide. as the resonator circuit ratings will depend on the floating capacitance of the resonator and the mounting circuit, the ratings should be determined in consultation with the resonator manufacturer. the design must ensure that a voltage exceeding the maximum rating is not applied to the oscillator pin. 19.6.2 note on board design when designing the board, place the crystal resonator and its load capacitors as close as possible to the xtal and extal pins. other signal lines should be routed away from the oscillator circuit, as shown in figure 19.6. this is to prevent induction from interfering with correct oscillation. c l2 avoid si g nal a si g nal b c l1 this lsi xtal extal figure 19.6 note on board design of oscillator circuit figure 19.7 shows external circuitry recommended to be provided around the pll circuit. place oscillation stabilization capacitor c1 and resistor r1 close to the pllcap pin, and ensure that no other signal lines cross this line. separate pllvc l and pllvss from the other vcc and vss lines at the board power supply source, and be sure to insert bypass capacitors cb close to the pins. section 19 clock pulse generator rev. 7.00 sep. 11, 2009 page 485 of 566 rej09b0211-0700 pllcap pllv cl pllv ss v cc v cl v ss (values are preliminary recommended values) note: * cb are laminated ceramic. r1 : 3 k c1 : 470 pf cb : 0.1 f cb : 0.1 f * cb : 0.1 f figure 19.7 external circuit ry recommended for pll circuit section 19 clock pulse generator rev. 7.00 sep. 11, 2009 page 486 of 566 rej09b0211-0700 section 20 power-down modes rev. 7.00 sep. 11, 2009 page 487 of 566 rej09b0211-0700 section 20 power-down modes in addition to the normal program execution state, this lsi has five power-down modes in which operation of the cpu and oscillator is halted and power dissipation is reduced. low-power operation can be achieved by individually controlling the cpu, on-chip supporting modules, and so on. this lsi's operating modes are as follows: (1) high-speed mode (2) medium-speed mode (3) sleep mode (4) module stop mode (5) software standby mode (6) hardware standby mode (2) to (6) are power-down modes. sleep mode is a cpu state, medium-speed mode is a cpu and bus master state, and module stop mode is an internal peripheral function (including bus masters other than the cpu) state. some of these states can be combined. after a reset, the lsi is in high-speed mode. figure 20.1 show a mode transition. table 20.1 shows the conditions of transition between modes when executing the sleep instruction and the state after tran sition back from low power mode due to an interrupt. table 20.2 shows the in ternal state of the lsi in each mode. note: mmt, ppg, pc break controller, and dtc are not implemented in the h8s/2614 and h8s/2616. table 20.1 low power dissipation mode transition conditions status of control bit at transition pre-transition state ssby state after transition invoked by sleep command state after transition back from low power mode invoked by interrupt 0 sleep high-speed/medium-speed high-speed/ medium-speed 1 software standby high-speed/medium-speed section 20 power-down modes rev. 7.00 sep. 11, 2009 page 488 of 566 rej09b0211-0700 pro g ram-halted state pro g ram execution state sck2 to sck0 = 0 sck2 to sck0 0 sleep command any interrupt sleep command external interrupt * stby pin = hi g h res pin = low stby pin = low ssby = 0 ssby = 1 res pin = hi g h : transition after exception processin g : low power dissipation mode reset state hi g h-speed mode (main clock) hardware standby mode software standby mode sleep mode (main clock) medium-speed mode (main clock) notes: when a transition is made between modes by means of an interrupt, the transition cannot be made on interrupt source g eneration alone. ensure that interrupt handlin g is performed after acceptin g the interrupt request. from any state except hardware standby mode, a transition to the reset state occurs when res is driven low. from any state, a transition to hardware standby mode occurs when stby is driven low. * nmi and irq0 to irq5 figure 20.1 mode transition diagram section 20 power-down modes rev. 7.00 sep. 11, 2009 page 489 of 566 rej09b0211-0700 table 20.2 lsi internal states in each mode function high-speed medium- speed sleep module stop software standby hardware standby system clock pulse generator functioning functioning functioning functioning halted halted cpu instructions registers functioning medium- speed operation halted (retained) high/ medium- speed operation halted (retained) halted (undefined) nmi external interrupts irq0 to irq5 functioning functioning functioni ng functioning functioning halted pbc dtc functioning medium- speed operation functioning halted (retained) halted (retained) halted (reset) i/o functioning functioning functioning functioning retained high impedance tpu mmt/poe ppg functioning functioning functioning halted (retained) halted (retained) halted (reset) wdt functioning functioning functioning functioning halted (retained) halted (reset) sci hcan peripheral functions a/d functioning functioning functioning halted (reset) halted (reset) halted (reset) ram functioning medium- speed operation functioning (dtc) functioning retained retained note: ?halted (retained)? means that internal register values are retained. the internal state is ?operation suspended?. ?halted (reset)? means that internal register values and internal states are initialized. in module stop mode, only modules for which a stop setting has been made are halted (reset or retained). section 20 power-down modes rev. 7.00 sep. 11, 2009 page 490 of 566 rej09b0211-0700 20.1 register descriptions registers related to the power down mode are shown below. for details on the system clock control register (sckcr), refer to section 19.1.1, system clock control register (sckcr). for details on register addresses and register states during each process, refer to appendix a, on-chip i/o register. ? system clock control register (sckcr) ? standby control register (sbycr) ? module stop control register a (mstpcra) ? module stop control register b (mstpcrb) ? module stop control register c (mstpcrc) 20.1.1 standby control register (sbycr) sbycr is an 8-bit readable/writable register that performs software standby mode control. bit bit name initial value r/w description 7 ssby 0 r/w software standby this bit specifies the transition mode after executing the sleep instruction 0: shifts to sleep mode when the sleep instruction is executed 1: shifts to software standby mode when the sleep instruction is executed this bit does not change when clearing the software standby mode by using external interrupts and shifting to normal operation. this bit should be written with 0 when clearing. section 20 power-down modes rev. 7.00 sep. 11, 2009 page 491 of 566 rej09b0211-0700 bit bit name initial value r/w description 6 5 4 sts2 sts1 sts0 0 0 0 r/w r/w r/w standby timer select 0 to 2 these bits select the mcu wait time for clock stabilization when software standby mode is cancelled by an external interrupt. with a crystal oscillator (table 20.3), select a wait time of 8ms (oscillation stabilization time) or more, depending on the operating frequency. with an external clock, select a wait time of 2 ms or more. 000: standby time = 8192 states 001: standby time = 16384 states 010: standby time = 32768 states 011: standby time = 65536 states 100: standby time = 131072 states 101: standby time = 262144 states 110: reserved 111: standby time = 16 states 3 ? 1 r/w reserved only 1 should be written to this bit. 2 to 0 ? all 0 ? reserved these bits are always read as 0 and cannot be modified. section 20 power-down modes rev. 7.00 sep. 11, 2009 page 492 of 566 rej09b0211-0700 20.1.2 module stop control registers a to c (mstpcra to mstpcrc) mstpcr is comprised of three 8-bit readable/writable registers, and performs module stop mode control. setting a bit to 1 causes the corresponding module to enter module stop mode. clearing the bit to 0 clears the module stop mode. mstpcra bit bit name initial value r/w module 7 mstpa7 * 0 r/w 6 mstpa6 0 r/w data transfer controller (dtc) 5 mstpa5 1 r/w 16-bit timer pulse unit (tpu) 4 mstpa4 * 1 r/w 3 mstpa3 1 r/w programmable pulse generator (ppg) 2 mstpa2 * 1 r/w 1 mstpa1 1 r/w a/d converter 0 mstpa0 * 1 r/w mstpcrb bit bit name initial value r/w module 7 mstpb7 1 r/w serial communication interface 0 (sci0) 6 mstpb6 1 r/w serial communication interface 1 (sci1) 5 mstpb5 1 r/w serial communication interface 2 (sci2) 4 mstpb4 * 1 r/w 3 mstpb3 * 1 r/w 2 mstpb2 * 1 r/w 1 mstpb1 * 1 r/w 0 mstpb0 * 1 r/w section 20 power-down modes rev. 7.00 sep. 11, 2009 page 493 of 566 rej09b0211-0700 mstpcrc bit bit name initial value r/w module 7 mstpc7 * 1 r/w 6 mstpc6 * 1 r/w 5 mstpc5 * 1 r/w 4 mstpc4 1 r/w pc break controller (pbc) 3 mstpc3 1 r/w controller area network (hcan) 2 mstpc2 1 r/w motor management timer (mmt) 1 mstpc1 * 1 r/w 0 mstpc0 * 1 r/w note: * mstpa7 is a readable/writable bit with an initial value of 0 and should always be written with 0. mstpa4, mstpa2, mstpa0, mstpb4 to mstpb0, mstpc7 to mstpc5, mstpc1, and mstpc0 are readable/writable bits with an initial value of 1 and should always be written with 1. 20.2 medium-speed mode when the sck0 to sck2 bits in sckcr are set to 1, the operating mode changes to medium- speed mode as soon as the current bus cycle ends. in medium-speed mode, the cpu operates on the operating clock ( /2, /4, /8, /16, or /32) specified by the sck0 to sck2 bits. bus masters (dtc) other than the cpu also operate in medium-speed mode. on-chip supporting modules other than bus masters always operate on the high-speed clock ( ). in medium-speed mode, a bus access is executed in the specified number of states with respect to the bus master operating clock. for example, if /4 is selected as the operating clock, on-chip memory is accessed in 4 states, and in ternal i/o registers in 8 states. medium-speed mode is cleared by clearing all of bits sck0 to sck2 to 0. a transition is made to high-speed mode and medium-speed mode is clear ed at the end of the current bus cycle. if a sleep instruction is executed when the ssby b it in sbycr is cleared to 0, a transition is made to sleep mode. when sleep mode is cleared by an interrupt, medium-speed mode is restored. when the sleep instruction is ex ecuted with the ssby bit = 1, ope ration shifts to the software standby mode. when software standby mode is cleared by an external interrupt, medium-speed mode is restored. section 20 power-down modes rev. 7.00 sep. 11, 2009 page 494 of 566 rej09b0211-0700 when the res pin is set low and medium-speed mode is cancelled, operation shifts to the reset state. the same applies in the case of a reset caused by overflow of the watchdog timer. when the stby pin is driven low, a transition is made to hardware standby mode. figure 20.2 shows the timing for transition to and clearance of medium-speed mode. sckcr sckcr , supportin g module clock bus master clock internal address bus internal write si g nal medium-speed mode figure 20.2 medium-speed mode transition and clearance timing section 20 power-down modes rev. 7.00 sep. 11, 2009 page 495 of 566 rej09b0211-0700 20.3 sleep mode 20.3.1 transition to sleep mode if sleep instruction is executed when the sbycr ssby bit = 0, the cpu enters the sleep mode. in sleep mode, cpu operation stops, however the c ontents of the cpu's internal registers are retained. other supporting modules do not stop. 20.3.2 clearing sleep mode sleep mode is cleared by any interrupt, or signals at the res , or stby pins. ? exiting sleep mode by interrupts: when an interrupt occurs, sleep mode is exited and interrupt exception processing starts. sleep mode is not exited if the interrupt is disabled, or if interrupts other than nmi are masked by the cpu. ? exiting sleep mode by res pin: setting the res pin low selects the reset state. after the stipulated reset input duration, driving the res pin high restart the cpu performing reset exception processing. ? exiting sleep mode by stby pin: when the stby pin level is driven low, a transition is made to hardware standby mode. section 20 power-down modes rev. 7.00 sep. 11, 2009 page 496 of 566 rej09b0211-0700 20.4 software standby mode 20.4.1 transition to software standby mode a transition is made to software standby mode if the sleep instruction is executed when the sbycr ssby bit is set to 1. in this mode, th e cpu, on-chip supporting modules, and oscillator, all stop. however, the contents of the cpu's internal registers, on-chip ram data, and the states of on-chip supporting modules other than the sci, a/d converter, hcan, and the states of i/o ports, are retained. in this mode, the oscillator stops, and therefore power dissipation is significantly reduced. 20.4.2 clearing software standby mode software standby mode is cleared by an external interrupt (nmi pin, or pins irq0 to irq5 ), or by means of the res pin or stby pin. ? clearing with an interrupt: when an nmi or irq0 to irq5 interrupt reque st signal is input, clock oscillation starts, and after the time set in bits sts0 to sts2 in sbycr has elapsed, stable clocks are supplied to the entire chip, software standby mode is cleared, and interrupt exception handling is started. when clearing software standby mode with an irq0 to irq5 interrupt, set the corresponding enable bit to 1 and ensure that no interrupt with a higher priority than interrupts irq0 to irq5 is generated. software standby mode cannot be cleared if the interrupt has been masked on the cpu side or has been designated as a dtc activation source. ? clearing with the res pin: when the res pin is driven low, clock oscillation is started. at the same time as clock oscillation starts, clocks are supplied to the entire chip . note that the res pin must be held low until clock oscillation stabilizes. when the res pin goes high, the cpu begins reset exception handling. ? clearing with the stby pin: when the stby pin is driven low, a transition is made to hardware standby mode. section 20 power-down modes rev. 7.00 sep. 11, 2009 page 497 of 566 rej09b0211-0700 20.4.3 setting oscillation stabilization time after clearing software standby mode bits sts2 to sts0 in sbycr should be set as described below. ? using a crystal oscillator: set bits sts0 to sts2 so that the standby time is at l east 8 ms (the oscillation stabilization time). table 20.3 shows the standby times for different operating frequencies and settings of bits sts0 to sts2. ? using an external clock: the pll circuit requires a time for stabilization. set bits sts0 to sts2 so that the standby time is at least 2 ms. table 20.3 oscillation stabilization time settings sts2 sts1 sts0 standby time 20 mhz 16 mhz 12 mhz 10 mhz 8 mhz 6 mhz 4 mhz unit 0 8192 states 0.41 0.51 0.68 0.8 1.0 1.3 2.0 0 1 16384 states 0.82 1.0 1.3 1.6 2.0 2.7 4.1 0 32768 states 1.6 2.0 2.7 3.3 4.1 5.5 8.2 0 1 1 65536 states 3.3 4.1 5.5 6.6 8.2 10.9 16.4 0 131072 states 6.6 8.2 10.9 13.1 16.4 21.8 32.8 0 1 262144 states 13.1 16.4 21.8 26.2 32.8 43.6 65.6 ms 1 1 0 reserved ? ? ? ? ? ? ? ? 1 16 states * 0.8 1.0 1.3 1.6 2.0 1.7 4.0 s : recommended time setting note: * setting prohibited section 20 power-down modes rev. 7.00 sep. 11, 2009 page 498 of 566 rej09b0211-0700 20.4.4 software standby mode application example figure 20.3 shows an example in which a transition is made to software standby mode at a falling edge on the nmi pin, and software standby mode is cleared at a rising edge on the nmi pin. in this example, an nmi interrupt is accepted with the nmieg bit in syscr cleared to 0 (falling edge specification), then the nmieg bit is set to 1 (rising edge specification), the ssby bit is set to 1, and a sleep instruction is executed, causing a transiti on to software standby mode. software standby mode is then cleared at the rising edge on the nmi pin. oscillator nmi nmieg ssby nmi exception handlin g nmieg = 1 ssby = 1 oscillation stabilization time t osc2 software standby mode (power-down mode) nmi exception handlin g sleep instruction figure 20.3 software standby mode application example section 20 power-down modes rev. 7.00 sep. 11, 2009 page 499 of 566 rej09b0211-0700 20.5 hardware standby mode 20.5.1 transition to hardware standby mode when the stby pin is driven low, a transition is made to hardware standby mode from any mode. in hardware standby mode, all functions enter th e reset state and stop operation, resulting in a significant reduction in power dissipation. as long as the prescribed voltage is supplied, on-chip ram data is retained. i/o ports are set to the high-impedance state. in order to retain on-chip ram data, the rame bit in syscr should be cleared to 0 before driving the stby pin low. do not change the state of the mode pins (md0 to md2) while this lsi is in hardware standby mode. 20.5.2 clearing hardware standby mode hardware standby mode is cleared by means of the stby pin and the res pin. when the stby pin is driven high while the res pin is low, the reset state is set and clock oscillation is started. ensure that the res pin is held low until the clock oscillator stabilizes (at least 8 ms?the oscillation stabilization time?when using a crystal oscillator). when the res pin is subsequently driven high, a transition is made to the program execution state via the reset exception handling state. 20.5.3 hardware standby mode timings timing of transition to hardware standby mode 1. to retain ram contents with the rame bit set to 1 in syscr drive the res signal low at least 10 states before the stby signal goes low, as shown in figure 20.4. after stby has gone low, res has to wait for at least 0 ns before becoming high. stby res t 2 0 ns t 1 10 t cyc figure 20.4 timing of transition to hardware standby mode section 20 power-down modes rev. 7.00 sep. 11, 2009 page 500 of 566 rej09b0211-0700 2. to retain ram contents with the rame bit cleared to 0 in syscr, or when ram contents do not need to be retained res does not have to be driven low as in the above case. timing of recovery from hardware standby mode drive the res signal low approximately 100 ns or more before stby goes high to execute a power-on reset. t osc1 t 100 ns stby res figure 20.5 timing of recovery from hardware standby mode 20.6 module stop mode module stop mode can be set for individual on-chip supporting modules. when the corresponding mstp bit in mstpcr is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. the cpu continues operating independently. when the corresponding mstp bit is cleared to 0, module stop mode is cleared and the module starts operating at the end of the bus cycle. in module stop mode, the internal states of modules other than the sci * , hcan, and a/d converter are retained. after reset clearance, all modules other than dtc are in module stop mode. when an on-chip supporting module is in module stop mode, read/write access to its registers is disabled. note: * the internal states of some sci registers are retained. section 20 power-down modes rev. 7.00 sep. 11, 2009 page 501 of 566 rej09b0211-0700 20.7 clock output disabling function the output of the clock can be controlled by means of the pstop bit in sckcr, and ddr for the corresponding port. when the pstop bit is set to 1, the clock stops at the end of the bus cycle, and output goes high. clock output is enabled when the pstop bit is clear ed to 0. when ddr for the corresponding port is cleared to 0, clock output is disabled and input port mode is set. table 20.4 shows the state of the pin in each processing state. table 20.4 pin state in each processing state register settings ddr pstop normal mode sleep mode software standby mode hardware standby mode 0 x high impedance high impedance high impedance high impedance 1 0 output output fixed high high impedance 1 1 fixed high fixed high fixed high high impedance legend: x: don?t care section 20 power-down modes rev. 7.00 sep. 11, 2009 page 502 of 566 rej09b0211-0700 20.8 usage notes 20.8.1 i/o port status in software standby mode, i/o port states are retained. therefore, there is no reduction in current dissipation for the output current when a high-level signal is output. 20.8.2 current dissipation during oscillation stabilization wait period current dissipation increases during the oscillation stabilization wait period. 20.8.3 dtc module stop depending on the operating status of the dtc, mstpa6 bit may not be set to 1. setting of the dtc module stop mode should be carried out only when the respective module is not activated. for details, refer to section 8, data transfer controller (dtc). 20.8.4 on-chip supporting module interrupt relevant interrupt operations cannot be perfor med in module stop mode. consequently, if module stop mode is entered when an interrupt has been requested, it will not be possible to clear the cpu interrupt source or the dtc activation source. interrupts should therefore be disabled before entering module stop mode. 20.8.5 writing to mstpcr mstpcr should onl y be written to by the cpu. section 21 electrical characteristics rev. 7.00 sep. 11, 2009 page 503 of 566 rej09b0211-0700 section 21 electrical characteristics 21.1 absolute maximum ratings table 21.1 lists the absolute maximum ratings. table 21.1 absolute maximum ratings item symbol value unit power supply voltage v cc ?0.3 to +7.0 v input voltage (xtal, extal) v in ?0.3 to v cc + 0.3 v input voltage (ports 4 and 9) v in ?0.3 to av cc + 0.3 v input voltage (except xtal, extal, ports 4 and 9) v in ?0.3 to v cc + 0.3 v analog power supply voltage av cc ?0.3 to +7.0 v analog input voltage v an ?0.3 to av cc + 0.3 v operating temperature t opr regular specifications: ?20 to +75 c wide-range specifications: ?40 to +85 c storage temperature t stg ?55 to +125 c caution: permanent damage to the chip may result if absolute maximum rating are exceeded. section 21 electrical characteristics rev. 7.00 sep. 11, 2009 page 504 of 566 rej09b0211-0700 21.2 dc characteristics table 21.2 lists the dc characteristics. table 21.3 lists the permissible output currents. table 21.2 dc characteristics conditions: v cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ss = av ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) * 1 item symbol min. typ. max. unit test conditions v t ? v cc 0.2 ? ? v v t + ? ? v cc 0.7 v irq0 to irq5 v t + ? v t ? v cc 0.05 ? ? v v t ? v cc 0.2 ? ? v v t + ? ? v cc 0.7 v schmitt trigger input voltage tpu input capture input tpu external clock input v t + ? v t ? v cc 0.05 ? ? v input high voltage res , stby , nmi, md2 to md0, fwe v ih v cc 0.9 ? v cc + 0.3 v extal v cc 0.7 ? v cc + 0.3 v ports 1, a to d, f, hrxd v cc 0.7 ? v cc + 0.3 v port 4 and 9 av cc 0.7 ? av cc + 0.3 v input low voltage res , stby , nmi, md2 to md0, fwe v il ?0.3 ? v cc 0.1 v extal ?0.3 ? v cc 0.2 v ports 1, a to d, f, hrxd ?0.3 ? v cc 0.2 v ports 4 and 9 ?0.3 ? av cc 0.2 v all output pins v oh v cc ? 0.5 ? ? v i oh = ?200 a output high voltage v cc ? 1.0 ? ? v i oh = ?1 ma output low voltage all output pins v ol ? ? 0.4 v i ol = 1.6 ma section 21 electrical characteristics rev. 7.00 sep. 11, 2009 page 505 of 566 rej09b0211-0700 item symbol min. typ. max. unit test conditions res | i in | ? ? 1.0 a input leakage current stby , nmi, md2 to md0, fwe, hrxd ? ? 1.0 a v in = 0.5 v to v cc ? 0.5 v ports 4 and 9 ? ? 1.0 a three-state leakage current (off status) ports 1, a to d, f, hrxd ? i tsi ? ? ? 1.0 a v in = 0.5 v to v cc ? 0.5 v mos input pull-up current ports a to d ?i p 30 ? 300 a v in = 0 v res c in ? ? 30 pf v in = 0 v input capacitance nmi ? ? 30 pf f = 1 mhz all input pins except res and nmi ? ? 15 pf t a = 25c normal operation i cc * 3 ? 65 v cc = 5.0 v 75 v cc = 5.5 v ma f = 20 mhz current dissipation * 2 (h8s/2612, h8s/2611) sleep mode ? 50 v cc = 5.0 v 60 v cc = 5.5 v ma all modules stopped ? 40 ? ma medium- speed mode ( /32) ? 45 ? ma f = 20 mhz, v cc = 5.0 v (reference values) ? 2.0 5.0 a t a 50c standby mode ? ? 20 a 50c < t a section 21 electrical characteristics rev. 7.00 sep. 11, 2009 page 506 of 566 rej09b0211-0700 item symbol min. typ. max. unit test conditions normal operation i cc * 4 ? 65 v cc = 5.0 v 75 v cc = 5.5 v ma f = 20 mhz current dissipation * 2 (h8s/2614, h8s/2616) sleep mode ? 50 v cc = 5.0 v 60 v cc = 5.5 v ma all modules stopped ? 40 ? ma medium- speed mode ( /32) ? 45 ? ma f = 20 mhz, v cc = 5.0 v (reference values) ? 2.0 5.0 a t a 50c standby mode ? ? 20 a 50c < t a during a/d conversion al cc ? 2.5 4.0 ma av cc = 5.0 v analog power supply current idle ? ? 5.0 a ram standby voltage v ram 2.0 ? ? v notes: 1. if the a/d converter is not used, do not leave the av cc , and av ss pins open. apply a voltage between 4.5 v and 5.5 v to the av cc pin by connecting them to v cc , for instance. 2. current dissipation values are for v ih = v cc (extal), av cc (ports 4 and 9), or v cc (other), and v il = 0 v, with all output pins unloaded and the on-chip mos pull-up transistors in the off state. 3. i cc depends on v cc and f as follows: i cc (max.) = 27 + (0.435 v cc f) (normal operation) i cc (max.) = 27 + (0.3 v cc f) (sleep mode) 4. i cc depends on v cc and f as follows: i cc (max.) = 5 + (0.45 v cc f) (normal operation) i cc (max.) = 5 + (0.35 v cc f) (sleep mode) 5. available only in h8s/2616 and h8s/2614. section 21 electrical characteristics rev. 7.00 sep. 11, 2009 page 507 of 566 rej09b0211-0700 table 21.3 permissible output currents conditions: v cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ss = av ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) * item symbol min. typ. max. unit permissible output low current (per pin) all output pins i ol ? ? 10 ma permissible output low current (total) total of all output pins i ol ? ? 100 ma permissible output high current (per pin) all output pins ?i oh ? ? 2.0 ma permissible output high current (total) total of all output pins ?i oh ? ? 30 ma note: * to protect chip reliability, do not exceed the output current values in table 21.3. 21.3 ac characteristics figure 21.1 show, the test conditions for the ac characteristics. 5 v r l r h c lsi output pin c = 30 pf r l = 2.4 k r h = 12 input/output timin g measurement levels ? low level: 0.8 v ? hi g h level: 2.0 v figure 21.1 output load circuit section 21 electrical characteristics rev. 7.00 sep. 11, 2009 page 508 of 566 rej09b0211-0700 21.3.1 clock timing table 21.4 lists the clock timing table 21.4 clock timing conditions : v cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ss = av ss = 0 v, = 4 mhz to 20 mhz, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide- range specifications) item symbol min. max. unit test conditions clock cycle time t cyc 50 250 ns figure 21.2 clock high pulse width t ch 15 ? ns clock low pulse width t cl 15 ? ns clock rise time t cr ? 10 ns clock fall time t cf ? 10 ns oscillation stabilization time at reset (crystal) t osc1 20 ? ms figure 21.3 oscillation stabilization time in software standby (crystal) t osc2 8 ? ms figure 20.3 external clock output stabilization delay time t dext 2 ? ms figure 21.3 t cr t cl t cf t ch t cyc figure 21.2 system clock timing section 21 electrical characteristics rev. 7.00 sep. 11, 2009 page 509 of 566 rej09b0211-0700 t osc1 t osc1 extal v cc stby res t dext t dext figure 21.3 oscillation stabilization timing 21.3.2 control signal timing table 21.5 lists the control signal timing. table 21.5 control signal timing conditions: v cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ss = av ss = 0 v, = 4 mhz to 20 mhz, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide- range specifications) item symbol min. max. unit test conditions res setup time t ress 200 ? ns figure 21.4 res pulse width t resw 20 ? t cyc nmi setup time t nmis 150 ? ns figure 21.5 nmi hold time t nmih 10 ? ns nmi pulse width (exiting software standby mode) t nmiw 200 ? ns irq setup time t irqs 150 ? ns irq hold time t irqh 10 ? ns irq pulse width (exiting software standby mode) t irqw 200 ? ns section 21 electrical characteristics rev. 7.00 sep. 11, 2009 page 510 of 566 rej09b0211-0700 t resw t ress t ress res figure 21.4 reset input timing t irqs irq ed g e input t irqh t nmis t nmih t irqs irq level input nmi note: i = 0 to 2 irqi t nmiw t irqw figure 21.5 interrupt input timing section 21 electrical characteristics rev. 7.00 sep. 11, 2009 page 511 of 566 rej09b0211-0700 21.3.3 timing of on-chip supporting modules table 21.6 lists the timing of on-chip supporting modules. table 21.6 timing of on-chip supporting modules conditions: v cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ss = av ss = 0, = 4 mhz to 20 mhz, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) item symbol min. max. unit test conditions i/o port output data delay timet pwd ? 50 ns figure 21.6 input data setup time t prs 30 ? input data hold time t prh 30 ? tpu timer output delay time t tocd ? 50 ns figure 21.7 timer input setup time t tics 30 ? timer clock input setup time t tcks 30 ? ns figure 21.8 single edge t tckwh 1.5 ? t cyc timer clock pulse width both edges t tckwl 2.5 ? sci asynchro- nous t scyc 4 ? t cyc figure 21.9 input clock cycle synchro- nous 6 ? input clock pulse widtht sckw 0.4 0.6 t scyc input clock rise time t sckr ? 1.5 t cyc input clock fall time t sckf ? 1.5 transmit data delay time t txd ? 50 ns figure 21.10 receive data setup time (synchronous) t rxs 50 ? receive data hold time (synchronous) t rxh 50 ? section 21 electrical characteristics rev. 7.00 sep. 11, 2009 page 512 of 566 rej09b0211-0700 item symbol min. max. unit test conditions a/d converter trigger input setup time t trgs 30 ? ns figure 21.11 hcan * 1 transmit data delay time t htxd ? 100 ns figure 21.12 transmit data setup time t hrxs 100 ? transmit data hold time t hrxh 100 ? ppg * 2 pulse output delay time t pod ? 50 ns figure 21.13 mmt * 2 mmt output delay time t mtod ? 50 ns figure 21.14 pci input setup time t pcis 35 ? pci input pulse width t pciw 1.5 ? t cyc poe input setup time t poes 35 ? ns figure 21.15 poe input pulse width t poew 1.5 ? t cyc notes: 1. the hcan input signal is asynchronous. however, its state is judged to have changed at the rising-edge (two clock cycles) of the ck clock signal shown in figure 21.12. the hcan output signal is also asynchronous. its state changes based on the rising-edge (two clock cycles) of the ck clock signal shown in figure 21.12. 2. ppg and mmt are not supported in h8s/2614 and h8s/2616. ports 1, 4, 9 a to d, f (read) t prs t 1 t 2 t pwd t prh ports 1, a to d, f (write) figure 21.6 i/o port input/output timing section 21 electrical characteristics rev. 7.00 sep. 11, 2009 page 513 of 566 rej09b0211-0700 t tics t tocd output compare output * input capture input * note: * tioca0 to tioca5, tiocb0 to tiocb5, tiocc0, tiocc3, tiocd0, tiocd3 figure 21.7 tpu input/output timing t tcks t tcks tclka to tclkd t tckwh t tckwl figure 21.8 tpu clock input timing t scyc t sckr t sckw sck0 to sck2 t sckf figure 21.9 sck clock input timing section 21 electrical characteristics rev. 7.00 sep. 11, 2009 page 514 of 566 rej09b0211-0700 sck0 to sck2 txd0 to txd2 (transmit data) rxd0 to rxd2 (receive data) t txd t rxh t rxs figure 21.10 sci input/output timing (clock synchronous mode) t trgs adtrg figure 21.11 a/d converter external trigger input timing v ol v ol htxd (transmit data) hrxd (receive data) t htxd t hrxs t hrxh figure 21.12 hcan input/output timing po15 to 8 t pod figure 21.13 ppg output timing section 21 electrical characteristics rev. 7.00 sep. 11, 2009 page 515 of 566 rej09b0211-0700 mmt output pci input t mtod t pcis t pciw figure 21.14 mmt input/output timing poe input t poes t poew figure 21.15 poe input/output timing section 21 electrical characteristics rev. 7.00 sep. 11, 2009 page 516 of 566 rej09b0211-0700 21.4 a/d conversion characteristics table 21.7 lists the a/d conversion characteristics. table 21.7 a/d conversion characteristics conditions: v cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ss = av ss = 0v, = 4 mhz to 20 mhz, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide- range specifications) item min. typ. max. unit resolution 10 10 10 bits conversion time 10 ? 200 s analog input capacitance ? ? 20 pf permissible signal-source impedance ? ? 5 k nonlinearity error ? ? 3.5 lsb offset error ? ? 3.5 lsb full-scale error ? ? 3.5 lsb quantization ? 0.5 ? lsb absolute accuracy ? ? 4.0 lsb section 21 electrical characteristics rev. 7.00 sep. 11, 2009 page 517 of 566 rej09b0211-0700 21.5 flash memory characteristics table 21.8 lists the flash memory characteristics. table 21.8 flash memory characteristics conditions: v cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ss = pllv ss = av ss = 0 v, t a = 0 to +75c (programming/erasing operating temperature range) item symbol min. typ. max. unit test condition programming time * 1 * 2 * 4 t p ? 10 200 ms/ 128 bytes erase time * 1 * 3 * 5 t e ? 100 1200 ms/block reprogramming count n wec ? ? 100 times programming wait time after swe bit setting * 1 t sswe 1 1 ? s wait time after psu bit setting * 1 t spsu 50 50 ? s wait time after p bit setting * 1 * 4 t sp30 28 30 32 s programming time wait t sp200 198 200 202 s programming time wait t sp10 8 10 12 s additional- programming time wait wait time after p bit clear * 1 t cp 5 5 ? s wait time after psu bit clear * 1 t cpsu 5 5 ? s wait time after pv bit setting * 1 t spv 4 4 ? s wait time after h'ff dummy write * 1 t spvr 2 2 ? s wait time after pv bit clear * 1 t cpv 2 2 ? s wait time after swe bit clear * 1 t cswe 100 100 ? s maximum programming count * 1 * 4 n ? ? 1000 times erase wait time after swe bit setting * 1 t sswe 1 1 ? s wait time after esu bit setting * 1 t sesu 100 100 ? s wait time after e bit setting * 1 * 5 t se 10 10 100 ms erase time wait wait time after e bit clear * 1 t ce 10 10 ? s wait time after esu bit clear * 1 t cesu 10 10 ? s wait time after ev bit setting * 1 t sev 20 20 ? s wait time after h'ff dummy write * 1 t sevr 2 2 ? s wait time after ev bit clear * 1 t cev 4 4 ? s wait time after swe bit clear * 1 t cswe 100 100 ? s maximum erase count * 1 * 5 n 12 ? 120 times section 21 electrical characteristics rev. 7.00 sep. 11, 2009 page 518 of 566 rej09b0211-0700 notes: 1. make each time setting in accordan ce with the program/program-verify flowchart or erase/erase-verify flowchart. 2. programming time per 128 bytes (shows the total period for which the p-bit in the flash memory control register (flmcr1) is set. it does not include the programming verification time.) 3. block erase time (shows the total period for which the e-bit flmcr1 is set. it does not include the erase verification time.) 4. to specify the maximum programming time value (tp (max.)) in the 128-bytes programming algorithm, set the max. value (1000) for the maximum programming count (n). the wait time after p bit setting should be changed as follows according to the value of the programming counter (n). programming counter (n) = 1 to 6: t sp30 = 30 s programming counter (n) = 7 to 1000: t sp200 = 200 s [in additional programming] programming counter (n) = 1 to 6: t sp10 = 10 s 5. for the maximum erase time (t e (max.)), the following relationship applies between the wait time after e bit setting (t se ) and the maximum erase count (n): t e (max.) = wait time after e bit setting (t se ) x maximum erase count (n) to set the maximum erase time, the values of (t se ) and (n) should be set so as to satisfy the above formula. examples: when t se = 100 ms, n = 12 times when t se = 10 ms, n = 120 times appendix rev. 7.00 sep. 11, 2009 page 519 of 566 rej09b0211-0700 appendix note: mmt, dtc, pbc, and ppg functions are not implemented in the h8s/2614 and h8s/2616. a. on-chip i/o register a.1 register addresses register name abbrevia- tion bit no. address * module data width access state master control register mcr 8 h'f800 hcan 16 4 general status register gsr 8 h'f801 hcan 16 4 bit configuration register bcr 16 h'f802 hcan 16 4 mailbox configuration register mbcr 16 h'f804 hcan 16 4 transmit wait register txpr 16 h'f806 hcan 16 4 transmit wait cancel register txcr 16 h'f808 hcan 16 4 transmit acknowledge register txack 16 h'f80a hcan 16 4 abort acknowledge register aback 16 h'f80c hcan 16 4 receive complete register rxpr 16 h'f80e hcan 16 4 remote request register rfpr 16 h'f810 hcan 16 4 interrupt register irr 16 h'f812 hcan 16 4 mailbox interrupt mask register mbimr 16 h'f814 hcan 16 4 interrupt mask register imr 16 h'f816 hcan 16 4 receive error counter rec 8 h'f818 hcan 16 4 transmit error counter tec 8 h'f819 hcan 16 4 unread message status register umsr 16 h'f81a hcan 16 4 local acceptance filter mask l lafml 16 h'f81c hcan 16 4 local acceptance filter mask h lafmh 16 h'f81e hcan 16 4 message control 0[1] mc0[1] 8 h'f820 hcan 16 4 message control 0[2] mc0[2] 8 h'f821 hcan 16 4 message control 0[3] mc0[3] 8 h'f822 hcan 16 4 message control 0[4] mc0[4] 8 h'f823 hcan 16 4 message control 0[5] mc0[5] 8 h'f824 hcan 16 4 message control 0[6] mc0[6] 8 h'f825 hcan 16 4 message control 0[7] mc0[7] 8 h'f826 hcan 16 4 message control 0[8] mc0[8] 8 h'f827 hcan 16 4 appendix rev. 7.00 sep. 11, 2009 page 520 of 566 rej09b0211-0700 register name abbrevia- tion bit no. address * module data width access state message control 1[1] mc1[1] 8 h'f828 hcan 16 4 message control 1[2] mc1[2] 8 h'f829 hcan 16 4 message control 1[3] mc1[3] 8 h'f82a hcan 16 4 message control 1[4] mc1[4] 8 h'f82b hcan 16 4 message control 1[5] mc1[5] 8 h'f82c hcan 16 4 message control 1[6] mc1[6] 8 h'f82d hcan 16 4 message control 1[7] mc1[7] 8 h'f82e hcan 16 4 message control 1[8] mc1[8] 8 h'f82f hcan 16 4 message control 2[1] mc2[1] 8 h'f830 hcan 16 4 message control 2[2] mc2[2] 8 h'f831 hcan 16 4 message control 2[3] mc2[3] 8 h'f832 hcan 16 4 message control 2[4] mc2[4] 8 h'f833 hcan 16 4 message control 2[5] mc2[5] 8 h'f834 hcan 16 4 message control 2[6] mc2[6] 8 h'f835 hcan 16 4 message control 2[7] mc2[7] 8 h'f836 hcan 16 4 message control 2[8] mc2[8] 8 h'f837 hcan 16 4 message control 3[1] mc3[1] 8 h'f838 hcan 16 4 message control 3[2] mc3[2] 8 h'f839 hcan 16 4 message control 3[3] mc3[3] 8 h'f83a hcan 16 4 message control 3[4] mc3[4] 8 h'f83b hcan 16 4 message control 3[5] mc3[5] 8 h'f83c hcan 16 4 message control 3[6] mc3[6] 8 h'f83d hcan 16 4 message control 3[7] mc3[7] 8 h'f83e hcan 16 4 message control 3[8] mc3[8] 8 h'f83f hcan 16 4 message control 4[1] mc4[1] 8 h'f840 hcan 16 4 message control 4[2] mc4[2] 8 h'f841 hcan 16 4 message control 4[3] mc4[3] 8 h'f842 hcan 16 4 message control 4[4] mc4[4] 8 h'f843 hcan 16 4 message control 4[5] mc4[5] 8 h'f844 hcan 16 4 message control 4[6] mc4[6] 8 h'f845 hcan 16 4 message control 4[7] mc4[7] 8 h'f846 hcan 16 4 message control 4[8] mc4[8] 8 h'f847 hcan 16 4 message control 5[1] mc5[1] 8 h'f848 hcan 16 4 message control 5[2] mc5[2] 8 h'f849 hcan 16 4 appendix rev. 7.00 sep. 11, 2009 page 521 of 566 rej09b0211-0700 register name abbrevia- tion bit no. address * module data width access state message control 5[3] mc5[3] 8 h'f84a hcan 16 4 message control 5[4] mc5[4] 8 h'f84b hcan 16 4 message control 5[5] mc5[5] 8 h'f84c hcan 16 4 message control 5[6] mc5[6] 8 h'f84d hcan 16 4 message control 5[7] mc5[7] 8 h'f84e hcan 16 4 message control 5[8] mc5[8] 8 h'f84f hcan 16 4 message control 6[1] mc6[1] 8 h'f850 hcan 16 4 message control 6[2] mc6[2] 8 h'f851 hcan 16 4 message control 6[3] mc6[3] 8 h'f852 hcan 16 4 message control 6[4] mc6[4] 8 h'f853 hcan 16 4 message control 6[5] mc6[5] 8 h'f854 hcan 16 4 message control 6[6] mc6[6] 8 h'f855 hcan 16 4 message control 6[7] mc6[7] 8 h'f856 hcan 16 4 message control 6[8] mc6[8] 8 h'f857 hcan 16 4 message control 7[1] mc7[1] 8 h'f858 hcan 16 4 message control 7[2] mc7[2] 8 h'f859 hcan 16 4 message control 7[3] mc7[3] 8 h'f85a hcan 16 4 message control 7[4] mc7[4] 8 h'f85b hcan 16 4 message control 7[5] mc7[5] 8 h'f85c hcan 16 4 message control 7[6] mc7[6] 8 h'f85d hcan 16 4 message control 7[7] mc7[7] 8 h'f85e hcan 16 4 message control 7[8] mc7[8] 8 h'f85f hcan 16 4 message control 8[1] mc8[1] 8 h'f860 hcan 16 4 message control 8[2] mc8[2] 8 h'f861 hcan 16 4 message control 8[3] mc8[3] 8 h'f862 hcan 16 4 message control 8[4] mc8[4] 8 h'f863 hcan 16 4 message control 8[5] mc8[5] 8 h'f864 hcan 16 4 message control 8[6] mc8[6] 8 h'f865 hcan 16 4 message control 8[7] mc8[7] 8 h'f866 hcan 16 4 message control 8[8] mc8[8] 8 h'f867 hcan 16 4 message control 9[1] mc9[1] 8 h'f868 hcan 16 4 message control 9[2] mc9[2] 8 h'f869 hcan 16 4 message control 9[3] mc9[3] 8 h'f86a hcan 16 4 message control 9[4] mc9[4] 8 h'f86b hcan 16 4 appendix rev. 7.00 sep. 11, 2009 page 522 of 566 rej09b0211-0700 register name abbrevia- tion bit no. address * module data width access state message control 9[5] mc9[5] 8 h'f86c hcan 16 4 message control 9[6] mc9[6] 8 h'f86d hcan 16 4 message control 9[7] mc9[7] 8 h'f86e hcan 16 4 message control 9[8] mc9[8] 8 h'f86f hcan 16 4 message control 10[1] mc10[1] 8 h'f870 hcan 16 4 message control 10[2] mc10[2] 8 h'f871 hcan 16 4 message control 10[3] mc10[3] 8 h'f872 hcan 16 4 message control 10[4] mc10[4] 8 h'f873 hcan 16 4 message control 10[5] mc10[5] 8 h'f874 hcan 16 4 message control 10[6] mc10[6] 8 h'f875 hcan 16 4 message control 10[7] mc10[7] 8 h'f876 hcan 16 4 message control 10[8] mc10[8] 8 h'f877 hcan 16 4 message control 11[1] mc11[1] 8 h'f878 hcan 16 4 message control 11[2] mc11[2] 8 h'f879 hcan 16 4 message control 11[3] mc11[3] 8 h'f87a hcan 16 4 message control 11[4] mc11[4] 8 h'f87b hcan 16 4 message control 11[5] mc11[5] 8 h'f87c hcan 16 4 message control 11[6] mc11[6] 8 h'f87d hcan 16 4 message control 11[7] mc11[7] 8 h'f87e hcan 16 4 message control 11[8] mc11[8] 8 h'f87f hcan 16 4 message control 12[1] mc12[1] 8 h'f880 hcan 16 4 message control 12[2] mc12[2] 8 h'f881 hcan 16 4 message control 12[3] mc12[3] 8 h'f882 hcan 16 4 message control 12[4] mc12[4] 8 h'f883 hcan 16 4 message control 12[5] mc12[5] 8 h'f884 hcan 16 4 message control 12[6] mc12[6] 8 h'f885 hcan 16 4 message control 12[7] mc12[7] 8 h'f886 hcan 16 4 message control 12[8] mc12[8] 8 h'f887 hcan 16 4 message control 13[1] mc13[1] 8 h'f888 hcan 16 4 message control 13[2] mc13[2] 8 h'f889 hcan 16 4 message control 13[3] mc13[3] 8 h'f88a hcan 16 4 message control 13[4] mc13[4] 8 h'f88b hcan 16 4 message control 13[5] mc13[5] 8 h'f88c hcan 16 4 message control 13[6] mc13[6] 8 h'f88d hcan 16 4 appendix rev. 7.00 sep. 11, 2009 page 523 of 566 rej09b0211-0700 register name abbrevia- tion bit no. address * module data width access state message control 13[7] mc13[7] 8 h'f88e hcan 16 4 message control 13[8] mc13[8] 8 h'f88f hcan 16 4 message control 14[1] mc14[1] 8 h'f890 hcan 16 4 message control 14[2] mc14[2] 8 h'f891 hcan 16 4 message control 14[3] mc14[3] 8 h'f892 hcan 16 4 message control 14[4] mc14[4] 8 h'f893 hcan 16 4 message control 14[5] mc14[5] 8 h'f894 hcan 16 4 message control 14[6] mc14[6] 8 h'f895 hcan 16 4 message control 14[7] mc14[7] 8 h'f896 hcan 16 4 message control 14[8] mc14[8] 8 h'f897 hcan 16 4 message control 15[1] mc15[1] 8 h'f898 hcan 16 4 message control 15[2] mc15[2] 8 h'f899 hcan 16 4 message control 15[3] mc15[3] 8 h'f89a hcan 16 4 message control 15[4] mc15[4] 8 h'f89b hcan 16 4 message control 15[5] mc15[5] 8 h'f89c hcan 16 4 message control 15[6] mc15[6] 8 h'f89d hcan 16 4 message control 15[7] mc15[7] 8 h'f89e hcan 16 4 message control 15[8] mc15[8] 8 h'f89f hcan 16 4 message data 0[1] md0[1] 8 h'f8b0 hcan 16 4 message data 0[2] md0[2] 8 h'f8b1 hcan 16 4 message data 0[3] md0[3] 8 h'f8b2 hcan 16 4 message data 0[4] md0[4] 8 h'f8b3 hcan 16 4 message data 0[5] md0[5] 8 h'f8b4 hcan 16 4 message data 0[6] md0[6] 8 h'f8b5 hcan 16 4 message data 0[7] md0[7] 8 h'f8b6 hcan 16 4 message data 0[8] md0[8] 8 h'f8b7 hcan 16 4 message data 1[1] md1[1] 8 h'f8b8 hcan 16 4 message data 1[2] md1[2] 8 h'f8b9 hcan 16 4 message data 1[3] md1[3] 8 h'f8ba hcan 16 4 message data 1[4] md1[4] 8 h'f8bb hcan 16 4 message data 1[5] md1[5] 8 h'f8bc hcan 16 4 message data 1[6] md1[6] 8 h'f8bd hcan 16 4 message data 1[7] md1[7] 8 h'f8be hcan 16 4 message data 1[8] md1[8] 8 h'f8bf hcan 16 4 appendix rev. 7.00 sep. 11, 2009 page 524 of 566 rej09b0211-0700 register name abbrevia- tion bit no. address * module data width access state message data 2[1] md2[1] 8 h'f8c0 hcan 16 4 message data 2[2] md2[2] 8 h'f8c1 hcan 16 4 message data 2[3] md2[3] 8 h'f8c2 hcan 16 4 message data 2[4] md2[4] 8 h'f8c3 hcan 16 4 message data 2[5] md2[5] 8 h'f8c4 hcan 16 4 message data 2[6] md2[6] 8 h'f8c5 hcan 16 4 message data 2[7] md2[7] 8 h'f8c6 hcan 16 4 message data 2[8] md2[8] 8 h'f8c7 hcan 16 4 message data 3[1] md3[1] 8 h'f8c8 hcan 16 4 message data 3[2] md3[2] 8 h'f8c9 hcan 16 4 message data 3[3] md3[3] 8 h'f8ca hcan 16 4 message data 3[4] md3[4] 8 h'f8cb hcan 16 4 message data 3[5] md3[5] 8 h'f8cc hcan 16 4 message data 3[6] md3[6] 8 h'f8cd hcan 16 4 message data 3[7] md3[7] 8 h'f8ce hcan 16 4 message data 3[8] md3[8] 8 h'f8cf hcan 16 4 message data 4[1] md4[1] 8 h'f8d0 hcan 16 4 message data 4[2] md4[2] 8 h'f8d1 hcan 16 4 message data 4[3] md4[3] 8 h'f8d2 hcan 16 4 message data 4[4] md4[4] 8 h'f8d3 hcan 16 4 message data 4[5] md4[5] 8 h'f8d4 hcan 16 4 message data 4[6] md4[6] 8 h'f8d5 hcan 16 4 message data 4[7] md4[7] 8 h'f8d6 hcan 16 4 message data 4[8] md4[8] 8 h'f8d7 hcan 16 4 message data 5[1] md5[1] 8 h'f8d8 hcan 16 4 message data 5[2] md5[2] 8 h'f8d9 hcan 16 4 message data 5[3] md5[3] 8 h'f8da hcan 16 4 message data 5[4] md5[4] 8 h'f8db hcan 16 4 message data 5[5] md5[5] 8 h'f8dc hcan 16 4 message data 5[6] md5[6] 8 h'f8dd hcan 16 4 message data 5[7] md5[7] 8 h'f8de hcan 16 4 message data 5[8] md5[8] 8 h'f8df hcan 16 4 message data 6[1] md6[1] 8 h'f8e0 hcan 16 4 message data 6[2] md6[2] 8 h'f8e1 hcan 16 4 appendix rev. 7.00 sep. 11, 2009 page 525 of 566 rej09b0211-0700 register name abbrevia- tion bit no. address * module data width access state message data 6[3] md6[3] 8 h'f8e2 hcan 16 4 message data 6[4] md6[4] 8 h'f8e3 hcan 16 4 message data 6[5] md6[5] 8 h'f8e4 hcan 16 4 message data 6[6] md6[6] 8 h'f8e5 hcan 16 4 message data 6[7] md6[7] 8 h'f8e6 hcan 16 4 message data 6[8] md6[8] 8 h'f8e7 hcan 16 4 message data 7[1] md7[1] 8 h'f8e8 hcan 16 4 message data 7[2] md7[2] 8 h'f8e9 hcan 16 4 message data 7[3] md7[3] 8 h'f8ea hcan 16 4 message data 7[4] md7[4] 8 h'f8eb hcan 16 4 message data 7[5] md7[5] 8 h'f8ec hcan 16 4 message data 7[6] md7[6] 8 h'f8ed hcan 16 4 message data 7[7] md7[7] 8 h'f8ee hcan 16 4 message data 7[8] md7[8] 8 h'f8ef hcan 16 4 message data 8[1] md8[1] 8 h'f8f0 hcan 16 4 message data 8[2] md8[2] 8 h'f8f1 hcan 16 4 message data 8[3] md8[3] 8 h'f8f2 hcan 16 4 message data 8[4] md8[4] 8 h'f8f3 hcan 16 4 message data 8[5] md8[5] 8 h'f8f4 hcan 16 4 message data 8[6] md8[6] 8 h'f8f5 hcan 16 4 message data 8[7] md8[7] 8 h'f8f6 hcan 16 4 message data 8[8] md8[8] 8 h'f8f7 hcan 16 4 message data 9[1] md9[1] 8 h'f8f8 hcan 16 4 message data 9[2] md9[2] 8 h'f8f9 hcan 16 4 message data 9[3] md9[3] 8 h'f8fa hcan 16 4 message data 9[4] md9[4] 8 h'f8fb hcan 16 4 message data 9[5] md9[5] 8 h'f8fc hcan 16 4 message data 9[6] md9[6] 8 h'f8fd hcan 16 4 message data 9[7] md9[7] 8 h'f8fe hcan 16 4 message data 9[8] md9[8] 8 h'f8ff hcan 16 4 message data 10[1] md10[1] 8 h'f900 hcan 16 4 message data 10[2] md10[2] 8 h'f901 hcan 16 4 message data 10[3] md10[3] 8 h'f902 hcan 16 4 message data 10[4] md10[4] 8 h'f903 hcan 16 4 appendix rev. 7.00 sep. 11, 2009 page 526 of 566 rej09b0211-0700 register name abbrevia- tion bit no. address * module data width access state message data 10[5] md10[5] 8 h'f904 hcan 16 4 message data 10[6] md10[6] 8 h'f905 hcan 16 4 message data 10[7] md10[7] 8 h'f906 hcan 16 4 message data 10[8] md10[8] 8 h'f907 hcan 16 4 message data 11[1] md11[1] 8 h'f908 hcan 16 4 message data 11[2] md11[2] 8 h'f909 hcan 16 4 message data 11[3] md11[3] 8 h'f90a hcan 16 4 message data 11[4] md11[4] 8 h'f90b hcan 16 4 message data 11[5] md11[5] 8 h'f90c hcan 16 4 message data 11[6] md11[6] 8 h'f90d hcan 16 4 message data 11[7] md11[7] 8 h'f90e hcan 16 4 message data 11[8] md11[8] 8 h'f90f hcan 16 4 message data 12[1] md12[1] 8 h'f910 hcan 16 4 message data 12[2] md12[2] 8 h'f911 hcan 16 4 message data 12[3] md12[3] 8 h'f912 hcan 16 4 message data 12[4] md12[4] 8 h'f913 hcan 16 4 message data 12[5] md12[5] 8 h'f914 hcan 16 4 message data 12[6] md12[6] 8 h'f915 hcan 16 4 message data 12[7] md12[7] 8 h'f916 hcan 16 4 message data 12[8] md12[8] 8 h'f917 hcan 16 4 message data 13[1] md13[1] 8 h'f918 hcan 16 4 message data 13[2] md13[2] 8 h'f919 hcan 16 4 message data 13[3] md13[3] 8 h'f91a hcan 16 4 message data 13[4] md13[4] 8 h'f91b hcan 16 4 message data 13[5] md13[5] 8 h'f91c hcan 16 4 message data 13[6] md13[6] 8 h'f91d hcan 16 4 message data 13[7] md13[7] 8 h'f91e hcan 16 4 message data 13[8] md13[8] 8 h'f91f hcan 16 4 message data 14[1] md14[1] 8 h'f920 hcan 16 4 message data 14[2] md14[2] 8 h'f921 hcan 16 4 message data 14[3] md14[3] 8 h'f922 hcan 16 4 message data 14[4] md14[4] 8 h'f923 hcan 16 4 message data 14[5] md14[5] 8 h'f924 hcan 16 4 message data 14[6] md14[6] 8 h'f925 hcan 16 4 appendix rev. 7.00 sep. 11, 2009 page 527 of 566 rej09b0211-0700 register name abbrevia- tion bit no. address * module data width access state message data 14[7] md14[7] 8 h'f926 hcan 16 4 message data 14[8] md14[8] 8 h'f927 hcan 16 4 message data 15[1] md15[1] 8 h'f928 hcan 16 4 message data 15[2] md15[2] 8 h'f929 hcan 16 4 message data 15[3] md15[3] 8 h'f92a hcan 16 4 message data 15[4] md15[4] 8 h'f92b hcan 16 4 message data 15[5] md15[5] 8 h'f92c hcan 16 4 message data 15[6] md15[6] 8 h'f92d hcan 16 4 message data 15[7] md15[7] 8 h'f92e hcan 16 4 message data 15[8] md15[8] 8 h'f92f hcan 16 4 hcan monitor register hcanmon 8 h'fa00 hcan 16 4 timer mode register tmdr 8 h'fb00 mmt 16 3 timer control register tcnr 8 h'fb02 mmt 16 3 timer status register tsr 8 h'fb04 mmt 16 3 timer counter tcnt 16 h'fb06 mmt 16 3 timer period data register tpdr 16 h'fb08 mmt 16 3 timer period buffer register tpbr 16 h'fb0a mmt 16 3 timer dead time data register tddr 16 h'fb0c mmt 16 3 mmt pin control register mmtpc 8 h'fb0e mmt 16 3 timer buffer register u (for a buffer operation) tbru 16 h'fb10 mmt 16 3 timer general register uu tgruu 16 h'fb12 mmt 16 3 timer general register u tgru 16 h'fb14 mmt 16 3 timer general register ud tgrud 16 h'fb16 mmt 16 3 timer dead time counter 0 tdcnt0 16 h'fb18 mmt 16 3 timer dead time counter 1 tdcnt1 16 h'fb1a mmt 16 3 timer buffer register u (for a free operation) tbru 16 h'fb1c mmt 16 3 timer buffer register v (for a buffer operation) tbrv 16 h'fb20 mmt 16 3 timer general register vu tgrvu 16 h'fb22 mmt 16 3 timer general register v tgrv 16 h'fb24 mmt 16 3 timer general register vd tgrvd 16 h'fb26 mmt 16 3 timer dead time counter 2 tdcnt2 16 h'fb28 mmt 16 3 timer dead time counter 3 tdcnt3 16 h'fb2a mmt 16 3 appendix rev. 7.00 sep. 11, 2009 page 528 of 566 rej09b0211-0700 register name abbrevia- tion bit no. address * module data width access state timer buffer register v (for a free operation) tbrv 16 h'fb2c mmt 16 3 timer buffer register w (for a buffer operation) tbrw 16 h'fb30 mmt 16 3 timer general register wu tgrwu 16 h'fb32 mmt 16 3 timer general register w tgrw 16 h'fb34 mmt 16 3 timer general register wd tgrwd 16 h'fb36 mmt 16 3 timer dead time counter4 tdcnt4 16 h'fb38 mmt 16 3 timer dead time counter5 tdcnt5 16 h'fb3a mmt 16 3 timer buffer register w (for a free operation) tbrw 16 h'fb3c mmt 16 3 input level control/status register icsr 16 h'fc00 poe 16 3 poe pin control register poepc 8 h'fc02 poe 16 3 standby control register sbycr 8 h'fde4 system 8 2 system control register syscr 8 h'fde5 system 8 2 system clock control register sckcr 8 h'fde6 system 8 2 mode control register mdcr 8 h'fde7 system 8 2 module stop control register a mstpcra 8 h'fde8 system 8 2 module stop control register b mstpcrb 8 h'fde9 system 8 2 module stop control register c mstpcrc 8 h'fdea system 8 2 low-power control register lpwrcr 8 h'fdec system 8 2 break address register a bara 32 h'fe00 pbc 32 2 break address register b barb 32 h'fe04 pbc 32 2 break control register a bcra 8 h'fe08 pbc 8 2 break control register b bcrb 8 h'fe09 pbc 8 2 irq sense control register h iscrh 8 h'fe12 int 8 2 irq sense control register l iscrl 8 h'fe13 int 8 2 irq enable register ier 8 h'fe14 int 8 2 irq status register isr 8 h'fe15 int 8 2 dtc enable register a dtcera 8 h'fe16 dtc 8 2 dtc enable register b dtcerb 8 h'fe17 dtc 8 2 dtc enable register c dtcerc 8 h'fe18 dtc 8 2 dtc enable register d dtcerd 8 h'fe19 dtc 8 2 dtc enable register e dtcere 8 h'fe1a dtc 8 2 dtc enable register f dtcerf 8 h'fe1b dtc 8 2 appendix rev. 7.00 sep. 11, 2009 page 529 of 566 rej09b0211-0700 register name abbrevia- tion bit no. address * module data width access state dtc enable register g dtcerg 8 h'fe1c dtc 8 2 dtc vector register dtvecr 8 h'fe1f dtc 8 2 ppg output control register pcr 8 h'fe26 ppg 8 2 ppg output mode register pmr 8 h'fe27 ppg 8 2 next data enable register h nderh 8 h'fe28 ppg 8 2 next data enable register l nderl 8 h'fe29 ppg 8 2 output data register h podrh 8 h'fe2a ppg 8 2 output data register l podrl 8 h'fe2b ppg 8 2 next data register h ndrh 8 h'fe2c ppg 8 2 next data register l ndrl 8 h'fe2d ppg 8 2 next data register h ndrh 8 h'fe2e ppg 8 2 next data register l ndrl 8 h'fe2f ppg 8 2 port 1 data direction register p1ddr 8 h'fe30 port 8 2 port a data direction register paddr 8 h'fe39 port 8 2 port b data direction register pbddr 8 h'fe3a port 8 2 port c data direction register pcddr 8 h'fe3b port 8 2 port d data direction register pdddr 8 h'fe3c port 8 2 port f data direction register pfddr 8 h'fe3e port 8 2 port a pull-up mos control register papcr 8 h'fe40 port 8 2 port b pull-up mos control register pbpcr 8 h'fe41 port 8 2 port c pull-up mos control register pcpcr 8 h'fe42 port 8 2 port d pull-up mos control register pdpcr 8 h'fe43 port 8 2 port a open drain control register paodr 8 h'fe47 port 8 2 port b open drain control register pbodr 8 h'fe48 port 8 2 port c open drain control register pcodr 8 h'fe49 port 8 2 timer control register_3 tcr_3 8 h'fe80 tpu_3 16 2 timer mode register_3 tmdr_3 8 h'fe81 tpu_3 16 2 timer i/o control register h_3 tiorh_3 8 h'fe82 tpu_3 16 2 timer i/o control register l_3 tiorl_3 8 h'fe83 tpu_3 16 2 timer interrupt enable register_3 tier_3 8 h'fe84 tpu_3 16 2 timer status register_3 tsr_3 8 h'fe85 tpu_3 16 2 timer counter h_3 tcnth_3 8 h'fe86 tpu_3 16 2 timer counter l_3 tcntl_3 8 h'fe87 tpu_3 16 2 timer general register ah_3 tgrah_3 8 h'fe88 tpu_3 16 2 appendix rev. 7.00 sep. 11, 2009 page 530 of 566 rej09b0211-0700 register name abbrevia- tion bit no. address * module data width access state timer general register al_3 tgral_3 8 h'fe89 tpu_3 16 2 timer general register bh_3 tgrbh_3 8 h'fe8a tpu_3 16 2 timer general register bl_3 tgrbl_3 8 h'fe8b tpu_3 16 2 timer general register ch_3 tgrch_3 8 h'fe8c tpu_3 16 2 timer general register cl_3 tgrcl_3 8 h'fe8d tpu_3 16 2 timer general register dh_3 tgrdh_3 8 h'fe8e tpu_3 16 2 timer general register dl_3 tgrdl_3 8 h'fe8f tpu_3 16 2 timer control register_4 tcr_4 8 h'fe90 tpu_4 16 2 timer mode register_4 tmdr_4 8 h'fe91 tpu_4 16 2 timer i/o control register_4 tior_4 8 h'fe92 tpu_4 16 2 timer interrupt enable register_4 tier_4 8 h'fe94 tpu_4 16 2 timer status register_4 tsr_4 8 h'fe95 tpu_4 16 2 timer counter h_4 tcnth_4 8 h'fe96 tpu_4 16 2 timer counter l_4 tcntl_4 8 h'fe97 tpu_4 16 2 timer general register ah_4 tgrah_4 8 h'fe98 tpu_4 16 2 timer general register al_4 tgral_4 8 h'fe99 tpu_4 16 2 timer general register bh_4 tgrbh_4 8 h'fe9a tpu_4 16 2 timer general register bl_4 tgrbl_4 8 h'fe9b tpu_4 16 2 timer control register_5 tcr_5 8 h'fea0 tpu_5 16 2 timer mode register_5 tmdr_5 8 h'fea1 tpu_5 16 2 timer i/o control register_5 tior_5 8 h'fea2 tpu_5 16 2 timer interrupt enable register_5 tier_5 8 h'fea4 tpu_5 16 2 timer status register_5 tsr_5 8 h'fea5 tpu_5 16 2 timer counter h_5 tcnth_5 8 h'fea6 tpu_5 16 2 timer counter l_5 tcntl_5 8 h'fea7 tpu_5 16 2 timer general register ah_5 tgrah_5 8 h'fea8 tpu_5 16 2 timer general register al_5 tgral_5 8 h'fea9 tpu_5 16 2 timer general register bh_5 tgrbh_5 8 h'f eaa tpu_5 16 2 timer general register bl_5 tgrbl_5 8 h'feab tpu_5 16 2 timer start register tstr 8 h'feb0 tpu common 16 2 timer synchro register tsyr 8 h'feb1 tpu common 16 2 interrupt priority register a ipra 8 h'fec0 int 8 2 interrupt priority register b iprb 8 h'fec1 int 8 2 appendix rev. 7.00 sep. 11, 2009 page 531 of 566 rej09b0211-0700 register name abbrevia- tion bit no. address * module data width access state interrupt priority register c iprc 8 h'fec2 int 8 2 interrupt priority register d iprd 8 h'fec3 int 8 2 interrupt priority register e ipre 8 h'fec4 int 8 2 interrupt priority register f iprf 8 h'fec5 int 8 2 interrupt priority register g iprg 8 h'fec6 int 8 2 interrupt priority register h iprh 8 h'fec7 int 8 2 interrupt priority register j iprj 8 h'fec9 int 8 2 interrupt priority register k iprk 8 h'feca int 8 2 interrupt priority register m iprm 8 h'fecc int 8 2 ram emulation register ramer 8 h'fedb rom 8 2 port 1 data register p1dr 8 h'ff00 port 8 2 port a data register padr 8 h'ff09 port 8 2 port b data register pbdr 8 h'ff0a port 8 2 port c data register pcdr 8 h'ff0b port 8 2 port d data register pddr 8 h'ff0c port 8 2 port f data register pfdr 8 h'ff0e port 8 2 timer control register_0 tcr_0 8 h'ff10 tpu_0 16 2 timer mode register_0 tmdr_0 8 h'ff11 tpu_0 16 2 timer i/o control register h_0 tiorh_0 8 h'ff12 tpu_0 16 2 timer i/o control register l_0 tiorl_0 8 h'ff13 tpu_0 16 2 timer interrupt enable register_0 tier_0 8 h'ff14 tpu_0 16 2 timer status register_0 tsr_0 8 h'ff15 tpu_0 16 2 timer counter h_0 tcnth_0 8 h'ff16 tpu_0 16 2 timer counter l_0 tcntl_0 8 h'ff17 tpu_0 16 2 timer general register ah_0 tgrah_0 8 h'ff18 tpu_0 16 2 timer general register al_0 tgral_0 8 h'ff19 tpu_0 16 2 timer general register bh_0 tgrbh_0 8 h'ff1a tpu_0 16 2 timer general register bl_0 tgrbl_0 8 h'ff1b tpu_0 16 2 timer general register ch_0 tgrch_0 8 h'ff1c tpu_0 16 2 timer general register cl_0 tgrcl_0 8 h'ff1d tpu_0 16 2 timer general register dh_0 tgrdh_0 8 h'ff1e tpu_0 16 2 timer general register dl_0 tgrdl_0 8 h'ff1f tpu_0 16 2 timer control register_1 tcr_1 8 h'ff20 tpu_1 16 2 timer mode register_1 tmdr_1 8 h'ff21 tpu_1 16 2 appendix rev. 7.00 sep. 11, 2009 page 532 of 566 rej09b0211-0700 register name abbrevia- tion bit no. address * module data width access state timer i/o control register_1 tior_1 8 h'ff22 tpu_1 16 2 timer interrupt enable register_1 tier_1 8 h'ff24 tpu_1 16 2 timer status register_1 tsr_1 8 h'ff25 tpu_1 16 2 timer counter h_1 tcnth_1 8 h'ff26 tpu_1 16 2 timer counter l_1 tcntl_1 8 h'ff27 tpu_1 16 2 timer general register ah_1 tgrah_1 8 h'ff28 tpu_1 16 2 timer general register al_1 tgral_1 8 h'ff29 tpu_1 16 2 timer general register bh_1 tgrbh_1 8 h'ff2a tpu_1 16 2 timer general register bl_1 tgrbl_1 8 h'ff2b tpu_1 16 2 timer control register_2 tcr_2 8 h'ff30 tpu_2 16 2 timer mode register_2 tmdr_2 8 h'ff31 tpu_2 16 2 timer i/o control register_2 tior_2 8 h'ff32 tpu_2 16 2 timer interrupt enable register_2 tier_2 8 h'ff34 tpu_2 16 2 timer status register_2 tsr_2 8 h'ff35 tpu_2 16 2 timer counter h_2 tcnth_2 8 h'ff36 tpu_2 16 2 timer counter l_2 tcntl_2 8 h'ff37 tpu_2 16 2 timer general register ah_2 tgrah_2 8 h'ff38 tpu_2 16 2 timer general register al_2 tgral_2 8 h'ff39 tpu_2 16 2 timer general register bh_2 tgrbh_2 8 h'ff3a tpu_2 16 2 timer general register bl_2 tgrbl_2 8 h'ff3b tpu_2 16 2 timer control/status register tcsr 8 h'ff74 wdt 16 2 timer counter tcnt 8 h'ff75 wdt 16 2 reset control/status register rstcsr 8 h'ff77 wdt 16 2 serial mode register_0 smr_0 8 h'ff78 sci_0 8 2 bit rate register_0 brr_0 8 h'ff79 sci_0 8 2 serial control register_0 scr_0 8 h'ff7a sci_0 8 2 transmit data register_0 tdr_0 8 h'ff7b sci_0 8 2 serial status register_0 ssr_0 8 h'ff7c sci_0 8 2 receive data register_0 rdr_0 8 h'ff7d sci_0 8 2 smart card mode register_0 scmr_0 8 h'ff7e sci_0 8 2 serial mode register_1 smr_1 8 h'ff80 sci_1 8 2 bit rate register_1 brr_1 8 h'ff81 sci_1 8 2 serial control register_1 scr_1 8 h'ff82 sci_1 8 2 transmit data register_1 tdr_1 8 h'ff83 sci_1 8 2 appendix rev. 7.00 sep. 11, 2009 page 533 of 566 rej09b0211-0700 register name abbrevia- tion bit no. address * module data width access state serial status register_1 ssr_1 8 h'ff84 sci_1 8 2 receive data register_1 rdr_1 8 h'ff85 sci_1 8 2 smart card mode register_1 scmr_1 8 h'ff86 sci_1 8 2 serial mode register_2 smr_2 8 h'ff88 sci_2 8 2 bit rate register_2 brr_2 8 h'ff89 sci_2 8 2 serial control register_2 scr_2 8 h'ff8a sci_2 8 2 transmit data register_2 tdr_2 8 h'ff8b sci_2 8 2 serial status register_2 ssr_2 8 h'ff8c sci_2 8 2 receive data register_2 rdr_2 8 h'ff8d sci_2 8 2 smart card mode register_2 scmr_2 8 h'ff8e sci_2 8 2 a/d data register ah addrah 8 h'ff90 a/d 8 2 a/d data register al addral 8 h'ff91 a/d 8 2 a/d data register bh addrbh 8 h'ff92 a/d 8 2 a/d data register bl addrbl 8 h'ff93 a/d 8 2 a/d data register ch addrch 8 h'ff94 a/d 8 2 a/d data register cl addrcl 8 h'ff95 a/d 8 2 a/d data register dh addrdh 8 h'ff96 a/d 8 2 a/d data register dl addrdl 8 h'ff97 a/d 8 2 a/d control/status register adcsr 8 h'ff98 a/d 8 2 a/d control register adcr 8 h'ff99 a/d 8 2 flash memory control register 1 flmcr1 8 h'ffa8 rom 8 2 flash memory control register 2 flmcr2 8 h'ffa9 rom 8 2 erase block register 1 ebr1 8 h'ffaa rom 8 2 erase block register 2 ebr2 8 h'ffab rom 8 2 port 1 register port1 8 h'ffb0 port 8 2 port 4 register port4 8 h'ffb3 port 8 2 port 9 register port9 8 h'ffb8 port 8 2 port a register porta 8 h'ffb9 port 8 2 port b register portb 8 h'ffba port 8 2 port c register portc 8 h'ffbb port 8 2 port d register portd 8 h'ffbc port 8 2 port f register portf 8 h'ffbe port 8 2 note: * lower 16 bits of the address. appendix rev. 7.00 sep. 11, 2009 page 534 of 566 rej09b0211-0700 a.2 register bits register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module mcr mcr7 ? mcr5 ? ? mcr2 mcr1 mcr0 hcan gsr ? ? ? ? gsr3 gsr2 gsr1 gsr0 bcr7 bcr6 bcr5 bcr4 b cr3 bcr2 bcr1 bcr0 bcr bcr15 bcr14 bcr13 bcr12 bcr11 bcr10 bcr9 bcr8 mbcr7 mbcr6 mbcr5 mbcr4 mbcr3 mbcr2 mbcr1 ? mbcr mbcr15 mbcr14 mbcr13 mbcr12 mbcr11 mbcr10 mbcr9 mbcr8 txpr7 txpr6 txpr5 txpr4 txpr3 txpr2 txpr1 ? txpr txpr15 txpr14 txpr13 txpr12 t xpr11 txpr10 txpr9 txpr8 txcr7 txcr6 txcr5 txcr4 txcr3 txcr2 txcr1 ? txcr txcr15 txcr14 txcr13 txcr12 txcr11 txcr10 txcr9 txcr8 txack7 txack6 txack5 txack4 txack3 txack2 txack1 ? txack txack15 txack14 txack13 txack12 t xack11 txack10 txack9 txack8 aback7 aback6 aback5 aback4 aback3 aback2 aback1 ? aback aback15 aback14 aback13 aback12 aback11 aback10 aback9 aback8 rxpr7 rxpr6 rxpr5 rxpr4 r xpr3 rxpr2 rxpr1 rxpr0 rxpr rxpr15 rxpr14 rxpr13 rxpr12 r xpr11 rxpr10 rxpr9 rxpr8 rfpr7 rfpr6 rfpr5 rfpr4 rfpr3 rfpr2 rfpr1 rfpr0 rfpr rfpr15 rfpr14 rfpr13 rfpr12 rfpr11 rfpr10 rfpr9 rfpr8 irr7 irr6 irr5 irr4 i rr3 irr2 irr1 irr0 irr ? ? ? irr12 ? ? irr9 irr8 mbimr7 mbimr6 mbimr5 mbimr4 mbimr3 mbimr2 mbimr1 mbimr0 mbimr mbimr15 mbimr14 mbimr13 mbimr12 mbimr11 mbimr10 mbimr9 mbimr8 imr7 imr6 imr5 imr4 imr3 im r2 imr1 ? imr ? ? ? imr12 ? ? imr9 imr8 rec bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tec bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 umsr7 umsr6 umsr5 umsr4 umsr3 umsr2 umsr1 umsr0 umsr umsr15 umsr14 umsr13 umsr12 umsr11 umsr10 umsr9 umsr8 lafml7 lafml6 lafml5 lafml4 lafml3 lafml2 lafml1 lafml0 lafml lafml15 lafml14 lafml13 lafml12 lafml11 lafml10 lafml9 lafml8 lafmh7 lafmh6 lafmh5 ? ? ? lafmh1 lafmh0 lafmh lafmh15 lafmh14 lafmh13 lafmh12 lafmh11 lafmh10 lafmh9 lafmh8 mc0[1] ? ? ? ? dlc3 dlc2 dlc1 dlc0 mc0[2] ? ? ? ? ? ? ? ? mc0[3] ? ? ? ? ? ? ? ? mc0[4] ? ? ? ? ? ? ? ? mc0[5] id-20 id-19 id-18 rtr ide ? id-17 id-16 mc0[6] id-28 id-27 id-26 id- 25 id-24 id-23 id-22 id-21 appendix rev. 7.00 sep. 11, 2009 page 535 of 566 rej09b0211-0700 register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module mc0[7] id-7 id-6 id-5 id-4 id-3 id-2 id-1 id-0 hcan mc0[8] id-15 id-14 id-13 id-12 id-11 id-10 id-9 id-8 mc1[1] ? ? ? ? dlc3 dlc2 dlc1 dlc0 mc1[2] ? ? ? ? ? ? ? ? mc1[3] ? ? ? ? ? ? ? ? mc1[4] ? ? ? ? ? ? ? ? mc1[5] id-20 id-19 id-18 rtr ide ? id-17 id-16 mc1[6] id-28 id-27 id-26 id- 25 id-24 id-23 id-22 id-21 mc1[7] id-7 id-6 id-5 id-4 id-3 id-2 id-1 id-0 mc1[8] id-15 id-14 id-13 id-12 id-11 id-10 id-9 id-8 mc2[1] ? ? ? ? dlc3 dlc2 dlc1 dlc0 mc2[2] ? ? ? ? ? ? ? ? mc2[3] ? ? ? ? ? ? ? ? mc2[4] ? ? ? ? ? ? ? ? mc2[5] id-20 id-19 id-18 rtr ide ? id-17 id-16 mc2[6] id-28 id-27 id-26 id- 25 id-24 id-23 id-22 id-21 mc2[7] id-7 id-6 id-5 id-4 id-3 id-2 id-1 id-0 mc2[8] id-15 id-14 id-13 id12 id-11 id-10 id-9 id-8 mc3[1] ? ? ? ? dlc3 dlc2 dlc1 dlc0 mc3[2] ? ? ? ? ? ? ? ? mc3[3] ? ? ? ? ? ? ? ? mc3[4] ? ? ? ? ? ? ? ? mc3[5] id-20 id-19 id-18 rtr ide ? id-17 id-16 mc3[6] id-28 id-27 id-26 id- 25 id-24 id-23 id-22 id-21 mc3[7] id-7 id-6 id-5 id-4 id-3 id-2 id-1 id-0 mc3[8] id-15 id-14 id-13 id-12 id-11 id-10 id-9 id-8 mc4[1] ? ? ? ? dlc3 dlc2 dlc1 dlc0 mc4[2] ? ? ? ? ? ? ? ? mc4[3] ? ? ? ? ? ? ? ? mc4[4] ? ? ? ? ? ? ? ? mc4[5] id-20 id-19 id-18 rtr ide ? id-17 id-16 mc4[6] id-28 id-27 id-26 id- 25 id-24 id-23 id-22 id-21 mc4[7] id-7 id-6 id-5 id-4 id-3 id-2 id-1 id-0 mc4[8] id-15 id-14 id-13 id-12 id-11 id-10 id-9 id-8 mc5[1] ? ? ? ? dlc3 dlc2 dlc1 dlc0 mc5[2] ? ? ? ? ? ? ? ? mc5[3] ? ? ? ? ? ? ? ? mc5[4] ? ? ? ? ? ? ? ? mc5[5] id-20 id-19 id-18 rtr ide ? id-17 id-16 mc5[6] id-28 id-27 id-26 id- 25 id-24 id-23 id-22 id-21 appendix rev. 7.00 sep. 11, 2009 page 536 of 566 rej09b0211-0700 register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module mc5[7] id-7 id-6 id-5 id-4 id-3 id-2 id-1 id-0 hcan mc5[8] id-15 id-14 id-13 id-12 id-11 id-10 id-9 id-8 mc6[1] ? ? ? ? dlc3 dlc2 dlc1 dlc0 mc6[2] ? ? ? ? ? ? ? ? mc6[3] ? ? ? ? ? ? ? ? mc6[4] ? ? ? ? ? ? ? ? mc6[5] id-20 id-19 id-18 rtr ide ? id-17 id-16 mc6[6] id-28 id-27 id-26 id- 25 id-24 id-23 id-22 id-21 mc6[7] id-7 id-6 id-5 id-4 id-3 id-2 id-1 id-0 mc6[8] id-15 id-14 id-13 id-12 id-11 id-10 id-9 id-8 mc7[1] ? ? ? ? dlc3 dlc2 dlc1 dlc0 mc7[2] ? ? ? ? ? ? ? ? mc7[3] ? ? ? ? ? ? ? ? mc7[4] ? ? ? ? ? ? ? ? mc7[5] id-20 id-19 id-18 rtr ide ? id-17 id-16 mc7[6] id-28 id-27 id-26 id- 25 id-24 id-23 id-22 id-21 mc7[7] id-7 id-6 id-5 id-4 id-3 id-2 id-1 id-0 mc7[8] id-15 id-14 id-13 id-12 id-11 id-10 id-9 id-8 mc8[1] ? ? ? ? dlc3 dlc2 dlc1 dlc0 mc8[2] ? ? ? ? ? ? ? ? mc8[3] ? ? ? ? ? ? ? ? mc8[4] ? ? ? ? ? ? ? ? mc8[5] id-20 id-19 id-18 rtr ide ? id-17 id-16 mc8[6] id-28 id-27 id-26 id- 25 id-24 id-23 id-22 id-21 mc8[7] id-7 id-6 id-5 id-4 id-3 id-2 id-1 id-0 mc8[8] id-15 id-14 id-13 id-12 id-11 id-10 id-9 id-8 mc9[1] ? ? ? ? dlc3 dlc2 dlc1 dlc0 mc9[2] ? ? ? ? ? ? ? ? mc9[3] ? ? ? ? ? ? ? ? mc9[4] ? ? ? ? ? ? ? ? mc9[5] id-20 id-19 id-18 rtr ide ? id-17 id-16 mc9[6] id-28 id-27 id-26 id- 25 id-24 id-23 id-22 id-21 mc9[7] id-7 id-6 id-5 id-4 id-3 id-2 id-1 id-0 mc9[8] id-15 id-14 id-13 id-12 id-11 id-10 id-9 id-8 mc10[1] ? ? ? ? dlc3 dlc2 dlc1 dlc0 mc10[2] ? ? ? ? ? ? ? ? mc10[3] ? ? ? ? ? ? ? ? mc10[4] ? ? ? ? ? ? ? ? mc10[5] id-20 id-19 id-18 rtr ide ? id-17 id-16 mc10[6] id-28 id-27 id-26 id- 25 id-24 id-23 id-22 id-21 appendix rev. 7.00 sep. 11, 2009 page 537 of 566 rej09b0211-0700 register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module mc10[7] id-7 id-6 id-5 id-4 id-3 id-2 id-1 id-0 hcan mc10[8] id-15 id-14 id-13 id-12 id-11 id-10 id-9 id-8 mc11[1] ? ? ? ? dlc3 dlc2 dlc1 dlc0 mc11[2] ? ? ? ? ? ? ? ? mc11[3] ? ? ? ? ? ? ? ? mc11[4] ? ? ? ? ? ? ? ? mc11[5] id-20 id-19 id-18 rtr ide ? id-17 id-16 mc11[6] id-28 id-27 id-26 id- 25 id-24 id-23 id-22 id-21 mc11[7] id-7 id-6 id-5 id-4 id-3 id-2 id-1 id-0 mc11[8] id-15 id-14 id-13 id-12 id-11 id-10 id-9 id-8 mc12[1] ? ? ? ? dlc3 dlc2 dlc1 dlc0 mc12[2] ? ? ? ? ? ? ? ? mc12[3] ? ? ? ? ? ? ? ? mc12[4] ? ? ? ? ? ? ? ? mc12[5] id-20 id-19 id-18 rtr ide ? id-17 id-16 mc12[6] id-28 id-27 id-26 id- 25 id-24 id-23 id-22 id-21 mc12[7] id-7 id-6 id-5 id-4 id-3 id-2 id-1 id-0 mc12[8] id-15 id-14 id-13 id-12 id-11 id-10 id-9 id-8 mc13[1] ? ? ? ? dlc3 dlc2 dlc1 dlc0 mc13[2] ? ? ? ? ? ? ? ? mc13[3] ? ? ? ? ? ? ? ? mc13[4] ? ? ? ? ? ? ? ? mc13[5] id-20 id-19 id-18 rtr ide ? id-17 id-16 mc13[6] id-28 id-27 id-26 id- 25 id-24 id-23 id-22 id-21 mc13[7] id-7 id-6 id-5 id-4 id-3 id-2 id-1 id-0 mc13[8] id-15 id-14 id-13 id-12 id-11 id-10 id-9 id-8 mc14[1] ? ? ? ? dlc3 dlc2 dlc1 dlc0 mc14[2] ? ? ? ? ? ? ? ? mc14[3] ? ? ? ? ? ? ? ? mc14[4] ? ? ? ? ? ? ? ? mc14[5] id-20 id-19 id-18 rtr ide ? id-17 id-16 mc14[6] id-28 id-27 id-26 id- 25 id-24 id-23 id-22 id-21 mc14[7] id-7 id-6 id-5 id-4 id-3 id-2 id-1 id-0 mc14[8] id-15 id-14 id-13 id-12 id-11 id-10 id-9 id-8 mc15[1] ? ? ? ? dlc3 dlc2 dlc1 dlc0 mc15[2] ? ? ? ? ? ? ? ? mc153] ? ? ? ? ? ? ? ? mc15[4] ? ? ? ? ? ? ? ? mc15[5] id-20 id-19 id-18 rtr ide ? id-17 id-16 mc15[6] id-28 id-27 id-26 id- 25 id-24 id-23 id-22 id-21 appendix rev. 7.00 sep. 11, 2009 page 538 of 566 rej09b0211-0700 register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module mc15[7] id-7 id-6 id-5 id-4 id-3 id-2 id-1 id-0 hcan mc15[8] id-15 id-14 id-13 id-12 id-11 id-10 id-9 id-8 md0[1] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md0[2] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md0[3] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md0[4] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md0[5] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md0[6] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md0[7] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md0[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md1[1] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md1[2] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md1[3] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md1[4] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md1[5] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md1[6] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md1[7] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md1[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md2[1] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md2[2] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md2[3] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md2[4] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md2[5] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md2[6] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md2[7] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md2[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md3[1] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md3[2] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md3[3] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md3[4] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md3[5] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md3[6] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md3[7] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md3[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md4[1] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md4[2] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md4[3] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md4[4] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md4[5] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md4[6] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 appendix rev. 7.00 sep. 11, 2009 page 539 of 566 rej09b0211-0700 register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module md4[7] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hcan md4[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md5[1] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md5[2] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md5[3] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md5[4] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md5[5] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md5[6] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md5[7] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md5[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md6[1] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md6[2] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md6[3] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md6[4] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md6[5] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md6[6] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md6[7] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md6[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md7[1] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md7[2] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md7[3] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md7[4] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md7[5] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md7[6] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md7[7] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md7[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md8[1] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md8[2] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md8[3] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md8[4] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md8[5] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md8[6] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md8[7] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md8[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md9[1] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md9[2] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md9[3] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md9[4] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md9[5] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md9[6] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 appendix rev. 7.00 sep. 11, 2009 page 540 of 566 rej09b0211-0700 register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module md9[7] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hcan md9[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md10[1] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md10[2] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md10[3] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md10[4] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md10[5] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md10[6] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md10[7] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md10[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md11[1] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md11[2] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md11[3] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md11[4] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md11[5] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md11[6] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md11[7] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md11[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md12[1] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md12[2] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md12[3] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md12[4] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md12[5] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md12[6] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md12[7] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md12[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md13[1] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md13[2] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md13[3] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md13[4] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md13[5] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md13[6] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md13[7] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md13[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md14[1] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md14[2] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md14[3] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md14[4] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md14[5] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md14[6] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 appendix rev. 7.00 sep. 11, 2009 page 541 of 566 rej09b0211-0700 register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module md14[7] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hcan md14[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md15[1] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md15[2] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md15[3] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md15[4] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md15[5] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md15[6] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md15[7] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md15[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hcanmon ? ? ? ? ? ? txd rxd tmdr ? ? ? ? olsn olsp md1 md0 mmt tcnr ? cst rpro ? ? ? tgien tgiem tsr tcfg ? ? ? ? ? tgfn tgfm bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 tcnt bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 tpdr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 tpbr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 tddr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mmtpc pwobe pwoae pvobe pvoae puobe puoae pcoe pcie bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 tbru * 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 tgruu bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 tgru bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 tgrud bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 tdcnt0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 tdcnt1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 tbru * 2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tbrv * 1 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 appendix rev. 7.00 sep. 11, 2009 page 542 of 566 rej09b0211-0700 register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 mmt tgrvu bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 tgrv bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 tgrvd bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 tdcnt2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 tdcnt3 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 tbrv * 2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 tbrw * 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 tgrwu bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 tgrw bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 tgrwd bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 tdcnt4 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 tdcnt5 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 tbrw * 2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 poe3f poe2f poe1f poe0f ? ? ? pie poe icsr poe3m1 poe3m0 poe2m1 poe2m0 poe1m1 poe1m0 poe0m1 poe0m0 poepc poe3e poe2e poe1e poe0e ? ? ? ? sbycr ssby sts2 sts1 sts0 ? ? ? ? system syscr macs ? intm1 intm 0 nmieg ? ? rame sckcr pstop ? ? ? stcs sck2 sck1 sck0 mdcr ? ? ? ? ? mds2 mds1 mds0 mstpcra mstpa7 mstpa6 mstpa5 mstpa4 mstpa3 mstpa2 mstpa1 mstpa0 mstpcrb mstpb7 mstpb6 mstpb5 mstpb4 mstpb3 mstpb2 mstpb1 mstpb0 mstpcrc mstpc7 mstpc6 mstpc5 mstpc4 mstpc3 mstpc2 mstpc1 mstpc0 lpwrcr ? ? ? ? ? ? stc1 stc0 appendix rev. 7.00 sep. 11, 2009 page 543 of 566 rej09b0211-0700 register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module ? ? ? ? ? ? ? ? pbc baa23 baa22 baa21 baa20 baa19 baa18 baa17 baa16 baa15 baa14 baa13 baa12 baa11 baa10 baa9 baa8 bara baa7 baa6 baa5 baa4 baa3 baa2 baa1 baa0 ? ? ? ? ? ? ? ? bab23 bab22 bab21 bab20 bab19 bab18 bab17 bab16 bab15 bab14 bab13 bab12 bab11 bab10 bab9 bab8 barb bab7 bab6 bab5 bab4 bab3 bab2 bab1 bab0 bcra cmfa cda bamra2 bamra1 bamra0 csela1 csela0 biea bcrb cmfb cdb bamrb2 bamrb1 bamrb0 cselb1 cselb0 bieb iscrh ? ? ? ? irq5scb irq5sca irq4scb irq4sca int iscrl irq3scb irq3sca irq2scb irq2sc a irq1scb irq1sca irq0scb irq0sca ier ? ? irq5e irq4e irq3e irq2e irq1e irq0e isr ? ? irq5f irq4f irq3f irq2f irq1f irq0f dtcera dtcea7 dtcea6 dtcea5 dtcea4 dtcea3 dtcea2 dtcea1 dtcea0 dtc dtcerb dtceb7 dtceb6 dtceb5 dtceb4 dtceb3 dtceb2 dtceb1 dtceb0 dtcerc dtcec7 dtcec6 dt cec5 dtcec4 dtcec3 dt cec2 dtcec1 dtcec0 dtcerd dtced7 dtced6 dt ced5 dtced4 dtced3 dt ced2 dtced1 dtced0 dtcere dtcee7 dtcee6 dtcee5 dtcee4 dtcee3 dtcee2 dtcee1 dtcee0 dtcerf dtcef7 dtcef6 dtcef5 dtcef4 dtcef3 dtcef2 dtcef1 dtcef0 dtcerg dtceg7 dtceg6 dt ceg5 dtceg4 dtceg3 dt ceg2 dtceg1 dtceg0 dtvecr swdte dtvec6 dtvec5 dtvec4 dtvec3 dtvec2 dtvec1 dtvec0 pcr g3cms1 g3cms0 g2cms1 g2cms0 g1cms1 g1cms0 g0cms1 g0cms0 ppg pmr g3inv g2inv ? ? g3nov g2nov ? ? nderh nder15 nder14 nder13 nder12 nder11 nder10 nder9 nder8 nderl nder7 nder6 nder5 nder4 nder3 nder2 nder1 nder0 podrh pod15 pod14 po d13 pod12 pod11 po d10 pod9 pod8 podrl pod7 pod6 po d5 pod4 pod3 po d2 pod1 pod0 ndrh ndr15 ndr14 ndr13 ndr12 ndr11 ndr10 ndr9 ndr8 ndrl ndr7 ndr6 ndr5 ndr4 ndr3 ndr2 ndr1 ndr0 ndrh ? ? ? ? ndr11 ndr10 ndr9 ndr8 ndrl ? ? ? ? ndr3 ndr2 ndr1 ndr0 p1ddr p17ddr p16ddr p15ddr p14ddr p 13ddr p12ddr p11ddr p10ddr port paddr ? ? ? ? pa3ddr pa2ddr pa1ddr pa0ddr pbddr pb7ddr pb6ddr pb5ddr pb4ddr pb3ddr pb2ddr pb1ddr pb0ddr pcddr pc7ddr pc6ddr pc5ddr pc4ddr pc3ddr pc2ddr pc1ddr pc0ddr pdddr pd7ddr pd6ddr pd5ddr pd4ddr pd3ddr pd2ddr pd1ddr pd0ddr pfddr pf7ddr pf6ddr pf5ddr pf4ddr pf3ddr pf2ddr pf1ddr pf0ddr papcr ? ? ? ? pa3pcr pa2pcr pa1pcr pa0pcr pbpcr pb7pcr pb6pcr pb5pcr pb4pcr pb3pcr pb2pcr pb1pcr pb0pcr appendix rev. 7.00 sep. 11, 2009 page 544 of 566 rej09b0211-0700 register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module pcpcr pc7pcr pc6pcr pc5pcr pc4pcr pc3pcr pc2pcr pc1pcr pc0pcr port pdpcr pd7pcr pd6pcr pd5pcr pd4pcr pd3pcr pd2pcr pd1pcr pd0pcr paodr ? ? ? ? pa3odr pa2odr pa1odr pa0odr pbodr pb7odr pb6odr pb5odr pb4odr pb3odr pb2odr pb1odr pb0odr pcodr pc7odr pc6odr pc5odr pc4odr pc3odr pc2odr pc1odr pc0odr tcr_3 cclr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tpu_3 tmdr_3 ? ? bfb bfa md3 md2 md1 md0 tiorh_3 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 tiorl_3 iod3 iod2 iod1 iod0 ioc3 ioc2 ioc1 ioc0 tier_3 ttge ? ? tciev tgied tgiec tgieb tgiea tsr_3 ? ? ? tcfv tgfd tgfc tgfb tgfa tcnth_3 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 tcntl_3 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tgrah_3 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 tgral_3 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tgrbh_3 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 tgrbl_3 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tgrch_3 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 tgrcl_3 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tgrdh_3 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 tgrdl_3 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tcr_4 ? cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tpu_4 tmdr_4 ? ? ? ? md3 md2 md1 md0 tior_4 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 tier_4 ttge ? tcieu tciev ? ? tgieb tgiea tsr_4 tcfd ? tcfu tcfv ? ? tgfb tgfa tcnth_4 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 tcntl_4 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tgrah_4 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 tgral_4 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tgrbh_4 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 tgrbl_4 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tcr_5 ? cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tpu_5 tmdr_5 ? ? ? ? md3 md2 md1 md0 tior_5 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 tier_5 ttge ? tcieu tciev ? ? tgieb tgiea tsr_5 tcfd ? tcfu tcfv ? ? tgfb tgfa tcnth_5 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 tcntl_5 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tgrah_5 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 appendix rev. 7.00 sep. 11, 2009 page 545 of 566 rej09b0211-0700 register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module tgral_5 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tpu_5 tgrbh_5 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 tgrbl_5 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tstr ? ? cst5 cst4 cst3 cst2 cst1 cst0 tpu common tsyr ? ? sync5 sync4 sync3 sync2 sync1 sync0 ipra ? ipr6 ipr5 ipr4 ? ipr2 ipr1 ipr0 int iprb ? ipr6 ipr5 ipr4 ? ipr2 ipr1 ipr0 iprc ? ipr6 ipr5 ipr4 ? ipr2 ipr1 ipr0 iprd ? ipr6 ipr5 ipr4 ? ipr2 ipr1 ipr0 ipre ? ipr6 ipr5 ipr4 ? ipr2 ipr1 ipr0 iprf ? ipr6 ipr5 ipr4 ? ipr2 ipr1 ipr0 iprg ? ipr6 ipr5 ipr4 ? ipr2 ipr1 ipr0 iprh ? ipr6 ipr5 ipr4 ? ipr2 ipr1 ipr0 iprj ? ipr6 ipr5 ipr4 ? ipr2 ipr1 ipr0 iprk ? ipr6 ipr5 ipr4 ? ipr2 ipr1 ipr0 iprm ? ipr6 ipr5 ipr4 ? ipr2 ipr1 ipr0 ramer ? ? ? ? rams ra m2 ram1 ram0 rom p1dr p17dr p16dr p15dr p14dr p 13dr p12dr p11dr p10dr port padr ? ? ? ? pa3dr pa2dr pa1dr pa0dr pbdr pb7dr pb6dr pb5dr pb4dr pb3dr pb2dr pb1dr pb0dr pcdr pc7dr pc6dr pc5dr pc4dr pc3dr pc2dr pc1dr pc0dr pddr pd7dr pd6dr pd5dr pd4dr pd3dr pd2dr pd1dr pd0dr pfdr pf7dr pf6dr pf5dr pf4dr pf3dr pf2dr pf1dr pf0dr tcr_0 cclr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tmdr_0 ? ? bfb bfa md3 md2 md1 md0 tiorh_0 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 tiorl_0 iod3 iod2 iod1 iod0 ioc3 ioc2 ioc1 ioc0 tier_0 ttge ? ? tciev tgied tgiec tgieb tgiea tsr_0 ? ? ? tcfv tgfd tgfc tgfb tgfa tcnth_0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 tcntl_0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tpu_0 tgrah_0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 tgral_0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tgrbh_0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 tgrbl_0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tgrch_0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 tgrcl_0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tgrdh_0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 tgrdl_0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 appendix rev. 7.00 sep. 11, 2009 page 546 of 566 rej09b0211-0700 register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module tcr_1 ? cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tpu_1 tmdr_1 ? ? ? ? md3 md2 md1 md0 tior_1 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 tier_1 ttge ? tcieu tciev ? ? tgieb tgiea tsr_1 tcfd ? tcfu tcfv ? ? tgfb tgfa tcnth_1 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 tcntl_1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tgrah_1 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 tgral_1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tgrbh_1 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 tgrbl_1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tcr_2 ? cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tpu_2 tmdr_2 ? ? ? ? md3 md2 md1 md0 tior_2 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 tier_2 ttge ? tcieu tciev ? ? tgieb tgiea tsr_2 tcfd ? tcfu tcfv ? ? tgfb tgfa bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 tcnth_2 tcntl_2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 tgrah_2 tgral_2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 tgrbh_2 tgrbl_2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tcsr ovf wt/ it tme ? ? cks2 cks1 cks0 wdt tcnt bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rstcsr wovf rste rsts ? ? ? ? ? smr_0 * 3 c/ a chr pe o/ e stop mp cks1 cks0 sci_0 (smr_0 * 4 ) (gm) (blk) (pe) (o/ e ) (bcp1) (bcp0) (cks1) (cks0) brr_0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 scr_0 tie rie te re mpie teie cke1 cke0 tdr_0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ssr_0 * 3 tdre rdrf orer fer per tend mpb mpbt (ssr_0 * 4 ) (tdre) (rdrf) (orer) (ers) (per) (tend) (mpb) (mpbt) rdr_0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 scmr_0 ? ? ? ? sdir sinv ? smif smr_1 * 3 c/ a chr pe o/ e stop mp cks1 cks0 sci_1 (smr_1 * 4 ) (gm) (blk) (pe) (o/ e ) (bcp1) (bcp0) (cks1) (cks0) brr_1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 scr_1 tie rie te re mpie teie cke1 cke0 tdr_1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ssr_1 * 3 tdre rdrf orer fer per tend mpb mpbt (ssr_1 * 4 ) (tdre) (rdrf) (orer) (ers) (per) (tend) (mpb) (mpbt) appendix rev. 7.00 sep. 11, 2009 page 547 of 566 rej09b0211-0700 register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module rdr_1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sci_1 scmr_1 ? ? ? ? sdir sinv ? smif smr_2 * 3 c/ a chr pe o/ e stop mp cks1 cks0 sci_2 (smr_2 * 4 ) (gm) (blk) (pe) (o/ e ) (bcp1) (bcp0) (cks1) (cks0) brr_2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 scr_2 tie rie te re mpie teie cke1 cke0 tdr_2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ssr_2 * 3 tdre rdrf orer fer per tend mpb mpbt (ssr_2 * 4 ) (tdre) (rdrf) (orer) (ers) (per) (tend) (mpb) (mpbt) rdr_2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 scmr_2 ? ? ? ? sdir sinv ? smif addrah ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 a/dc addral ad1 ad0 ? ? ? ? ? ? addrbh ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 addrbl ad1 ad0 ? ? ? ? ? ? addrch ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 addrcl ad1 ad0 ? ? ? ? ? ? addrdh ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 addrdl ad1 ad0 ? ? ? ? ? ? adcsr adf adie adst scan ch3 ch2 ch1 ch0 adcr trgs1 trgs0 ? ? cks1 cks0 ? ? flmcr1 fwe swe esu1 psu1 ev1 pv1 e1 p1 rom flmcr2 fler ? ? ? ? ? ? ? ebr1 eb7 eb6 eb5 eb4 eb3 eb2 eb1 eb0 ebr2 ? ? ? ? ? ? eb9 eb8 port1 p17 p16 p15 p14 p13 p12 p11 p10 port port4 p47 p46 p45 p44 p43 p42 p41 p40 port9 ? ? ? ? p93 p92 p91 p90 porta ? ? ? ? pa3 pa2 pa1 pa0 portb pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 portc pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 portd pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 portf pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 notes: 1. for buffer operation. 2. for free operation. 3. normal serial communication interface mode. 4. smart card interface mode. some bit functions of smr differ in normal serial communication interface mode and smart card interface mode. appendix rev. 7.00 sep. 11, 2009 page 548 of 566 rej09b0211-0700 a.3 register states in each operating mode register name reset high-speed medium-speed sleep module stop software standby hardware standby module mcr initialized ? ? ? initialized initialized initialized hcan gsr initialized ? ? ? initialized initialized initialized bcr initialized ? ? ? initialized initialized initialized mbcr initialized ? ? ? initialized initialized initialized txpr initialized ? ? ? initialized initialized initialized txcr initialized ? ? ? initialized initialized initialized txack initialized ? ? ? initialized initialized initialized aback initialized ? ? ? initialized initialized initialized rxpr initialized ? ? ? initialized initialized initialized rfpr initialized ? ? ? initialized initialized initialized irr initialized ? ? ? initialized initialized initialized mbimr initialized ? ? ? initialized initialized initialized imr initialized ? ? ? initialized initialized initialized rec initialized ? ? ? initialized initialized initialized tec initialized ? ? ? initialized initialized initialized umsr initialized ? ? ? initialized initialized initialized lafml initialized ? ? ? initialized initialized initialized lafmh initialized ? ? ? initialized initialized initialized mc0[1] initialized ? ? ? ? ? ? mc0[2] initialized ? ? ? ? ? ? mc0[3] initialized ? ? ? ? ? ? mc0[4] initialized ? ? ? ? ? ? mc0[5] initialized ? ? ? ? ? ? mc0[6] initialized ? ? ? ? ? ? mc0[7] initialized ? ? ? ? ? ? mc0[8] initialized ? ? ? ? ? ? mc1[1] initialized ? ? ? ? ? ? mc1[2] initialized ? ? ? ? ? ? mc1[3] initialized ? ? ? ? ? ? mc1[4] initialized ? ? ? ? ? ? mc1[5] initialized ? ? ? ? ? ? mc1[6] initialized ? ? ? ? ? ? mc1[7] initialized ? ? ? ? ? ? mc1[8] initialized ? ? ? ? ? ? mc2[1] initialized ? ? ? ? ? ? mc2[2] initialized ? ? ? ? ? ? mc2[3] initialized ? ? ? ? ? ? mc2[4] initialized ? ? ? ? ? ? mc2[5] initialized ? ? ? ? ? ? mc2[6] initialized ? ? ? ? ? ? mc2[7] initialized ? ? ? ? ? ? mc2[8] initialized ? ? ? ? ? ? mc3[1] initialized ? ? ? ? ? ? mc3[2] initialized ? ? ? ? ? ? mc3[3] initialized ? ? ? ? ? ? appendix rev. 7.00 sep. 11, 2009 page 549 of 566 rej09b0211-0700 register name reset high-speed medium-speed sleep module stop software standby hardware standby module mc3[4] initialized ? ? ? ? ? ? hcan mc3[5] initialized ? ? ? ? ? ? mc3[6] initialized ? ? ? ? ? ? mc3[7] initialized ? ? ? ? ? ? mc3[8] initialized ? ? ? ? ? ? mc4[1] initialized ? ? ? ? ? ? mc4[2] initialized ? ? ? ? ? ? mc4[3] initialized ? ? ? ? ? ? mc4[4] initialized ? ? ? ? ? ? mc4[5] initialized ? ? ? ? ? ? mc4[6] initialized ? ? ? ? ? ? mc4[7] initialized ? ? ? ? ? ? mc4[8] initialized ? ? ? ? ? ? mc5[1] initialized ? ? ? ? ? ? mc5[2] initialized ? ? ? ? ? ? mc5[3] initialized ? ? ? ? ? ? mc5[4] initialized ? ? ? ? ? ? mc5[5] initialized ? ? ? ? ? ? mc5[6] initialized ? ? ? ? ? ? mc5[7] initialized ? ? ? ? ? ? mc5[8] initialized ? ? ? ? ? ? mc6[1] initialized ? ? ? ? ? ? mc6[2] initialized ? ? ? ? ? ? mc6[3] initialized ? ? ? ? ? ? mc6[4] initialized ? ? ? ? ? ? mc6[5] initialized ? ? ? ? ? ? mc6[6] initialized ? ? ? ? ? ? mc6[7] initialized ? ? ? ? ? ? mc6[8] initialized ? ? ? ? ? ? mc7[1] initialized ? ? ? ? ? ? mc7[2] initialized ? ? ? ? ? ? mc7[3] initialized ? ? ? ? ? ? mc7[4] initialized ? ? ? ? ? ? mc7[5] initialized ? ? ? ? ? ? mc7[6] initialized ? ? ? ? ? ? mc7[7] initialized ? ? ? ? ? ? mc7[8] initialized ? ? ? ? ? ? mc8[1] initialized ? ? ? ? ? ? mc8[2] initialized ? ? ? ? ? ? mc8[3] initialized ? ? ? ? ? ? mc8[4] initialized ? ? ? ? ? ? mc8[5] initialized ? ? ? ? ? ? mc8[6] initialized ? ? ? ? ? ? mc8[7] initialized ? ? ? ? ? ? mc8[8] initialized ? ? ? ? ? ? mc9[1] initialized ? ? ? ? ? ? mc9[2] initialized ? ? ? ? ? ? mc9[3] initialized ? ? ? ? ? ? appendix rev. 7.00 sep. 11, 2009 page 550 of 566 rej09b0211-0700 register name reset high-speed medium-speed sleep module stop software standby hardware standby module mc9[4] initialized ? ? ? ? ? ? hcan mc9[5] initialized ? ? ? ? ? ? mc9[6] initialized ? ? ? ? ? ? mc9[7] initialized ? ? ? ? ? ? mc9[8] initialized ? ? ? ? ? ? mc10[1] initialized ? ? ? ? ? ? mc10[2] initialized ? ? ? ? ? ? mc10[3] initialized ? ? ? ? ? ? mc10[4] initialized ? ? ? ? ? ? mc10[5] initialized ? ? ? ? ? ? mc10[6] initialized ? ? ? ? ? ? mc10[7] initialized ? ? ? ? ? ? mc10[8] initialized ? ? ? ? ? ? mc11[1] initialized ? ? ? ? ? ? mc11[2] initialized ? ? ? ? ? ? mc11[3] initialized ? ? ? ? ? ? mc11[4] initialized ? ? ? ? ? ? mc11[5] initialized ? ? ? ? ? ? mc11[6] initialized ? ? ? ? ? ? mc11[7] initialized ? ? ? ? ? ? mc11[8] initialized ? ? ? ? ? ? mc12[1] initialized ? ? ? ? ? ? mc12[2] initialized ? ? ? ? ? ? mc12[3] initialized ? ? ? ? ? ? mc12[4] initialized ? ? ? ? ? ? mc12[5] initialized ? ? ? ? ? ? mc12[6] initialized ? ? ? ? ? ? mc12[7] initialized ? ? ? ? ? ? mc12[8] initialized ? ? ? ? ? ? mc13[1] initialized ? ? ? ? ? ? mc13[2] initialized ? ? ? ? ? ? mc13[3] initialized ? ? ? ? ? ? mc13[4] initialized ? ? ? ? ? ? mc13[5] initialized ? ? ? ? ? ? mc13[6] initialized ? ? ? ? ? ? mc13[7] initialized ? ? ? ? ? ? mc13[8] initialized ? ? ? ? ? ? mc14[1] initialized ? ? ? ? ? ? mc14[2] initialized ? ? ? ? ? ? mc14[3] initialized ? ? ? ? ? ? mc14[4] initialized ? ? ? ? ? ? mc14[5] initialized ? ? ? ? ? ? mc14[6] initialized ? ? ? ? ? ? mc14[7] initialized ? ? ? ? ? ? mc14[8] initialized ? ? ? ? ? ? mc15[1] initialized ? ? ? ? ? ? mc15[2] initialized ? ? ? ? ? ? mc15[3] initialized ? ? ? ? ? ? appendix rev. 7.00 sep. 11, 2009 page 551 of 566 rej09b0211-0700 register name reset high-speed medium-speed sleep module stop software standby hardware standby module mc15[4] initialized ? ? ? ? ? ? hcan mc15[5] initialized ? ? ? ? ? ? mc15[6] initialized ? ? ? ? ? ? mc15[7] initialized ? ? ? ? ? ? mc15[8] initialized ? ? ? ? ? ? md0[1] initialized ? ? ? ? ? ? md0[2] initialized ? ? ? ? ? ? md0[3] initialized ? ? ? ? ? ? md0[4] initialized ? ? ? ? ? ? md0[5] initialized ? ? ? ? ? ? md0[6] initialized ? ? ? ? ? ? md0[7] initialized ? ? ? ? ? ? md0[8] initialized ? ? ? ? ? ? md1[1] initialized ? ? ? ? ? ? md1[2] initialized ? ? ? ? ? ? md1[3] initialized ? ? ? ? ? ? md1[4] initialized ? ? ? ? ? ? md1[5] initialized ? ? ? ? ? ? md1[6] initialized ? ? ? ? ? ? md1[7] initialized ? ? ? ? ? ? md1[8] initialized ? ? ? ? ? ? md2[1] initialized ? ? ? ? ? ? md2[2] initialized ? ? ? ? ? ? md2[3] initialized ? ? ? ? ? ? md2[4] initialized ? ? ? ? ? ? md2[5] initialized ? ? ? ? ? ? md2[6] initialized ? ? ? ? ? ? md2[7] initialized ? ? ? ? ? ? md2[8] initialized ? ? ? ? ? ? md3[1] initialized ? ? ? ? ? ? md3[2] initialized ? ? ? ? ? ? md3[3] initialized ? ? ? ? ? ? md3[4] initialized ? ? ? ? ? ? md3[5] initialized ? ? ? ? ? ? md3[6] initialized ? ? ? ? ? ? md3[7] initialized ? ? ? ? ? ? md3[8] initialized ? ? ? ? ? ? md4[1] initialized ? ? ? ? ? ? md4[2] initialized ? ? ? ? ? ? md4[3] initialized ? ? ? ? ? ? md4[4] initialized ? ? ? ? ? ? md4[5] initialized ? ? ? ? ? ? md4[6] initialized ? ? ? ? ? ? md4[7] initialized ? ? ? ? ? ? md4[8] initialized ? ? ? ? ? ? md5[1] initialized ? ? ? ? ? ? md5[2] initialized ? ? ? ? ? ? md5[3] initialized ? ? ? ? ? ? appendix rev. 7.00 sep. 11, 2009 page 552 of 566 rej09b0211-0700 register name reset high-speed medium-speed sleep module stop software standby hardware standby module md5[4] initialized ? ? ? ? ? ? hcan md5[5] initialized ? ? ? ? ? ? md5[6] initialized ? ? ? ? ? ? md5[7] initialized ? ? ? ? ? ? md5[8] initialized ? ? ? ? ? ? md6[1] initialized ? ? ? ? ? ? md6[2] initialized ? ? ? ? ? ? md6[3] initialized ? ? ? ? ? ? md6[4] initialized ? ? ? ? ? ? md6[5] initialized ? ? ? ? ? ? md6[6] initialized ? ? ? ? ? ? md6[7] initialized ? ? ? ? ? ? md6[8] initialized ? ? ? ? ? ? md7[1] initialized ? ? ? ? ? ? md7[2] initialized ? ? ? ? ? ? md7[3] initialized ? ? ? ? ? ? md7[4] initialized ? ? ? ? ? ? md7[5] initialized ? ? ? ? ? ? md7[6] initialized ? ? ? ? ? ? md7[7] initialized ? ? ? ? ? ? md7[8] initialized ? ? ? ? ? ? md8[1] initialized ? ? ? ? ? ? md8[2] initialized ? ? ? ? ? ? md8[3] initialized ? ? ? ? ? ? md8[4] initialized ? ? ? ? ? ? md8[5] initialized ? ? ? ? ? ? md8[6] initialized ? ? ? ? ? ? md8[7] initialized ? ? ? ? ? ? md8[8] initialized ? ? ? ? ? ? md9[1] initialized ? ? ? ? ? ? md9[2] initialized ? ? ? ? ? ? md9[3] initialized ? ? ? ? ? ? md9[4] initialized ? ? ? ? ? ? md9[5] initialized ? ? ? ? ? ? md9[6] initialized ? ? ? ? ? ? md9[7] initialized ? ? ? ? ? ? md9[8] initialized ? ? ? ? ? ? md10[1] initialized ? ? ? ? ? ? md10[2] initialized ? ? ? ? ? ? md10[3] initialized ? ? ? ? ? ? md10[4] initialized ? ? ? ? ? ? md10[5] initialized ? ? ? ? ? ? md10[6] initialized ? ? ? ? ? ? md10[7] initialized ? ? ? ? ? ? md10[8] initialized ? ? ? ? ? ? md11[1] initialized ? ? ? ? ? ? md11[2] initialized ? ? ? ? ? ? md11[3] initialized ? ? ? ? ? ? appendix rev. 7.00 sep. 11, 2009 page 553 of 566 rej09b0211-0700 register name reset high-speed medium-speed sleep module stop software standby hardware standby module md11[4] initialized ? ? ? ? ? ? hcan md11[5] initialized ? ? ? ? ? ? md11[6] initialized ? ? ? ? ? ? md11[7] initialized ? ? ? ? ? ? md11[8] initialized ? ? ? ? ? ? md12[1] initialized ? ? ? ? ? ? md12[2] initialized ? ? ? ? ? ? md12[3] initialized ? ? ? ? ? ? md12[4] initialized ? ? ? ? ? ? md12[5] initialized ? ? ? ? ? ? md12[6] initialized ? ? ? ? ? ? md12[7] initialized ? ? ? ? ? ? md12[8] initialized ? ? ? ? ? ? md13[1] initialized ? ? ? ? ? ? md13[2] initialized ? ? ? ? ? ? md13[3] initialized ? ? ? ? ? ? md13[4] initialized ? ? ? ? ? ? md13[5] initialized ? ? ? ? ? ? md13[6] initialized ? ? ? ? ? ? md13[7] initialized ? ? ? ? ? ? md13[8] initialized ? ? ? ? ? ? md14[1] initialized ? ? ? ? ? ? md14[2] initialized ? ? ? ? ? ? md14[3] initialized ? ? ? ? ? ? md14[4] initialized ? ? ? ? ? ? md14[5] initialized ? ? ? ? ? ? md14[6] initialized ? ? ? ? ? ? md14[7] initialized ? ? ? ? ? ? md14[8] initialized ? ? ? ? ? ? md15[1] initialized ? ? ? ? ? ? md15[2] initialized ? ? ? ? ? ? md15[3] initialized ? ? ? ? ? ? md15[4] initialized ? ? ? ? ? ? md15[5] initialized ? ? ? ? ? ? md15[6] initialized ? ? ? ? ? ? md15[7] initialized ? ? ? ? ? ? md15[8] initialized ? ? ? ? ? ? hcanmon initialized ? ? ? initialized initialized initialized tmdr initialized ? ? ? ? ? initialized mmt tcnr initialized ? ? ? ? ? initialized tsr initialized ? ? ? ? ? initialized tcnt initialized ? ? ? ? ? initialized tpdr initialized ? ? ? ? ? initialized tpbr initialized ? ? ? ? ? initialized tddr initialized ? ? ? ? ? initialized mmtpc initialized ? ? ? ? ? initialized tbru initialized ? ? ? ? ? initialized tgruu initialized ? ? ? ? ? initialized appendix rev. 7.00 sep. 11, 2009 page 554 of 566 rej09b0211-0700 register name reset high-speed medium-speed sleep module stop software standby hardware standby module tgru initialized ? ? ? ? ? initialized mmt tgrud initialized ? ? ? ? ? initialized tdcnt0 initialized ? ? ? ? ? initialized tdcnt1 initialized ? ? ? ? ? initialized tbru initialized ? ? ? ? ? initialized tbrv initialized ? ? ? ? ? initialized tgrvu initialized ? ? ? ? ? initialized tgrv initialized ? ? ? ? ? initialized tgrvd initialized ? ? ? ? ? initialized tdcnt2 initialized ? ? ? ? ? initialized tdcnt3 initialized ? ? ? ? ? initialized tbrv initialized ? ? ? ? ? initialized tbrw initialized ? ? ? ? ? initialized tgrwu initialized ? ? ? ? ? initialized tgrw initialized ? ? ? ? ? initialized tgrwd initialized ? ? ? ? ? initialized tdcnt4 initialized ? ? ? ? ? initialized tdcnt5 initialized ? ? ? ? ? initialized tbrw initialized ? ? ? ? ? initialized icsr initialized ? ? ? ? ? initialized poe poepc initialized ? ? ? ? ? initialized sbycr initialized ? ? ? ? ? initialized system syscr initialized ? ? ? ? ? initialized sckcr initialized ? ? ? ? ? initialized mdcr initialized ? ? ? ? ? initialized mstpcra initialized ? ? ? ? ? initialized mstpcrb initialized ? ? ? ? ? initialized mstpcrc initialized ? ? ? ? ? initialized lpwrcr initialized ? ? ? ? ? initialized bara initialized ? ? ? ? ? initialized pbc barb initialized ? ? ? ? ? initialized bcra initialized ? ? ? ? ? initialized bcrb initialized ? ? ? ? ? initialized iscrh initialized ? ? ? ? ? initialized int iscrl initialized ? ? ? ? ? initialized ier initialized ? ? ? ? ? initialized isr initialized ? ? ? ? ? initialized dtcera initialized ? ? ? ? ? initialized dtc dtcerb initialized ? ? ? ? ? initialized dtcerc initialized ? ? ? ? ? initialized dtcerd initialized ? ? ? ? ? initialized dtcere initialized ? ? ? ? ? initialized dtcerf initialized ? ? ? ? ? initialized dtcerg initialized ? ? ? ? ? initialized dtvecr initialized ? ? ? ? ? initialized pcr initialized ? ? ? ? ? initialized ppg pmr initialized ? ? ? ? ? initialized nderh initialized ? ? ? ? ? initialized appendix rev. 7.00 sep. 11, 2009 page 555 of 566 rej09b0211-0700 register name reset high-speed medium-speed sleep module stop software standby hardware standby module nderl initialized ? ? ? ? ? initialized ppg podrh initialized ? ? ? ? ? initialized podrl initialized ? ? ? ? ? initialized ndrh initialized ? ? ? ? ? initialized ndrl initialized ? ? ? ? ? initialized ndrh initialized ? ? ? ? ? initialized ndrl initialized ? ? ? ? ? initialized p1ddr initialized ? ? ? ? ? initialized port paddr initialized ? ? ? ? ? initialized pbddr initialized ? ? ? ? ? initialized pcddr initialized ? ? ? ? ? initialized pdddr initialized ? ? ? ? ? initialized pfddr initialized ? ? ? ? ? initialized papcr initialized ? ? ? ? ? initialized pbpcr initialized ? ? ? ? ? initialized pcpcr initialized ? ? ? ? ? initialized pdpcr initialized ? ? ? ? ? initialized paodr initialized ? ? ? ? ? initialized pbodr initialized ? ? ? ? ? initialized pcodr initialized ? ? ? ? ? initialized tcr_3 initialized ? ? ? ? ? initialized tpu_3 tmdr_3 initialized ? ? ? ? ? initialized tiorh_3 initialized ? ? ? ? ? initialized tiorl_3 initialized ? ? ? ? ? initialized tier_3 initialized ? ? ? ? ? initialized tsr_3 initialized ? ? ? ? ? initialized tcnth_3 initialized ? ? ? ? ? initialized tcntl_3 initialized ? ? ? ? ? initialized tgrah_3 initialized ? ? ? ? ? initialized tgral_3 initialized ? ? ? ? ? initialized tgrbh_3 initialized ? ? ? ? ? initialized tgrbl_3 initialized ? ? ? ? ? initialized tgrch_3 initialized ? ? ? ? ? initialized tgrcl_3 initialized ? ? ? ? ? initialized tgrdh_3 initialized ? ? ? ? ? initialized tgrdl_3 initialized ? ? ? ? ? initialized tcr_4 initialized ? ? ? ? ? initialized tpu_4 tmdr_4 initialized ? ? ? ? ? initialized tior_4 initialized ? ? ? ? ? initialized tier_4 initialized ? ? ? ? ? initialized tsr_4 initialized ? ? ? ? ? initialized tcnth_4 initialized ? ? ? ? ? initialized tcntl_4 initialized ? ? ? ? ? initialized tgrah_4 initialized ? ? ? ? ? initialized tgral_4 initialized ? ? ? ? ? initialized tgrbh_4 initialized ? ? ? ? ? initialized tgrbl_4 initialized ? ? ? ? ? initialized appendix rev. 7.00 sep. 11, 2009 page 556 of 566 rej09b0211-0700 register name reset high-speed medium-speed sleep module stop software standby hardware standby module tcr_5 initialized ? ? ? ? ? initialized tpu_5 tmdr_5 initialized ? ? ? ? ? initialized tior_5 initialized ? ? ? ? ? initialized tier_5 initialized ? ? ? ? ? initialized tsr_5 initialized ? ? ? ? ? initialized tcnth_5 initialized ? ? ? ? ? initialized tcntl_5 initialized ? ? ? ? ? initialized tgrah_5 initialized ? ? ? ? ? initialized tgral_5 initialized ? ? ? ? ? initialized tgrbh_5 initialized ? ? ? ? ? initialized tgrbl_5 initialized ? ? ? ? ? initialized tstr initialized ? ? ? ? ? initialized tpu common tsyr initialized ? ? ? ? ? initialized ipra initialized ? ? ? ? ? initialized int iprb initialized ? ? ? ? ? initialized iprc initialized ? ? ? ? ? initialized iprd initialized ? ? ? ? ? initialized ipre initialized ? ? ? ? ? initialized iprf initialized ? ? ? ? ? initialized iprg initialized ? ? ? ? ? initialized iprh initialized ? ? ? ? ? initialized iprj initialized ? ? ? ? ? initialized iprk initialized ? ? ? ? ? initialized iprm initialized ? ? ? ? ? initialized ramer initialized ? ? ? ? ? initialized rom p1dr initialized ? ? ? ? ? initialized port padr initialized ? ? ? ? ? initialized pbdr initialized ? ? ? ? ? initialized pcdr initialized ? ? ? ? ? initialized pddr initialized ? ? ? ? ? initialized pfdr initialized ? ? ? ? ? initialized tcr_0 initialized ? ? ? ? ? initialized tpu_0 tmdr_0 initialized ? ? ? ? ? initialized tiorh_0 initialized ? ? ? ? ? initialized tiorl_0 initialized ? ? ? ? ? initialized tier_0 initialized ? ? ? ? ? initialized tsr_0 initialized ? ? ? ? ? initialized tcnth_0 initialized ? ? ? ? ? initialized tcntl_0 initialized ? ? ? ? ? initialized tgrah_0 initialized ? ? ? ? ? initialized tgral_0 initialized ? ? ? ? ? initialized tgrbh_0 initialized ? ? ? ? ? initialized tgrbl_0 initialized ? ? ? ? ? initialized tgrch_0 initialized ? ? ? ? ? initialized tgrcl_0 initialized ? ? ? ? ? initialized tgrdh_0 initialized ? ? ? ? ? initialized tgrdl_0 initialized ? ? ? ? ? initialized appendix rev. 7.00 sep. 11, 2009 page 557 of 566 rej09b0211-0700 register name reset high-speed medium-speed sleep module stop software standby hardware standby module tcr_1 initialized ? ? ? ? ? initialized tpu_1 tmdr_1 initialized ? ? ? ? ? initialized tior_1 initialized ? ? ? ? ? initialized tier_1 initialized ? ? ? ? ? initialized tsr_1 initialized ? ? ? ? ? initialized tcnth_1 initialized ? ? ? ? ? initialized tcntl_1 initialized ? ? ? ? ? initialized tgrah_1 initialized ? ? ? ? ? initialized tgral_1 initialized ? ? ? ? ? initialized tgrbh_1 initialized ? ? ? ? ? initialized tgrbl_1 initialized ? ? ? ? ? initialized tcr_2 initialized ? ? ? ? ? initialized tpu_2 tmdr_2 initialized ? ? ? ? ? initialized tior_2 initialized ? ? ? ? ? initialized tier_2 initialized ? ? ? ? ? initialized tsr_2 initialized ? ? ? ? ? initialized tcnth_2 initialized ? ? ? ? ? initialized tcntl_2 initialized ? ? ? ? ? initialized tgrah_2 initialized ? ? ? ? ? initialized tgral_2 initialized ? ? ? ? ? initialized tgrbh_2 initialized ? ? ? ? ? initialized tgrbl_2 initialized ? ? ? ? ? initialized tcsr initialized ? ? ? ? ? initialized wdt tcnt initialized ? ? ? ? ? initialized rstcsr initialized ? ? ? ? ? initialized smr_0 initialized ? ? ? initialized initialized initialized sci_0 brr_0 initialized ? ? ? initialized initialized initialized scr_0 initialized ? ? ? initialized initialized initialized tdr_0 initialized ? ? ? initialized initialized initialized ssr_0 initialized ? ? ? initialized initialized initialized rdr_0 initialized ? ? ? initialized initialized initialized scmr_0 initialized ? ? ? initialized initialized initialized smr_1 initialized ? ? ? initialized initialized initialized sci_1 brr_1 initialized ? ? ? initialized initialized initialized scr_1 initialized ? ? ? initialized initialized initialized tdr_1 initialized ? ? ? initialized initialized initialized ssr_1 initialized ? ? ? initialized initialized initialized rdr_1 initialized ? ? ? initialized initialized initialized scmr_1 initialized ? ? ? initialized initialized initialized smr_2 initialized ? ? ? initialized initialized initialized sci_2 brr_2 initialized ? ? ? initialized initialized initialized scr_2 initialized ? ? ? initialized initialized initialized tdr_2 initialized ? ? ? initialized initialized initialized ssr_2 initialized ? ? ? initialized initialized initialized rdr_2 initialized ? ? ? initialized initialized initialized scmr_2 initialized ? ? ? initialized initialized initialized appendix rev. 7.00 sep. 11, 2009 page 558 of 566 rej09b0211-0700 register name reset high-speed medium-speed sleep module stop software standby hardware standby module addrah initialized ? ? ? initialized initialized initialized a/dc addral initialized ? ? ? initialized initialized initialized addrbh initialized ? ? ? initialized initialized initialized addrbl initialized ? ? ? initialized initialized initialized addrch initialized ? ? ? initialized initialized initialized addrcl initialized ? ? ? initialized initialized initialized addrdh initialized ? ? ? initialized initialized initialized addrdl initialized ? ? ? initialized initialized initialized adcsr initialized ? ? ? initialized initialized initialized adcr initialized ? ? ? initialized initialized initialized flmcr1 initialized ? ? ? ? ? initialized rom flmcr2 initialized ? ? ? ? ? initialized ebr1 initialized ? ? ? ? ? initialized ebr2 initialized ? ? ? ? ? initialized port1 initialized ? ? ? ? ? initialized port port4 initialized ? ? ? ? ? initialized port9 initialized ? ? ? ? ? initialized porta initialized ? ? ? ? ? initialized portb initialized ? ? ? ? ? initialized portc initialized ? ? ? ? ? initialized portd initialized ? ? ? ? ? initialized portf initialized ? ? ? ? ? initialized note: ? is not initialized. appendix rev. 7.00 sep. 11, 2009 page 559 of 566 rej09b0211-0700 b. i/o port states in each pin state port name mcu operating mode reset hardware standby mode software standby mode program execution state sleep mode port 1 7 t t keep i/o port port 4 7 t t t input port port 9 7 t t t input port port a 7 t t keep i/o port port b 7 t t keep i/o port port c 7 t t keep i/o port port d 7 t t keep i/o port pf7 7 t t [ddr = 0] t [ddr = 1] h [ddr = 0] t [ddr = 1] clock output pf6 pf5 pf4 pf3 pf2 pf1 pf0 7 t t keep i/o port htxd 7 h t h output hrxd 7 input t t input legend: h: high level t: high impedance keep: input port becomes high-impedance, output port retains state appendix rev. 7.00 sep. 11, 2009 page 560 of 566 rej09b0211-0700 c. product code lineup product type model package (package code) h8s/2612 f-ztat version standard product hd64f2612 mask rom version standard product hd6432612 standard product hd6432611 h8s/2614 mask rom version standard product hd6432614 qfp-80 (fp-80q/fp-80qv) h8s/2616 mask rom version standard product hd6432616 appendix rev. 7.00 sep. 11, 2009 page 561 of 566 rej09b0211-0700 d. package dimensions the package dimension that is shown in the renesas semiconductor package data book has priority. note) 1. dimensions" * 1"and" * 2" do not include mold flash 2. dimension" * 3"does not include trim offset. prqp0080jd-a p-qfp80-14x14-0.65 0.83 14 1.6 0.10 0 8 0.65 0.12 0.17 0.22 0.24 0.32 0.40 0.00 0.10 0.25 3.05 17.0 17.2 17.4 2.70 14 0.30 0.15 0.6 0.8 1.0 0.12 17.4 17.2 17.0 0.83 reference symbol dimension in millimeters min nom max previous code jeita package code renesas code fp-80q/fp-80qv 1.2g mass[typ.] 1 e d 1 1 p 1 e d 2 l z z y x c b b a h a e d a c e e l h * 1 * 2 * 3 m x y 40 41 60 61 21 20 f 1 80 d e d e p z z b h d h e detail f 1 1 2 c l a l aa p 1 1 terminal cross section b c b c figure d.1 fp-80q, fp-80qv package dimensions appendix rev. 7.00 sep. 11, 2009 page 562 of 566 rej09b0211-0700 index rev. 7.00 sep. 11, 2009 page 563 of 566 rej09b0211-0700 index 16-bit timer pulse unit (tpu)............... 159 buffer operation.............................. 205 cascaded operation ......................... 208 free-running count operation........... 198 input capt ure ................................... 201 periodic count operation .................. 198 phase counting mode...................... 216 pwm modes.................................... 211 synchronous operation ................... 203 toggle out put .................................... 199 waveform output by compare match ......................................................... 199 a/d converter ........................................ 435 a/d converter activation................ 225 a/d trigger input ............................. 157 conversion time ............................. 443 external trigger............................... 445 scan mode ....................................... 442 single mode..................................... 442 address map............................................. 55 address space........................................... 20 addressing modes .................................... 42 absolute address............................... 43 immediate .......................................... 44 memory indirect ................................ 44 program-counter relative ................. 44 register direct ................................... 42 register indirect ................................ 42 register indirect with displacement.. 43 register indirect with post-increment43 register indirect with pre-decrement 43 bcc ...................................................... 30, 38 bit rate ................................................... 415 break address ...................................... 89, 92 break conditions........................................ 92 bus arbitration ....................................... 100 bus cycle ................................................... 97 bus masters ............................................ 100 clock pulse generator ............................477 condition field .........................................41 condition-code register (ccr) ...............24 cpu operating modes ..............................16 advanced mode .................................17 normal mode.....................................16 data directi on register..............................127 data register.............................................127 data transfer controller .........................103 activation by software ....................123 block transfer mode .......................117 chain transfer .........................119, 124 dtc vector table............................110 normal mode...........................115, 123 register information ........................110 repeat mode ....................................116 software activation ...........................120 software activation .........................125 vector number for the software activation interrupt ...........................109 effective address................................42, 45 effective address extension .....................41 exception handling...................................57 interrupts............................................62 reset exception handling..................59 stack status........................................64 traces.................................................62 trap instruction..................................63 exception handling v ector table.............58 extended control register (exr).............23 flash memory boot m ode .......................................464 emulation.........................................468 erase/erase-verify...........................472 erasing units .....................................458 power-down states..........................475 program/program-verify .................470 programming units ...........................458 index rev. 7.00 sep. 11, 2009 page 564 of 566 rej09b0211-0700 programming/erasing in user program mode................................................ 466 general registers...................................... 22 hcan............................................... 99, 383 11 consecutive recessive bits ........... 412 arbitration field ....................... 419, 422 buffer segment ................................. 415 configuratio n mode......................... 412 control fi eld..................................... 419 data field ......................................... 419 data frame ....................................... 422 dtc interface.................................. 429 hcan halt mode............................ 427 hcan sleep mode.......................... 424 mailbox............................ 409, 411, 417 message control (mc0 to mc15)... 409 message data (md0 to md15) ....... 411 message transmission cancellation.. 419 message transmission method ....... 417 remote frame .................................. 423 remote transmission request bit ....... 423 unread message overwrite............... 423 input pull- up mos.................................. 127 instruction set........................................... 30 arithmetic operations instructions.... 33 bit manipulation instructions ............ 36 block data transfer instructions....... 40 branch instructions............................ 38 data transfer instructions ................. 32 logic operations instructions............ 35 shift instructions................................ 35 system control instructions .............. 39 interrupt control modes ........................... 79 interrupt controller................................... 67 interrupt exception handling vector table .................................................................. 76 interrupt mask bit..................................... 25 interrupt mask level .................................. 23 interrupt priority register (ipr)................. 67 interrupts adi .................................................. 445 ers0/ovr0..................................... 428 nmi.............................................. 75, 87 rm0 ................................................. 428 rm1 ................................................. 428 sle0 ................................................ 428 swdtend...................................... 120 tciu_1 ............................................ 224 tciu_2 ............................................ 224 tciu_4 ............................................ 224 tciu_5 ............................................ 224 tciv_0 ............................................ 224 tciv_1 ............................................ 224 tciv_2 ............................................ 224 tciv_3 ............................................ 224 tciv_4 ............................................ 224 tciv_5 ............................................ 224 tgia_0............................................ 224 tgia_1............................................ 224 tgia_2............................................ 224 tgia_3............................................ 224 tgia_4............................................ 224 tgia_5............................................ 224 tgib_0 ............................................ 224 tgib_1 ............................................ 224 tgib_2 ............................................ 224 tgib_3 ............................................ 224 tgib_4 ............................................ 224 tgib_5 ............................................ 224 tgic_0 ............................................ 224 tgic_3 ............................................ 224 tgid_0............................................ 224 tgid_3............................................ 224 tgimn ............................................ 263 tginn............................................. 263 wovi .............................................. 309 mac instruction ....................................... 53 memory cycle............................................ 97 mmt....................................................... 100 index rev. 7.00 sep. 11, 2009 page 565 of 566 rej09b0211-0700 motor management timer...................... 245 buffer registers................................. 251 dead time.................................. 251, 258 non-overlap time.............................. 251 multiply-accumulate register (mac)..... 26 on-board programming ......................... 463 open-drain control register...................... 127 operating mode selection ........................ 51 operation field ......................................... 41 pc break controller.................................. 89 pin arrangement......................................... 5 pll circuit ............................................. 483 port register............................................. 127 program counter (pc) .............................. 23 program/erase protection ....................... 474 programmable pulse generator .............. 281 non-overlapping pulse output ....... 295 output trig ger ................................... 289 programmer mode .................................. 475 register addr.............................................. 438 ipr................................... 530, 545, 556 register field............................................ 41 registers aback ................... 395, 519, 534, 548 adcr ...................... 441, 533, 547, 558 adcsr.................... 439, 533, 547, 558 addr.............................. 533, 547, 558 bara ........................ 90, 5 28, 543, 554 barb ........................ 91, 5 28, 543, 554 bcr ......................... 389, 519, 534, 548 bcra ........................ 91, 5 28, 543, 554 bcrb ........................ 92, 5 28, 543, 554 brr ......................... 331, 532, 546, 557 cra ................................................. 107 crb ................................................. 108 dar................................................. 107 dtcer .................... 108, 528, 543, 554 dtvecr ................. 109, 529, 543, 554 ebr1 ....................... 461, 533, 547, 558 ebr2........................ 462, 533, 547, 558 flmcr1.................. 459, 533, 547, 558 flmcr2.................. 461, 533, 547, 558 gsr.......................... 387, 519, 534, 548 hcanmon............. 411, 527, 541, 553 icsr......................... 275, 528, 542, 554 ier ............................. 71, 5 28, 543, 554 imr.......................... 403, 519, 534, 548 ipr .....................................................70 irr........................... 398, 519, 534, 548 iscr........................... 71, 5 28, 543, 554 isr ............................. 74, 5 28, 543, 554 lafmh ................... 406, 519, 534, 548 lafml.................... 406, 519, 534, 548 lpwrcr ................. 479, 528, 542, 554 mbcr...................... 391, 519, 534, 548 mbimr.................... 402, 519, 534, 548 mc ........................... 409, 519, 534, 548 mcr......................... 386, 519, 534, 548 md ........................... 411, 523, 538, 551 mdcr........................ 52, 528, 542, 554 mmtpc ................... 252, 527, 541, 553 mra ................................................106 mrb.................................................107 mstpcr.................. 492, 528, 542, 554 nder....................... 284, 529, 543, 554 ndr ......................... 286, 529, 543, 555 p1ddr..................... 130, 529, 543, 555 p1dr........................ 131, 531, 545, 556 paddr .................... 137, 529, 543, 555 padr....................... 138, 531, 545, 556 paodr .................... 139, 529, 544, 555 papcr..................... 139, 529, 543, 555 pbddr .................... 141, 529, 543, 555 pbdr ....................... 142, 531, 545, 556 pbodr .................... 143, 529, 544, 555 pbpcr ..................... 143, 529, 543, 555 pcddr .................... 147, 529, 543, 555 pcdr ....................... 148, 531, 545, 556 pcodr .................... 149, 529, 544, 555 index rev. 7.00 sep. 11, 2009 page 566 of 566 rej09b0211-0700 pcpcr..................... 149, 529, 544, 555 pcr ......................... 289, 529, 543, 554 pdddr.................... 152, 529, 543, 555 pddr ...................... 153, 531, 545, 556 pdpcr .................... 154, 529, 544, 555 pfddr .................... 155, 529, 543, 555 pfdr ....................... 156, 531, 545, 556 pmr......................... 290, 529, 543, 554 podr ...................... 285, 529, 543, 555 poepc..................... 278, 528, 542, 554 port1..................... 131, 533, 547, 558 port4..................... 135, 533, 547, 558 port9..................... 136, 533, 547, 558 porta .................... 138, 533, 547, 558 portb .................... 142, 533, 547, 558 portc .................... 148, 533, 547, 558 portd .................... 153, 533, 547, 558 portf..................... 156, 533, 547, 558 ramer................... 462, 531, 545, 556 rdr......................... 316, 532, 546, 557 rec ......................... 404, 519, 534, 548 rfpr ....................... 397, 519, 534, 548 rsr ................................................. 316 rstcsr .................. 307, 532, 546, 557 rxpr....................... 396, 519, 534, 548 sar ................................................. 107 sbycr .................... 490, 528, 542, 554 sckcr .................... 478, 528, 542, 554 scmr ...................... 330, 532, 546, 557 scr ......................... 321, 532, 546, 557 smr......................... 317, 532, 546, 557 ssr .......................... 324, 532, 546, 557 syscr ...................... 53, 528, 542, 554 tbr ................. 251, 527, 541, 553, 554 tcnr ...................... 249, 527, 541, 553 tcnt...............195, 250, 304, 527, 532, ......................... 541, 546, 55 3, 556, 557 tcr ......................... 166, 531, 545, 556 tcsr ....................... 305, 532, 546, 557 tdcnt .................... 251, 527, 541, 554 tddr ...................... 251, 527, 541, 553 tdr ......................... 316, 532, 546, 557 tec.......................... 404, 519, 534, 548 tgr ................ 195, 205, 251, 527, 531, ................................. 541, 545, 553, 556 tier ........................ 190, 531, 545, 556 tior ........................ 173, 531, 545, 556 tmdr..................... 171, 248, 527, 531, ................................. 541, 545, 553, 556 tpbr ....................... 251, 527, 541, 553 tpdr ....................... 251, 527, 541, 553 tsr ................. 192, 250, 31 6, 527, 531, ................................. 541, 545, 553, 556 tstr........................ 195, 530, 545, 556 tsyr ....................... 196, 530, 545, 556 txack.................... 394, 519, 534, 548 txcr....................... 393, 519, 534, 548 txpr ....................... 392, 519, 534, 548 umsr ...................... 405, 519, 534, 548 reset.......................................................... 59 serial communication interface ............. 313 asynchronous mode ........................ 338 bit rate .............................................. 331 break................................................ 377 framing er ror.................................... 345 mark state........................................ 377 overrun error .................................... 345 parity error ....................................... 345 stack pointer (sp)...................................... 22 time quanta (tq)................................... 416 trace bit ................................................... 23 trapa instruction ............................. 44, 63 watchdog ti mer ..................................... 303 interval timer mode........................ 308 overflows ......................................... 308 renesas 16-bit single- chip microcomputer hardware manual h8s/2612 group, h8s/2612 f-ztat publication date: 1st edition, september 2000 rev.7.00, september 11, 2009 published by: sales strategic planning div. renesas technology corp. edited by: customer support department global strategic communication div. renesas solutions corp. ? 2009. renesas technology corp., all rights reserved. printed in japan. sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com refer to " http://www.renesas.com/en/network " for the latest and detailed information. renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500, fax: <1> (408) 382-7501 renesas technology europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k. tel: <44> (1628) 585-100, fax: <44> (1628) 585-900 renesas technology (shanghai) co., ltd. unit 204, 205, aziacenter, no.1233 lujiazui ring rd, pudong district, shanghai, china 200120 tel: <86> (21) 5877-1818, fax: <86> (21) 6887-7858/7898 renesas technology hong kong ltd. 7th floor, north tower, world finance centre, harbour city, canton road, tsimshatsui, kowloon, hong kong tel: <852> 2265-6688, fax: <852> 2377-3473 renesas technology taiwan co., ltd. 10th floor, no.99, fushing north road, taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 3518-3399 renesas technology singapore pte. ltd. 1 harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas technology korea co., ltd. kukje center bldg. 18th fl., 191, 2-ka, hangang-ro, yongsan-ku, seoul 140-702, korea tel: <82> (2) 796-3115, fax: <82> (2) 796-2145 renesas technology malaysia sdn. bhd unit 906, block b, menara amcorp, amcorp trade centre, no.18, jln persiaran barat, 46050 petaling jaya, selangor darul ehsan, m alaysia tel: <603> 7955-9390, fax: <603> 7955-9510 renesas sales offices colophon 6.2 h8s/2612 group, h8s/2612 f-ztat rej09b0211-0700 hardware manual 1753, shimonumabe, nakahara-ku, kawasaki-shi, kanagawa 211-8668 japan |
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